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Uf"^ 



September 1978 

Contains descriptions of individual 
microprocessors and support devices used 
only witti the parent microprocessor 






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UN INTRODUCTION 
TO MICnOCOMPUTCRS 
VOLUM6 2 

SOM€ R€RL MICROPftOC€SSORS 



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y ildom Osborne 
ith Jerry Kcine 



Osborne & Associates, inc. 
Berkeley, California 



Library of Congress Catalogue Card Number 76-374891 
ISBN 0-931988-15-2 



Copyright © 1975, 1976, 1977, 1978 by Adam Osborne and Associates, Incorporated 



All rights reserved. Printed in the United States of America. No part of this publication may be reproduced, 
stored in a retrieval system, or transmitted in any form, or by any means, electronic, mechanical, photocopy- 
ing, recording or otherwise, without the prior written permission of the publishers. Original bound volume of 
AN INTRODUCTION TO MICROCOMPUTERS series published in 1975. 



o 



Published By 

z Adam Osborne & Associates, Inc. 

g P.O. Box 2036 

g Berkeley, California, U.S.A. 94702 

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@ 



DISTRIBUTORS OF OSBORNE & ASSOCIATES, INC. PUBLICATIONS 

For information on translations and on book distributors outside of the United States of America, 
please call or write: 

Osborne & Associates, Inc. 

P.O. Box 2036 

Berkeley, California 94702 

United States of America 

(415) 548-2805 

TWX 910-366-7277 



CONTRIBUTING AUTHORS 

The following persons have contributed in the writing of sections of this book in addition to its principal 
authors: 

Susanna Jacobson 
ui Osborne & Associates, Inc. 

< Curt Ingraham 

g Osborne & Associates, Inc. 

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TABLE OF CONTENTS 

CHAPTER PAGE 

1 4-Bit Microprocessors and the TMS1 000 Series Microcomputers 1-1 

^ TMS1 000 Programmable Registers 1-3 

^ TMS1 000 Memory Addressing Mode 1-5 

2 TMS1000 Status Flags 1-5 

g TMS1000 Input and Output Logic 1-5 

o TMS1000 Series Microcomputer Pins and Signals 1-6 

- TMS1 000 Series Microcomputer Instruction Execution 1-10 

lu TMS1 000 Series Microcomputer Instruction Set 1-10 

< The Benchmark Program 1-10 

o Datasheets 1-D1 

o 

» 2 The Mosteic 3870 (and Fairchild F8) 2-1 

«B The 3870 One-Chip Microcomputer 2-3 

z 3870/F8 Programmable Registers 2-5 

g 3870 Memory Addressing Modes 2-6 

g 3870/F8 Status Flags . 2-9 

o 3870 Pins and Signals 2-9 

5 3870 Instruction Timing and Execution 2-11 

Q 3870 I/O Ports 2-11 

^ 3870 Interrupt Logic 2-13 

^ Timer/Counter Logic 2-15 

The 3870 Control Code 2-17 

The 3870/F8 Instruction Set 2-19 

The 3870 Benchmark Program 2-26 

The 3850 CPU 2-29 

F8 Programmable Registers and Status Flags 2-31 

F8 Addressing Modes 2-31 

F8 Clock Circuits 2-32 

F8 CPU Pins and Signals 2-34 

F8 Timing and Instruction Execution 2-35 

F8 I/O Ports 2-37 

A Summary of F8 Interrupt Processing 2-37 

The F8 Instruction Set 2-37 

The Benchmark Program 2-38 

The 3851 Program Storage Unit (PSU) 2-39 

The 3851 PSU Read-Only Memory 2-40 

3851 PSU Input/Output Logic 2-41 

3851 PSU Interrupt Logic 2-42 

3851 PSU Programmable Timer Logic 2-45 

3851 PSU Data Transfer Timing 2-45 

Using the 3851 PSU in Non-F8 Configurations 2-45 

The 3861 and 3871 Parallel I/O (PIO) Devices 2-47 

The 3856 and 3857 16K Programmable Storage Units (16K PSU) 2-47 

Additional F8 Support Devices 2-49 

The 3852 Dynamic Memory Interface (DMI) 2-49 

The 3854 Direct Memory Access (DMA) Device 2-53 

The 3853 Static Memory Interface (SMI) 2-54 

Data Sheets 2-D1 . 

3 The National Semiconductor SC/MP 3-1 

SC/MP Programmable Registers 3-3 

Addressing Modes 3-4 

SC/MP Status Register 3-5 

SC/MP CPU Signals and Pin Assignments 3-5 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 

3 (Cont.) SC/MP Timing and Instruction Execution - 3-7 

SC/MP Bus Access Logic 3-8 

SC/MP Input/Output Operations 3-10 

The SC/MP Halt State 3-13 

SC/MP Interrupt Processing 3-14 

SC/MP DMA and Multiprocessor Operations 3-17 

The SC/MP Reset Operation 3-21 

SC/MP Serial Input/Output Operations 3-21 

The SC/MP Instruction Set 3-22 

The Benchmark Program 3-28 

Support Devices for the SC/MP CPU 3-29 

UsingOther Microcomputer Support Devices with the SC/MP CPU 3-31 

Datasheets 3-D1 

4 The8080A 4-1 

The8080ACPU 4-3 

8080A Programmable Registers 4-3 

8080A Addressing Modes 4-4 

8080A Status 4-5 

8080A CPU Pins and Signals 4-6 

8080A Timing and Instruction Execution 4-7 

Clock Signals 4-8 

Instruction Fetch Sequence 4-12 

A Memory Read or Write Operation 4-12 

Separate Stack Memory Modules 4-12 

The Wait State 4-13 

The Wait, Hold and Halt States 4-16 

The Hold State 4-17 

The Halt State and Instruction 4-19 

The Reset Operation 4-19 

External Interrupts ' 4-21 

External Interrupts During the Halt State 4-24 

Wait and Hold Conditions Following an Interrupt 4-24 

The 8080A Instruction Set 4-24 

The Benchmark Program 4-25 

Instruction Execution Times and Codes ' 4-33 

SupportDevicesthat may be Used with the 8080A 4-46 

The 8224 Clock Generator and Driver 4-46 

The 8224 Clock Generator Pins and Signals 4-46 

The 8228 and 8238 System Controller and Bus Driver 4-48 

Bus Driver Logic 4-48 

Control Signal Logic 4-49 

8228 System Controller Pins and Signals 4-49 

The 8259 Priority Interrupt Control Unit (PICU) 4-52 

8259 PICU Pins and Signals 4-52 

The 8259 PICU Interrupt Acknowledge Vector 4-54 

8259 PICU Priority Arbitration Options 4-57 

Howlnterrupt Requests and Priority Status are' Recorded 4-60 

Programming the 8259 PICU 4-62 

TheTMS 5501 Multifunction Input/Output Controller 4-67 

TMS 5501 Device Pins and Signals 4-67, 

TMS 5501 Device Access 4-70' 

TMS 5501 Interrupt Handling 4-74 

TMS 5501 Parallel I/O Operations 4-75 

TMS 5501 Serial I/O Operation 4-75 

TMS 5501 Interval Timers 4-76 

Datasheets 4-D1 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 

5 The 8085 5-1 

The8085ACPU 5-2 

2 8085A Programmable Registers 5-3 

5 8085A Addressing Modes 5-3 

§ 8085A Status 5-3 

^ 8085A CPU Pins and Signals 5-3 

8 A Comparison of 8085A and 8080A Signals 5-7 

2 8085A Timing and Instruction Execution 5-7 

to The Clock Signals 5-8 

h- Memory Access Sequences 5-9 

^ Bus Idle Machine Cycles 5-18 

o The Wait State 5-20 

« The SID and SOD Signals 5-21 

^ The Hold State 5-24 

lu TheHalt State and Instruction 5-26 

tc External Interrupts 5-28 

S The Reset Operation 5-32 

g The 8085A Instruction Set 5-34 

5 8085A Microprocessor Support Devices 5-35 

< The 81 55/81 56 Static Read/Write Memory with I/O Ports and Timer 5-35 

< 81 55/81 56 Device Pins and Signals 5-35 
(g) 81 55/81 56 Parallel Input/Output 5-38 

8155/8156 Device Addressing 5-39 

The 8155/81 56 Counter/Timer 5-41 

81 55/81 56 Control and Status Registers 5-43 

8155/8156 Device Programming 5-43 

The 8355 Read-only Memory with I/O 5-45 

8355 Device Pins and Signals 5-45 

8355 Ready Logic 5-49 

8355 I/O Logic 5-50 

The 8755A Erasable Programmable Read-Only Memory with I/O 5-51 

Datasheets 5-D1 

6 The 8048 Microcomputer Devices 6-1 

The 8048, 8748. 8049. 8749 and 8035 Microcomputers 6-2 

An 8048 and 8049 Functional Overview 6-3 

8048. 8748, and 8035 Microcomputer Programmable Registers 6-7 

8048 Series Addressing Modes 6-8 

A Program Memory Map 6-12 

8048 Series Status 6-13 

8048 Series Microcomputer Operating Modes 6-14 

8048 Series Microcomputer Pins and Signals 6-15 

8048 Series Timing and Instruction Execution 6-18 

Internal Execution Mode 6-18 

External Memory Access Mode 6-20 

Debug Mode 6-23 

Single Stepping 6-23 

Programming Mode 6-24 

Verification Mode 6-26 

Input/Output Programming 6-26 

Hold State 6-26 

Counter/Timer Operations 6-27 

Internal and External Interrupts 6-27 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 

6 (Cont.) The 8048 Microcomputer Series Instruction Set 6-32 

The Benchnnarl< Program 6-32 

The 8041 Slave Microcomputer 6-41 

An 8041 Functional Overview 6-42 

8041 Data Bus Logic 6-43 

8041 I/O Ports One and Two 6-44 

8041 and 8741 Programmable Registers 6-44 

8041 and 8741 Addressing Modes 6-44 

8041 and 8741 Status 6-45 

8041 and 8741 Slave Microcomputer Operating Modes 6-45 

8041 and 8741 Pins and Signals . 6-45 

8041 Series Timing and Instruction Execution 6-46 

8741 Single Stepping and Programming Mode 6-46 

8041 Input/Output Programming 6-46 

8041 Counter/Timer Operations 6-47 

8041 Interrupt Logic 6-47 

Programming 8048-8041 Data Transfers 6-47 

The 8041/8741 Instruction Set 6-49 

The 8021 Single-Chip Microcomputer 6-51 

An 8021 Functional Overview 6-51 

8021 I/O Port Pins 6-51 

TheTI Pin 6-51 

The 8021 Reset Input 6-52 

The 8021 Clock Inputs 6-53 

The 8021 Timer/Counter 6-53 

8021 Scratchpad Memory and Programming 6-53 

The 8243 Input/Output Expander 6-53 

8243 Input/Output Expander Pins and Signals 6-53 

8243 Input/Output Expander Operations 6-55 

Datasheets 6-D1 

7 2iIogZ80 7-1 

TheZSOCPU 7-1 

A Summary of Z80/8080A Differences 7-1 

Z80 Programmable Registers 7-5 

Z80 Addressing Modes ' ' 7-6 

Z80 Status 7-7 

Z80 CPU Pins and Signals 7-7 

Z80-8080A Signal Compatibility 7-9 

Z80 Timing and Instruction Execution 7-11 

Instruction Fetch Execution Sequences 7-12 

A Memory Read Operation 7-13 

Memory Write Operation 7-13 

The Wait State 7-14 

Input or Output Generation 7-14 

Bus Requests 7-15 

External interrupts 7-16 

The Halt Instruction 7-19 

The Z80 Instruction Set 7-38 

Input/Output Instructions 7-38 

Primary Memory Reference instructions 7-39 

BlockTransfer and Search instructions 7-39 

Secondary Memory Reference (Memory Operate) Instructions 7-41 

Immediate instructions 7-41 

Jump Instructions 7-41 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 
7 (Cont.) Subroutine Call and Return Instructions . 7-41 

Immediate Operate Instructions 7-41 

Q Jump-on-Condition Instructions 7-41 

H Register-Register Move Instructions 7-42 

a Register-Register Operate Instructions 7-42 

2 Register Operate Instructions 7-42 

o Bit Manipulation Instructions 7-42 

^ Stack Instructions 7-43 

~ Interrupt Instructions 7-43 

111 Status and Miscellaneous Instructions 7-44 

< The Benchmark Program 7-44 
g Support Devices that may be Used with the Z80 7-44 
« The Z80 Parallel I/O Interface (PIO) 7-45 

< Z80 PIO Pins and Signals 7-46 
•3 Z80 PIO Operating Modes 7-49 
2 Z80 PIO Interrupt Servicing 7-51 

Programming the Z80 PIO 7-52 
S The Z80 Clock Timer Circuit (CTC) 7-54 
° Z80 CTC Functional Organization 7-54 

1 Z80 CTC Pins and Signals 7-55 
Q Z80 CTC Operating Modes 7-57 
^ Z80CTC!nterrupt Logic 7-60 
^ Programming the Z80 CTC 7-60 

Datasheets 7-D1 

9 The Motorola MC6800 9-1 

TheMC6800CPU 9-3 

The MC6800 Programmable Registers 9-3 

MC6800 Memory Addressing Modes 9-3 

MC6800 Status Flags 9-5 

MC6800 CPU Pins and Signals 9-6 

MC6800 Timing and Instruction Execution 9-7 

The Hold State, the Halt State and Direct Memory Access 9-10 

Interrupt Processing, Reset and the Wait State 9-12 

The MC6800 Instruction Set 9-16 

The Benchmark Program 9-17 

MC6800Summary of Cycle by Cycle Operation 9-25 

Support Devices that may be Used with the MC6800 9-31 

The MC6802 CPU with Read/Write Memory 9-33 

The MC6870 Two Phase Clocks 9-39 

The MC6870A Clock Device 9-41 

The MC6871A Clock Device 9-41 

The MC6871B Clock Device 9-43 

THeMC6875 Clock Device 9-44 

Some Standard Clock Signal Interface Logic 9-44 

The MC6820 and MCS6520 Peripheral Interface Adapter (PIA) 9-45 

The MC6820PIA Pins and Signals 9-45 

MC6820 Operations 9-48 

The MC6850 Asynchronous Communications interface Adapter (ACIA) 9-55 

The MC6850ACIA Pins and Signals 9-55 

MC6850 Data Transfer and Control Operations 9-57 

MC6850 ACIA Control Codes and Status Flags 9-59 

The MC6852 Synchronous Serial Data Adapter (SSDA) , 9-61 

MC6852SSDA Pins and Signals 9-61 

MC6852 Data Transfer and Control Operations 9-63 

MC6852 Status Register 9-65 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 

9 (Cont.) The MC6852 Control Registers 9-66 

Programming the MC6852 9-70 

The MC8507 (or MC6828) Priority Interrupt Controller (PIC) 9-71 

MC6828 Pins and Signals 9-72 

Thelnterrupt Acknowledge Process 9-74 

Interrupt Priorities 9-75 

Interrupt Inhibit Logic 9-77 

The MC6840 Programmable Counter/Timer 9-78 

The MC6840Counter/Timer Pins and Signals 9-78 

MC6840 Addressing 9-82 

MC6840 Counter/n"imer Programmable Options 9-94 

The MC6844 Direct Memory Access Controller 9-106 

MC6844 DMA Controller Pins and Signals 9-107 

MC6844 Addressable Registers 9-109 

MC6844 DMA Transfer Modes 9-110 

MC6844DMAC Three-State Control, Cycle Stealing Mode 9-111 

MC6844DMAC Halt Modes 9-113 

Comparing MC6844DMAC Modes 9-116 

Using an MC6844DMAC with Mixed Modes 9-116 

The MC6844 Control Registers and Operating Options 9-1 1 6 

Resetting the MC6844 DMAC 9-122 

Programming the MC6844DMAC 9-122 

The MC6846 Multifunction Support Device 9-124 

MC6846 Multifunction Device Pins and Signals 9-124 

MC6846Counter/rimer Logic 9-127 

MC6846 I/O Port Logic 9-128 

MC6846 Device Reset 9-129 

Datasheets 9-D1 

10 The MOS Technology MCS6500 10-1 

The MCS6500 Series CPUs 10-2 

MCS6500 Series CPU Programmable Registers 10-3 

MCS6500 Memory Addressing Modes 10-4 

MCS6500 Status Flags 10-6 

MCS6500 CPU Pins and Signals 10-7 

MCS6500 Timing and Instruction Execution 10-13 

Interrupt Processing and System Reset 10-15 

MCS6500 CPU Clock Logic 10-15 

MCS6500 CPU interface Logic 10-15 

The MCS6500 Instruction Set 10-16 

The Benchmark Program 10-16 

Support Devices that may be Used with the MCS6500 Series Microprocessors 1 0-27 

The MCS6522 Peripheral Interface Adapter 10-29 

MCS6522PIA Pins and Signals 10-30 

MCS6522 Parallel Data Transfer Operations 10-33 

MCS6522 Interval Timer Logic 10-36 

MCS6522 Shifter Logic 10-42 

MCS6522 Interrupt Logic 10-46 

The MCS6530 Multifunction Support Logic Device 10-47 

MCS6530 Multifunction Device Pins and Signals 10-47 

MCS6530 Parallel Data Transfer Operations 10-51 

MCS6530 Interval Timer and Interrupt Logic 10-51 

The MCS6532 Multifunction Support Logic Device 10-53 

MCS6532 Multifunction Device Pins and Signals 10-54 

MCS6532 Logic Functions 10-55 

Datasheets 10-D1 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 

11 The Signetics 2650A 11-1 

The 2650A CPU Logic 11-1 

2650A Programmable Registers 11-3 

Q The 2650A Memory Addressing Modes 11-4 

H The 2650A Status Flags 11-8 

c The 2650A CPU Pins and Signals 11-10 

2 Interfacing Memory to the 2650A Microcomputer 11-12 

o Interfacing I/O Devices to the 2650A Microcomputer 11-12 

2 The 2650A Microcomputer Instruction Process 11-12 

~ 2650A Microcomputer Direct Memory Access 11-14 

w The 2650A Microcomputer Instruction Set 11-14 

< The 2650A Benchmark Program 11-15 

g Support Devices that may be Used with the 2650A Microprocessor 1 1 -23 

w Datasheets 11-D1 

< 

.a 12 TheRCACOSMAC 12-1 

z TheCOSMACCPU 12-2 

COSMAC Programmable Registers 12-2 
w COSMAC Memory Addressing Modes 12-4 
° COSMAC Status Flags 12-5 

1 COSMAC CPU Pins and Signals 12-5 
5 COSMAC Timing and Instruction Execution 12-8 
/-J COSMAC Memory Read Timing 12-11 
^ COSMAC Memory Write Instruction Timing 12-11 

COSMAC Data Input, Data Output, and Direct Memory Access 12-12 

A Summary of COSMAC Interrupt Processing 12-17 

The COSMAC Instruction Set 12-17 

The Benchmark Program 12-23 

Using COSMAC with Other Microprocessor Support Devices 12-32 

The CDP1852 Parallel I/O Port 12-33 

CDP1852 Pins and Signals 12-33 

CDP1852 Operations Overview 12-33 

CDP1852 Input Operations 12-34 

CDP1 852 Output Operations 12-37 

Datasheets 12-D1 

13 IM6100 Microcomputer Devices 13-1 

ThelM6100CPU 13-2 

IM6100 Programmable Registers 13-3 

IM6100 Memory Space 13-3 

IM61 00 Memory Addressing Modes 13-3 

IM61 00 Status Flags 13-6 

IM6100 CPU Pins and Signals 13-6 

IM6100 Timing and Instruction Execution 13-9 

IM6100NoOperationMachineCycle 13-10 

IM6100 Data Input Machine Cycle 13-10 

IM6100 Data Output Machine Cycle 13-10 

IM6100 Address Demultiplexing 13-11 

IM61 00 Memory Read Machine Cycle Timing 13-13 

IM6100 Memory Write Machine Cycle 13-14 

IM6100 Input/Output Timing 13-18 

IM61 00 Wait State 13-22 

IM61 00 Hold and Halt Conditions 13-23 

IM6100 Direct Memory Access 13-26 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 

13(Cont.) The IM6100 Reset 13-29 

IM61 00 Interrupt Logic 13-29 

IM6100 Control Panel Logic 13-33 

External Control Signal Priorities 13-37 

IM6100 Instruction Set 13-37 

The IM6100 Benchmark Program, 13-38 

Some Special IM61 00 Hardware Considerations 13-47 

Implementing a Hardware Stack 13-47 

Support Devices that may be Used with the IM61 00 13-51 

The IM61 01 Parallel Interface Element (PIE) 13-53 

IM6101 Parallel Interface Element Pins and Signals 13-55 

IM61 01 Functional Logic 13-56 

IM6101 Interrupt Handling Logic ■ 13-62 

The IM61 02 MEDIC 13-64 

IM6102 MEDIC Pins and Signals 13-65 

The IM6100-IM6102 Interface 13-69 

IM61 02 Extended Memory Control 13-69 

IM61 02 Extended Memory Programming Considerations 13-77 

IM61 02 Extended Memory Interrupt Considerations 13-78 

IM6102 Dynamic Memory Refresh and Direct Memory Access Logic 13-79 

IM6102 Programmable Real-Time Clock Logic 13-83 

IM6102MEDICInstructions 13-85 

Datasheets 13-D1 

14 The 8X300 {or SMS300) 14-1 

The 8X300 Microcontroller 14-1 

8X300 Addressable Registers 14-3 

8X300 Status Flags 14-4 

8X300 Memory Addressing 14-4 

8X300 Pins and Signals 14-5 

8X300 Instruction Execution and Timing 14-6 

The 8X300 Instruction Set 14-9 

The 8X300 Benchmark Program 14-17 

The8T32,8T33,8T35. and 8T36 Interface Vector Byte (IV Byte) 14-21 

8T32/3/5/6 IV Byte Pins and Signals 14-21 

8T32/3/5/6 IV Byte Operation 14-23 

8T32/3/5/6 IV Byte Addresses 14-24 

The 8T39 and 8T58 Bus Expanders 14-26 

Datasheets 14-D1 

15 The National Semiconductor PACE and INS8900 15-1 

PACE and INS8900 Microcomputer System Overviews 15-2 

INS8900 Programmable Registers 15-4 

INS8900 Stack 15-5 

INS8900 and PACE Addressing Modes 15-6 

INS8900 and PACE Status and Control Flags 15-9 

iNS8900 and PACE CPU Pins and Signals 15-10 

INS8900 and PACE Timing and Instruction Execution 15-1 1 

The Initialization Operation 15-14 

The Halt State and Processor Stall Operations 15-14 

Direct Memory Access Operations 15-15 

The INS8900 and PACE Interrupt System 15-19 

The INS8900 and PACE Instruction Set 15-24 

The Benchmark Program 15-33 

The PACE DP8302 System Timing Element (STE) 15-35 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 

15{Cont.) The PACE Bidirectional Transceiver Element (BTE) 15-36 

Using Other Microcomputer Support Devices with the PACE and INS8900 15-38 

g Datasheets 15-D1 

^ 16 The General Instrument CP1 600 16-1 

0. The CP1 600 Microcomputer System Overview 16-1 

o CP1 600 Programmable Registers 16-3 

2 CP1600 Memory Addressing Mode 16-3 

~- CP1600 Status and Control Flags 16-6 

ifi CP1 600 CPU Pins and Signals 16-6 

< CP1 600 Instruction Timing and Execution 16-10 
g CP1 600 Memory Access Timing 16-10 
^ The CP1 600 Wait State 16-12 

< The CP1 600 Halt State 16-12 
2 CP1 600 Initialization Sequence 16-13 
z CP1600 DMA Logic 16-13 
o The CP1 600 Interrupt Logic 16-15 
w The CP1600 Instruction Set 16-16 
^ The Benchmark Program 16-25 

< Support Devices that may be Used with the CP1 600 16-27 
5 The CP1680 Input/Output Buffer (JOB) 16-30 
Q CP1680IOB Pins and Signals 16-30 

CP1 680 Addressable Registers 16-31 

The CP1 680 Control Register 16-32 

CP1 680 Data Transfer Operations 16-33 

The CP1 680 Interval Timer 16-36 

CP1 680 Interrupt Logic 16-37 

Datasheets 16-D1 

17 The General Instrument 1650 Series Microcomputers 17-1 

A 1650 Functional Overview 17-1 

1650 Series Microcomputer Programmable Registers 17-4 

1650 Series Microcomputer Memory Addressing Modes 17-6 

1650 Series Microcomputer Pins and Signals 17-6 

1650 Series Microcomputer Instruction Set 17-8 

The 1650 Benchmark Program 17-9 

Datasheets 17-D1 

18 The Texas I nstrumentsTMS 9900, TMS 9980, and TMS 9440 Products 18-1 

The TMS 9900 Microprocessor 1 8-2 

A TMS 9900 Functional Overview 18-2 

TMS 9900 Programmable Registers 18-3 

TMS 9900 Memory Addressing Modes 18-6 

TMS 9900 I/O Addressing 1 8-8 

TMS 9900 CPU Pins and Signals 18-13 

TMS 9900 Timing and Instruction Execution ^8-.^5 

Memory Access Operations 18-15 

Memory Select Logic 18-19 

TMS 9900 I/O Instruction Timing 18-20 

The Wait State 18-23 

The Hold State 18-25 

The Halt State 18-25 

TMS 9900 Interrupt Processing Logic 18-26 

The TMS 9900 Reset 18-34 

The TMS 9900 Load Operation 18-34 



TABLE OF CONTENTS (Continued) 

CHAPTER PAGE 

18(Cont.) The TMS 9900 Instruction Set 18-35 

The Benchmark Program 18-42 

The TMS 9980A and the TMS 9981 Microprocessors 18-44 

TMS 9980 Series Microprocessor Pins and Signals 18-45 

TMS 9980 Series Microprocessor Timing and Instruction Execution 1 8-49 

TMS 9980 Series Interrupt Logic 1 8-49 

The TMS 9980 Series Instruction Set 18-52 

The TMS 9940 Single-Chip Microcomputers 18-52 

TMS 9940 Registers and Read/Write Memory 1 8-54 

TMS 9940 CPU Pins and Signal Assignments 18-56 

TMS 9940 General Purpose Flags 18-65 

TMS 9940 Timer/Event Counter Logic 18-65 

TMS 9940 Interrupt Logic 18-65 

TMS 9940 Reset 18-65 

Programming a TMS 9940E Erasable Programmable Read-Only Memory 1 8-66 

Loading a Program into TMS 9940 Read/Write Memory 1 8-66 

The TMS 9940 Instruction Set 18-66 

The TIM 9904 Four-Phase Clock Generator/Driver 18-67 

The TMS 9901 Programmable System Interface (PSD 18-70 

TMS 9901 Pins and Signals 18-73 

TMS 9901 PSI Interrupt Logic 18-76 

TMS 9901 Data Input and Output 18-78 

TMS 9901 Real-Time Clock Logic 18-80 

TMS 9901 Reset Logic 18-81 

Datasheets 18-D1 

19 Single Chip Nova Minicomputer Central Processing Units 19-1 

A Product Overview 19-2 

Nova Programmable Registers 19-4 

Nova Memory Addressing Modes 19-5 

Nova Status Flags 19-10 

MicroNova and 9440 CPU Pins and Signals 19-10 

CPU Logic and Instruction Execution, '19-17 

Arithmetic/Logic Instructions 19-17 

Memory Reference Instructions 19-20 

Input/Output Instructions 19-20 

A Nova Summary 19-22 

9440 Timing and Instruction Execution 19-23 

MicroNova and 9440 Interrupt Processing 19-27 

MicroNova and 9440 Direct Memory Access Logic 19-31 

The MicroNova and 9440 Instruction Sets 1 9-32 

The Benchmark Program 19-32 

Datasheets 19-D1 

20 The Intel 8086 20-1 

The 8086 CPU 20-3 

8086 Programmable Registers and Addressing Modes 20-3 

8086 Status 20-17 

8086 CPU Pins and Signals 20-19 

8086 Timing and Instruction Execution 20-25 

8086 Bus Cycles 20-26 

8086 Instruction Queue 20-27 

8086 Memory and I/O Device Read Bus Cycle for Simple Configurations 20-30 

8086 Memory or I/O Device Write Bus Cycle for Minimum Mode 20-31 

8086 Read and Write Bus Cycles for Maximum Mode 20-32 



TABLE OF CONTENTS (Continued) 



CHAPTER PAGE 

20(Cont.) The 8086 Wait State 20-34 

The 8086 Hold State 20-34 

Q The 8086 Halt State 20-36 

b The 8086 Lock 20-37 

g The 8086 Processor Wait for Test State 20-38 

2 The 8086 Processor Escape 20-38 

The 8086 Reset Operation 20-38 
z 8086 Interrupt Processing 20-38 
"• Single Stepping Mode 20-41 
w The 8086 Instruction Set 20-41 

< 8086-8080A Instruction Compatibility 20-48 
^ The Benchmark Program 20-48 
^ Instruction Execution Times and Codes 20-67 

< The Intel 8284 Clock Generator/Driver 20-77 
2 8284 Clock Generator/Driver Pins and Signals 20-77 

1 The Intel 8288 Bus Controller 20-80 
o 8288 Bus Controller Signals and Pin Assignments 20-80 
« The 8282/8283 8-Bit Input/Output Port 20-83 
° The 8282/8283 Input/Output Port Pins and Signal Assignments 20-83 

< The 8286/8287 8-Bit Bidirectional Bus Transceivers 20-85 
5 8286 and 8287 Bidirectional Bus Transceiver Pins and Signal Assignments 20-85 
g3) Some 8086 Microprocessor Bus Configurations 20-86 

Datasheets 20-D1 

22 2900 Series and 6700 Series Chip Slice Products 22-1 

The 2901/6701 Arithmetic and Logic Unit (ALU) 22-2 

The 2909 Microprogram Sequencer 22-5 

The 2902 Carry Look Ahead 22-8 

Datasheets 22-D1 

23 The IV1C10800 Series Chip Slice Logic 23-1 

The MC10800 Arithmetic and Logic Unit Slice 23-3 

The MCI 0801 Microprogram Control Unit 23-5 

The MCI 0802 Timing Device 23-6 

The MCI 0803 Memory Interface Device 23-6 

Datasheets 23-D1 

24 The Hewlett Packard MC2 24-1 

An MC2 System Overview 24-1 

MC2 Programmable Registers and Status 24-2 

MC2 Memory Addressing Modes 24-4 

Hardware Aspects of the MC2 24-4 

The MC2 Instruction Set 24-5 

The Benchmark Program 24-6 

25 Selecting a Microcomputer 25-1 

Designing Logic with Microcomputers — A Sequence of Events 25-2 

Microcomputer Development Hardware 25-3 

Microcomputer System Software 25-5 

An Economic Example 25-9 

A Look at the Future 25-10 



LIST OF FIGURES 

FIGURE PAGE 

1-1 Logic of the TMS1000 Series Microcomputer 1-2 

Q 1-2 TMS1000 and MC141000 Microcomputer Signals and Pin Assignments 1-6 

}u 1-3 TMS1 200 and MC141 200 Microcomputer Signals and Pin Assignments 1-7 

< 1-4 TMS1 070 Microcomputer Signals and Pin Assignments 1-7 

o 1-5 TMS1 270 Microcomputer Signals and Pin Assignments 1-8 

EC 1-6 TMS1 100 Microcomputer Signals and Pin Assignments 1-8 

o 1-7 TMS1 300 Micrqcomputer Signals and Pin Assignments 1-9 

2-1 A Fairchild/Mostek F8 Microcomputer System 2-2 

2-2 Logic of the Fairchild/Mostek 3870 Microcomputer 2-4 

2-3 3870 Microcomputer Signals and Pin Assignments 2-9 

o 2-4 Instructions That Move Data Between the Scratchpad and Various Registers 2-26 

2-5 Logic of the Fairchild F8 3850 CPU 2-30 

2-6 Fairchild 3850 CPU Signals and Pin Assignments 2-34 

2-7 Logic of the Fairchild F8 3851, 3856, and 3857 Programmable Storage Unit 2-39 

2-8 3851 PSU Signals and Pin Assignments 2-40 

g 2-9 Conceptual Logic to Include a 3851 PSU in a Non-F8 Microcomputer System 2-46 

2-10 3856 PSU Signals and Pin Assignments 2-48 

2-1 1 3857 PSU Signals and Pin Assignments 2-49 



S 



< 2-12 Logic of the Fairchild F8 3852 Dynamic Memory Interface (DMI), and of the 3854 

< Direct Memory Access (DMA) Devices 2-50 
@ 2-13 3852 DMI Signals and Pin Assignments 2-52 

2-14 3854 DMA Signals and Pin Assignments 2-54 

2-15 Logic of the F8 3853 Static Memory Interface (SMI) Device 2-55 

2-16 3853 SMI Signals and Pin Assignments 2-56 

3-1 Logic of the SC/MP Microcomputer 3-2 

3-2 SC/MP CPU Signals and Pin Assignments 3-6 

3-3 SC/MP Bus Access Logic Processing Sequence 3-9 

3-4 Bus Utilization of Each SC/MP Instruction 3-1 1 

3-5 SC/MP Data Input Cycle 3-12 

3-6 SC/MP Data Output Cycle 3-12 

3-7 NHOLD Signal Used to Lengthen SC/MP I/O Operation 3-13 

3-8 Circuit to Cause Programmed Halt for SC/MP CPU 3-13 

3-9 SC/MP Interrupt Instruction Fetch Process 3-14 

3-10 Using SC/MP in a System with Direct Memory Access 3-17 

3-1 1 One Method of Initializing an SC/MP Multiprocessor System 3-20 

3-12 Forcing the Halt State in an SC/MP Multiprocessor System 3-20 

3-13 An SC/MP System Showing Typical Support Devices that may be Required 3-29 

3-14 SC/MP Data Lines Buffered Using 8216 Devices 3-30 

4-1 The 8080A CPU. 8224 Clock and 8228 System Controller Forming a 

Three-Device Microprocessor 4-4 

4-2 8080A CPU Signals and Pin Assignments 4-8 

4-3 A Machine Cycle Consisting of Five Clock Periods 4-8 

4-4 Status Output During T2 of Every Machine Cycle 4-10 

4-5 8080A Instruction Fetch Sequence 4-13 

4-6 8080A Memory Write Timing 4-14 

4-7 The 8080A CPU Operating With Fast Memory and No Wait State 4-15 

4-8 The 8080A CPU Operating With Slow Memory and a Normal Wait State 4-16 

4-9A Floating of Data and Address Busses at $2 in T3, for READ Operation Being 

Completed Prior to Onset of Hold State 4-17 

4-9B Floating of Data and Address Busses at $2 in T4, for a WRITE, or Any Non-READ 

Operation (R/WO=False) 4-18 

4-1 OA Floating of Data and Address Busses for READ Operation in a Three Clock Period 

Machine Cycle 4-18 



LIST OF FIGURES (Continued) 

FIGURE PAGE 

4-1 OB Floating of Data and Address Busses at 02 in Ti , for WRITE or Any Non-READ 

Operation Being Completed Prior to Onset of Hold State' 4-18 

4-11 Interrupt initiation Sequence 4-20 

4-1 2 Signal Sequences and Tinning for Instructions: STC, CMC. CMA. NOP. RLC. RRC. RAL. BAR. 

XCHG. El. Dl.' DAA. ADD R. ADC R. SUB R. SBB R. ANA R. XRA R, ORA R. CMP R 4-33 
4-1 3 Signal Sequences and Timing for Instructions: INR. DCR. MOV REG REG. SPHL. PCHL. 

DCX. INX 4-34 

4-14 Signal Sequences and Timing for Instructions: DCR. INR.MVI M 4-34 

4-1 5 Signal Sequences and Timing for Instructions: LDAX. MOV REG M. ADI, ACl. SUI. SBI. 

ANl. XRI. ORI. CPI. MVI R. ADD M. ADC M. SUB M, SBB M. ANA M, XRA M. 

ORA M, CMP M 4-35 

4-16 Signal Sequences and Timing for Instructions: STAX. MOV M REG 4-35 

4-17 Signal Sequences and Timing for Instructions; LHLD 4-36 

4-18 Signal Sequences and Timing for Instructions: PUSH, RST 4-36 

4-19 Signal Sequences and Timing for Instructions: POP. RET • 4-37 

4-20 Signal Sequences and Timing for Instructions: DAD 4-38 

4-21 Signal Sequences and Timing for Instructions: XTHL 4-38 

4-22 Signal Sequences and Timing for Instructions: LXI. JMP, JNZ. JZ. JNC. JC, JPO. 

JPE. JP. JM ■ 4-39 

4-23 Signal Sequences and Timing for Instructions: STA ' 4-39 

4-24 Signal Sequences and Timing for Instructions: LDA 4-40 

4-25 Signal Sequences and Timing for Instructions: SHLD 4-40 

4-26 Signal Sequences and Timing for Instructions: CALL. CNZ. CZ. CNC. CC. CPO, CPE. 

CP.CM ■' ■ 4-41 

4-27 Signal Sequences and Timing for Instructions: RNZ. RZ. RNC. RC. RPO, RPE. RP, RM 4-42 

4-28 Signal Sequences and Timing for Instructions: IN 4-43 

4-29 Signal Sequences and Timing for Instructions: OUT 4-44 

4-30 Signal Sequences and Timing for Instructions: HLT 4-45 

4-31 8224 Clock Generator Signals and Pin Assignments 4-47 

4-32 8228 System Controller Signals and Pin Assignments 4-49 

4-33 A Standard. Three Device 8080A Microcomputer System 4-51 

4-34 Timing for Control Signals Output by the 8228 System Controller 4-51, 

4-35 8259Priority Interrupt Control Unit Signals and Pin Assignments 4-53 

4-36 A System With One PICU 4-54 

4-37 ^ A System With Three PICUs-Gne Master and Two Slaves 4-56 

4-38 Logicof the TMS 5501 Multifunction Input/Output Controller 4-68 

4-39 TMS 5501 Multifunction Input/Output Controller Signals and Pin Assignments 4-69 

5-1 Logic of the 8085A Microprocessor 5-2 

5-2 8085A CPU Signals and Pin Assignments 5-4 

5-3 A Comparison of 8085A and 8080A/8224/8228Signailnterface 5-6 

5-4 A Four Clock Period Instruction Fetch Machine Cycle 5-9 

5-5 A Six Clock Period Instruction Fetch Machine Cycle 5-10 

5-6 A Memory Read Machine Cycle Following an Instruction Fetch 5-15 

5-7 An I/O Read Machine Cycle Following an Instruction Fetch 5-16 

5-8 A Memory Write Machine Cycle Following an Instruction Fetch 5-17 

5-9 An I/O Write Machine Cycle Following an Instruction Fetch 5-18 

5-10. A Bus Idle Machine Cycle Following an Instruction Fetch During Execution of a 

DAD Instruction 5-19 

5-11 Wait States Occurring in a Memory Read Machine Cycle 5-20 

5-12 A RIM Instruction Followed by a SIM Instruction 5-23 

5-13 A Hold State Following a Single Machine Cycle Instruction Execution 5-23 

5-14. A Halt Instruction and a Halt State Terminated by an Interrupt Request 5-26 

5-15 Hold States Occurring Within a Halt State 5-27 

5-16 An Interrupt Being Acknowledged Using a Single Byte Instruction 5-28 

5-17 A Bus Idle Instruction Fetch Machine Cycle 5-30 

5-18 Power On and RESET IN Timing for the 8085A 5-31 





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LIST OF FIGURES (Continued) 

FIGURE PAGE 

Logic of the 81 55 and 81 56 Multifunction Devices 5-36 

Logic Functions of the 81 55/8156 Device 5-37 

8155/8156 Multifunction Device Signals and Pin Assignments 5-37 

An 81 55 Device Connected to an 8085A CPU Bus 5-38 

Logic of the 8355 and 8755 Multifunction Devices 5-46 

Logic Functions of the 8355 Device 5-47 

8355 Multifunction Device Signals and Pin Assignments 5-48 

An 8085A-81 55/81 56-8355 Microcomputer System 5-48 

8755A Multifunction Device Signals and Pin Assignments 5-52 

Logic of the 8048 Series Microcomputers 6-3 

Functional Logic of the 8048, 8049, 8748, 8749, and 8035 Microcomputers 6-4 

8048 I/O Ports '1 and 2 Pin Logic 6-6 

8048 Series Microcomputers' Memory Addressing 6-9 

8048, 8748 and 8035 Microcomputer Pins and Signals 6-16 

Execution of 8048 Single Machine Cycle Instructions Without any External Access 6-19 

An 8048 Series Externallnstruction Fetch 6-19 

An 8048 Series External Data Read or Write 6-20 

An 8048-8355 Configuration 6-21 

Demultiplexing DB0-DB7 to Create Separate Address and Data Busses 6-21 

An 8048 Single Step Circuit 6-24 

^ 6-12 8748 EPROM Programming and Verification Timing 6-25 

6-13 An Eight-Device Daisy Chained Interrupt Request/Acknowledge Scheme 6-29 

6-14 A Low Chip Implementation of an Eight-Device Daisy Chained Interrupt 

Request/Acknowledge Scheme 6-31 

6-15 A Comparison of 8048 and 8041 Functional Logic 6-42 

6-16 8041 and 8741 Microcomputer Pins and Signals 6-45 

6-17 A Comparison of 8048 and 8021 Functional Logic 6-50 

6-18 8021 Microcomputer Pins and Signals 6-52 

6-19 Logic of the 8243 Input/Qutput Expander 6-54 

6-20 Input/Output Expander Pins and Signals 6-55 

6-21 Functional Diagram of the 8243 Input/Output Expander 6-56 

6-22 An 8243/8048 Configuration with External Logic Read and Write Strobes 6-57 

6-23 ' Timing for Data Output to an 8243 Port Via an MOVD, ORLD, or ANLD Instruction 6-58 

6-24 Timing for Data Input from an 8243 Port 6-58. 

7-1 Logic Functions of the Z80 CPU 7-2 

7-2 The Standard 8080A Three-Chip System and Z80 Signal Equivalents 7-3 

7-3 Z80 Programmable Registers 7-5 

7-4 Z80 CPU Signals and Pin Assignments 7-8 

7-5 Z80 Instruction Fetch Sequence 7-12 

7-6. Z80 Memory Read Timing 7-13 

7-7 Z80 Memory Write Timing 7-13 

7-8 Z80 Wait State Timing 7-14 

7-9 Z80 Input or Output Cycles 7-15 

7-10 Z80 Input or Output Cycles with Wait States 7-15 

7-11 Z80 Bus Timing 7-16 

7-12 ZSOResponse to a Maskable Interrupt Request 7-16 

7-13 Wait States During Z80 Response to a Maskable Interrupt Request 7-18 

7-14 ZBOResponse to a Nonmaskable Interrupt Request 7-19 

7-15 Z80 Halt Instruction Timing 7-19 

7-16 Logic Functions of the Z80PIO 7-46 

7-17 Z80PIO Signals and Pin Assignments 7-48 

7-18 Mode (Output) Timing 7-50 

7-19 Mode 1 (Input) Timing 7-51 

7-20 PortA, Mode 2 (Bidirectional) Timing 7-51 



LIST OF FIGURES (Continued) 

FIGURE PAGE 

7-21 Interrupt Acknowledge Timing 7-52 

7-22 Z80-CTC Signals and Pin Assignments 7-56 

7-23 Z80-CTC Control Code Interpretation 7-61 

9-1 Logic of the MC6800 CPU Device 9-4 

9-2 MC6800 CPU Signals and Pin Assignments 9-5 

9-3 A Standard MC6800 Read Machine Cycle 9-8 

9-4 A Standard MC6800 Write Machine Cycle 9-8. 

9-5 TSC Floating the Address Bus 9-10 

9-6 TSC Floating the Address and Data Busses When DBE is Tied to 4)2 9-11 

9-7 System Bus Floating During the Halt State 9-12 

9-8 MC6800 Interrupt Acknowledge Sequence 9-14 

9-9 The Reset Sequence 9-15 

9-10 MC6800 Wait Instruction Execution Sequence 9-16 

9-11 Use of 8080A Support Devices With MC6800 CPU 9-32 

9-12 Timing for8080A Support Devices Used With an MC6800 CPU 9-33 

9-13 Logic of the MC6802 CPU Device 9-34 

9-14 MC6802 CPU Signals and Pin Assignments 9-35 

9-15 MC6870A Clock Device Pins and Signals 9-39 

9-16 MC6871A Clock Device Pins and Signals 9-40 

9-17 MC6871B Clock Device Pins and Signals 9-40 

9-18 MC6875 Clock Device Pins and Signals 9-41 

9-19 Logic of the MC6820PIA 9-46 

9-20 MC6820PIA Signals and Pin Assignments 9-47 

9-21 Functional Block Diagram for the MC6820P1A 9-48 

9-22 I/O Port A Control Register Interpretation 9-52 

9-23 I/O Port B Control Register Interpretation 9-52 

9-24 Logic of the MC6850ACIA or MC6852SSDA Devices 9-56 

9-25 MC6850ACIA Signals and Pin Assignments 9-57 

9-26 MC6852SSDA Signals and Pin Assignments 9-62 

9-27 Data Flows Within an MC6852SSDA 9-64 

9-28 Logic of the MC6828 Priority Interrupt Controller 9-71 

9-29 MC6828 Signals and Pin Assignments 9-72 

9-30 MC6840Counter/Timer Signals and Pin Assignments 9-79 

9-31 Logic of the MC6844 DMA Controller 9-107 

9-32 MC6844 DMA Controller Signals and Pin Assignments 9-108 

9-33 Timing for Three-State Control, Cycle Stealing Direct Memory Access with the MC6844 9-111 

9-34 An MC6844 DMAC Connected for Three-State Control, Cycle Stealing Direct Memory 

Access 9-112 

9-35 Timing for Halt, Cycle Stealing Direct Memory Access with the MC6844 9-114 

9-36 An MC6844 DMAC Connected for Halt, Cycle Stealing or Halt Burst Direct Memory 

Access 9-115 

9-37 Logic for MC6844 DMAC with Channel 3 Chained to Channel and Data Flowing 

into Alternate Memory Buffers 9-120 

9-38 Logic of the MC6846 Multifunction Device 9-125 

9-39 MC6846 Multifunction Device Signals and Pin Assignments 9-126 

10-1 Logic of MCS6500 Series CPU Devices 10-3 

10-2 MCS6502 Signals and Pin Assignmerits 10-8 

10-3 MCS6503 Signals and Pin Assignments 10-8 

10-4 MCS6504 Signals and Pin Assignments 10-9 

10-5 MCS6505 signals and Pin Assignments 10-9 

10-6 MCS6506 Signals and Pin Assignments 10-10 

10-7 MCS651 2 Signals and Pin Assignments 10-10 

10-8 MCS6513 Signals and Pin Assignments 10-11 

10-9 MCS6514 Signals and Pin Assignments 10-11 

10-10 MCS6515 Signals and Pin Assignments 10-12 





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LIST OF FIGURES (Continued) 

FIGURE PAGE 

Time Base Generation for MCS650X CPU Input Clocks 10-17 

Logic of the MCS6522PIA 10-29 

MCS6522 PIA Signals and Pin Assignnnents 10-31 

Auxiliary Control Register Bit Assignnnents 1 0-32 

Peripheral Control Register Bit Assignnnents 10-34 

Logic of the MCS6530 and MCS6532 Multifunction Support Devices 1 0-48 

Logic Provided by the MCS6530 Multifunction Device 10-49 

MCS6530 Multifunction Device Signals and Pin Assignnnents 10-50 

Logic Provided by the MCS6532 Multifunction Device 10-53 

MCS6532 Multifunction Device Signals and Pin Assignments 10-54 

Logic of the 2650A Microcomputer CPU 1 1 -2 

2650A CPU Signals and Pin Assignments 11-9 
How Control Signals Identify Address and Data Bus Use for the 2650A Microcomputer 11-13 

2650A-8080A Signal Equivalents 1 1 -24 

2650A-MC6800 Signal Equivalents 11-24 

An 825 1 USART Accessed by a'2650A as an I/O Device 11-25 

An 825 1 USART Accessed by a 2650A as a Memory Device 1 1 -25 

An 8255 PPI Accessed by a 2650A as an I/O Device 11-26 

An 8255 PPI Accessed by a 2650A as a Memory Device 1 1 -26 

Vectored Interrupt Using the 8214 PICU with a 2650A CPU 11-27 

(2) 11-11 Synchronization Circuits in a 2650A-MC68XX Interface 11-28 

11-12 An MC6850ACIA Connected to a 2650A '' 11-29 

11-13 An MC6820 PIA Connected to a 2650A 11-29 

11-14 Important Timing Considerations When Interfacing a 2650A CPU with MC68XX 

Series Devices 11-30 

12-1 Logic of the CDP1802COSMAC CPU and the CDP1852 I/O Port 12-3 

12-2 CDP1802COSMAC CPU Signals and Pin Assignments 12-6 

12-3 COSMAC Machine Cycle Timing 12-8 

12-4 COSMAC Memory Read Instruction Timing 12-10 

12-5 COSMAC Memory Write Instruction Timing 12-11 

12-6 COSMAC DMA-IN Machine Cycle 12-12 

12-7 COSMAC DMA-OUT Machine Cycle 12-13 

12-8 COSMAC I/O Data Input Instruction Execution Timing 12-15 

12-9 COSMAC I/O Data Output Instruction Execution Timing 12-16 

12-10 CDP1 852 I/O Port Pins and Signals 12-32 

12-11 CDP1852 I/O Port in Input Modewith Programmed input 12-35 

12-12 CDP1852 I/O Port in Input Mode with DMA Input 12-36 

12-13 CDP1852 I/O Port in Output Modewith Programmed Output 12-38 

12-14 CDP1 852 I/O Port in Output Mode with DMA Output 12-39 

13-1 Logic of the IM6100 CPU and the IM61 01 Parallellnterface Element 13-2 

13-2 IM6100 CPU Signals and Pin Assignments 13-7 

13-3 IM6100 Machine Cycles and Clock Periods 13-8 

13-4 IM6100 Data Input Machine Cycle Timing 13-10 

13-5 IM6100 Data Output Machine CycleTiming 13-11 

13-6 IM61 00 Memory Read Machine CycleTiming 13-12 

13-7 IM6100 Instruction Fetch Machine Cycle 13-12 

13-8 Machine Cycle Timing for Memory Read from Indirectly Addressed Location 13-13 

13-9 IM6100MemoryWriteMachineCycleTiming 13-14 

13-10 Machine CycleTiming for Memory Write to Indirectly Addressed Location 13-15 

13-1 1 Auto-Increment Machine Cycle for an IM6100 Memory Reference Instruction that 

Specifies Indirect Addressing with Auto-Increment 1 3-1 5 

13-12 IM6100DCA Instruction Timing with Indirect Addressing 13-16 

13-13 IM6100 DCA Instruction Timing with Indirect Addressing and Auto-Increment 13-17 



LIST OF FIGURES (Continued) 

FIGURE PAGE 

13-14 IM6100 I/O Data Input Machine Cycle 13-18 

13-15 IM6100 I/O Data Output Machine Cycle 13-19 

13-16 IM6100l/OlnstructionTiming 13-21 

13-17 Wait States within an IM6100 Data Input Machine Cycle 13-22 

13-18 Wait States within an IM6100 Data Output Machine Cycle 13-23 

13-19 An IM61 00 Halt State Initiated by Execution of a HLT Instruction 1 3-24 

13-20 An IM6100 Halt State Initiated and Terminated by the RUN/HLT Input 13-25 

13-21 IM6100 DMA Initiation Timing 13-27 

13-22 IM61 00 DMA Termination Timing 13-28 

13-22a IM61 00 Interrupt Acknowledge Timing 13-30 

1 3-23 Logic and Instruction Sequce for an IM61 00 Vectored Interrupt Acknowledge 1 3:32 

13-24 IM61 00 OSR Instruction Timing 13-34 

13-25 IM6100 DCA Instruction in Control Panel Memory-Timing with Indirect Addressing 13-36 

13-26 IM61 00 Jump-to-Subroutine Instruction Timing with Indirect Addressing 13-48 

13-27 IM6100 Jump-to-Subroutine Instruction Timing with Stack Access Logic 13-49 

13-28 Using an External Stack Memory to Avoid IM6100JMS ROM Problems 13-50 

13-29 IM6100 System Bus Converted to an 8080A-Compatible System Bus ' 13-52 

13-30 IM6101 Parallel Interface Element Signals and Pin Assignments 13-54 

13-31 Logic of the 1M6101 PIE ' ' 13-55 

13-32 An IM61 01 I/O Read Instruction's Timing 13-59 

13-33 An IM6101 I/O Write Instruction's Timing 13-60 

13-34 Logic of the IM61 02 MEDIC 13.65 

13-35 IM61 02 MEDIC Signals and Pin Assignments 13-66 

13-36 An IM6100 Microcomputer System that Includes an IM6102 MEDIC and IM6101 

PIE Device 13-68 

13-37 IM61 02 Extended Memory Addressing Registers and Data Paths 13-71 

1 3-38 IM61 00 DCA Instruction Timing with Direct Addressing Using Extended Memory 

Addressing 13-73 

13-39 iM6100 DCA Instruction Timing with Indirect Addressing Using Extended Memory 

Addressing 13-75 

13-40 IM6100 DCA Instruction Timing with Indirect Addressing and Auto-Increment Using 

Extended Memory Addressing 13-76 

13-41 IM6102 DMA Read Timing 13-80 

13-42 IM6102 DMA Write Timing 13-81 

14-1 Logic of the 8X300 Microcontroller and 8T32/3/5/6 14-2 

14-2 A Logic Overview of the 8X300 Microcontroller 14-3 

14-3 8X300 Microcontroller Signals and Pin Assignments 14-5 

14-4 An 8X300 Register-to-Register Instruction's Execution 14-11 

14-5 An 8X300 IV Byte-to-Register Instruction's Execution 14-12 

14-6 An 8X300 Register-to-IV Byte Instruction's Execution 14-13 

1 4-7 An 8X300 IV Byte-to-IV Byte Instruction's Execution 14-14 

14-8 8T32/3/5/6 Interface Vector Byte Signals and Pin Assignments 14-21 

14-9 8T32/3/5/6 IV Byte Control Signals and Interfaces 14-22 

14-10 8T32/3/5/6 IV Byte Address Programming Pulse , , 14-24 

14-11 8T32/3/5/6 IV Byte Protect Programming Pulse 14-25 

14-12 8T39 and 8T38 Bus Expander Signals and Pin Assignments 14-26 

15-1 A National Semiconductor PACE Microcomputer System 15-3 

15-2 A National Semiconductor 1NS8900 Microcomputer System 15-4 

15-3 Logic of the INS8900 Microprocessor 15-5 

15-4 1NS8900 and PACE CPU Signals and Pin Assignments 15-10 

15-5 1NS8900 and PACE Data Input Timing 15-12 

T5-6 INS8900 and PACE Data Output Timing 15-13 

15-7 Using the EXTEND Signalto Lengthen 1/0 Cycles 15-13 

15-8 INS8900 and PACE Initialization Timing 15-14 





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LIST OF FIGURES (Continued) 

FIGURE PAGE 

Terminating INS8900 or PACE Halt State 15-15 

Timing Diagram for Processor Stall Using NHALT and CONTIN Signals 15-16 

Using PACE EXTEND Signal for Cycle-Stealing DMA 15-17 
Idealized Circuit for Cycle-Stealing DMA During INS8900 and PACE Internal Machine 

Cycles 15-18 

Timing for Cycle-Stealing DMA During INS8900 and PACE Internal Machine Cycle 15-19 

internal View of INS8900 and PACE Interrupt System 15-20 

Initiating INS8900 and PACE Level Interrupt Using NHALT and CONTIN Signals 1 5-23 
Circuit to Prevent Conflicts Between PACE Level Interrupts and Lower Priority 

Interrupts 15-25 

DP8302SystemTimingEiement(STE) Pins and Signals 15-35 

Circuit to Generate Substrate Bias Voltage (Vbb) for PACE CPU 15-36 

BTE Signals and Pin Assignments 15-36 

Signal Connections to Control BTE in a DMA System 15-37 

Logic of the CP1 600 CPU and CP1 680 I/O Buffer 16-2 

CP1 600 CPU Signals and Pin Assignments 1 6-7 

CP1 600 Machine Cycles and Bus Timing 1 6-9 

CP1 600 Instruction Fetch Timing 16-9 

CP1 600 Timing for Memory Read Instruction with Implied Memory Addressing 16-10 

CP1 600 Timing for Memory Write Instruction with Implied Memory Addressing 16-11 

CP1 600 Wait State Timing 16-12 

CP1600 DMA Timing 16-14 

CP1600 Interrupt Service Routine Initialization 16-14 

CP1600 Timing for TCI Instruction's Execution 16-15 

CP1 600 to 8080A Bus Conversion 16-26 

CP1 600 lOB Signals and Pin Assignments 16-28 

A CP1 600-CP1 680 Microcomputer Configuration 1 6-29 

PD1680 Handshaking with Data Input 16-34 

PD1 680 Handshaking for Data Output 1 6-35 

Logic of the 1650 Series Microcomputers 17-2 

1650 Functional Logic 17-3 

1 650 Series Microcomputer Bidirectional I/O Port Pin Logic 1 7-4 

1650 Microcomputer Signals and Pin Assignments 17-7 

Logic of the TMS 9900 CPU 18-2 

TMS 9900 Signals and Pin Assignments 18-14 

TMS 9900 Clock Periods and Timing Signals as Generated by the TIM 9904 18-16 

A TMS 9900 Memory Read Machine Cycle 18-16 

A TMS 9900 Memory Write Machine Cycle 1 8-1 7 

Two TMS 9900 Output-to-CRU Machine Cycles 18-21 

TwoTMS 9900 Input-from-CRU Machine Cycles 18-22 

TMS 9900 System Bus Utilization During I/O Operations 18-24 

The TMS 9900 Wait State 18-24 

TMS 9900 Hold State Timing 18-25 

TMS 9900 Memory Map 18-28 

A TMS 9900 Interrupt Acknowledge Pulse Generated Using an SBO Instruction 18-33 

TMS 9900 Interrupt Acknowledge Generated by Decoding Valid Addresses ■ 1 8-33 

Logicof the TMS 9980A and TMS 9981 Microprocessors 18-46 

TMS 9980A Signals and Pin Assignments 18-47 

TMS 9981 Signals and Pin Assignments 18-48 

TMS 9980 Memory Map 18-51 

Some TMS 9980AArMS 9981 Interrupt Interfaces 18-52 

Logicof the TMS 9940 Single-Chip Microcomputers 18-53 

TMS 9940 Memory Map 18-54 



LIST OF FIGURES (Continued) 

FIGURE PAGE 

18-21 TMS 9940 Microcomputer Signals and Pin Assignments 18-58 

18-22 Handshaking Logic in a TMS 9940 Multi-Microcomputer Network Communicating 

via the TD Data Line 18-62 

18-23 TIM 9904 Signals and Pin Assignments 18-68 

18-24 Logicof the TMS 9901 Programmable System Interface 18-71 

18-25 TMS 9901 Programmable System Interface Signals and Pin Assignments 18-72 

18-26 TMS 9901 PSI General Data Flows and CRU Bit Assignments 18-75 

1 9-1 Logic of the Data General MicroNova and the Fairchild 9440 1 9-3 

19-2 MicroNova CPU Signals and Pin Assignments 19-13 

19-3 9440 CPU Signals and Pin Assignments 19-14 

19-4 TheNova Arithmetic and Logic Unit 19-16 

19-5 Arithmetic/Logic Instruction Object Code Interpretation 19-16 

19-6 Load and Store Instruction Object Codes 19-19 

19-7 Jump and Modify Memory Instruction Object Codes 19-19 

1 9-8 General Input/Output Instruction Object Code Interpretation 1 9-20 

19-9 Input/Output Skip Instruction Object Code Interpretation 19-21 

19-10 CPU Device 3Fi 6 Input/Output Instruction Object Code Interpretation 19-21 

19-11 CPU Device 1 Input/Output Iristruction Object Code Interpretation 19-22 

19-12 9440 Memory Read/Instruction Fetch Timing 19-23 

19-13 9440 Memory Write Timing 19-24 

19-14 9440 I/O Data Input Timing 19-26 

19-15 9440 I/O Data Output Timing 19-26 

1 9-1 6 9440 Interrupt Acknowledgelnstruction Execution Timing 1 9-30 

19-17 9440 Mask Out Instruction Execution Timing 19-31 

20-1 Logic of the Intel 8086 CPU 20-4 

20-2 8086 Programmable Registers 20-5 

20-3 8086 Pins and Signal Assignments 20-19 

20-4 Two 8086 Bus Cycles 20-26 

20-5 8086 Memon/ Read Bus Cycle for a Minimum Mode System (MN/MX=4-5V) 20-30 

20-6 8086 Memory Write Bus Cycle for a Minimum Mode System (MN/MX=-F5V) 20-32 

20-7 8086 Memory or I/O Read Bus Cycle for a Maximum Mode System (MN/MX=OV) 20-33 

20-8 8086 Memory or I/O Write Bus Cycle for a Maximum Mode System {MN/MX=OV) 20-33 

20-9 The 8086 READY Input and Wait States 20-34 

20-1 8086 HALT Instruction and Bus Cycle Timing for a Complex Bus Configuration 20-36 

20-11 8086 Interrupt Vector 20-39 

20-12 Logic of the 8284 Clock Generator and Driver 20-76 

20-13 8284 Clock Generator and Driver Pins and Signal Assignments 20-76 

20-14 Normal 8284 Clock Generator Circuit 20-78 

20-15 Clock Synchronization Logic in a Multi-CPU 8086 Configuration 20-79 

20-16 8288 Bus Controller Pins and Signal Assignments 20-80 

20-1 7 8282 and 8283 Input/Output Port Pins and Signal Assignments 20-84 

20-1 8 8286 and 8287 Bidirectional Bus Transceiver Pins and Signal Assignments 20-85 

20-19 Generating a System Bus for a Simple 8086 Configuration 20-86 

20-20 Generating a System Bus in an 8086 Microcomputer System Using an 8288 Bus 

Controller 20-88 

22-1 The 2901/6701 Arithmetic and Logic Unit 22-2 

22-2 2901 ALU Logic 22-3 

22-3 2909 Microprogram Sequencer Block Diagram 22-6 

22-4 Four 2901 sin a 16-Bit CPU Using the 2902 for Carry Look Ahead 22-9 

23-1 MC10800 Series Devices in a Central Processing Unit Configuration 23-1 

23-2 The MC10800 ALU Slice Functional Diagram 23-2 

23-3 MC10803 Memory Interface Device Block Diagram 23-6 



LIST OF FIGURES (Continued) 

FIGURE PAGE 

24-1 Logic of the Hewlett Packard MC2 Microprocessor 24-2 

24-2 CPU and I/O Device Registers' Organization for the MC2 24-4 

25-1 System Software Modules 25-6 



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LIST OF TABLES 

TABLE PAGE 

TMS 1 000 Series Microcomputer Summary 1 -1 

TMS1 000 Series Instruction Set Summary 1-12 

3870/F8 Instruction Set Summary 2-21 

Timing and ROMC States for F8 Instruction Set 2-27 

3870/F8 Instruction Set Object Codes 2-29 

ROMC Signals and What They Imply 2-33 

Relationship Between Programmable Timer Contents and Effective Timer Counts 2-44 

A Summary of Differences Between 3851, 3856, and 3857 PSUs 2-47 

Status and Address Output via the Data Lines at the Beginning of an I/O Cycle 3-8 

Statuses Output on the Data Bus for Various Types of Machine Cycles 3-8 

SC/MP Instruction Execution Times 3-1 1 

SC/MP Instruction Set Summary 3-24 

SC/MP Instruction Set Object Codes and Execution Times 3-27 

Devices of the 8080A Microcomputer Family 4-2 

Statuses Output via the Data Lines During the Second Clock Cycle of an 8080A 

Machine Cycle 4-1 1 

Statuses Output on the Data Bus for Various Types of Machine Cycle 4-1 1 

A Summary of 8080A/9080A Microcomputer Instruction Set 4-27 

A Summary of Instruction Object Codes and Execution Cycles 4-32 

@ 4-6 A Summary of 8259 PICU Operations 4-66 

4-7 TMS 5501 Address Interpretations 4-70 

4-8 TMS 5501 Interrupt Logic and Priorities 4-74 

5-1 A Summary of 8085A Instruction Object Codes and Execution Cycles 5-32 

5-2 8155/8156 Device Port C Pin Options 5-38 

6-1 A Summary of 8048 Series Microcomputers 6-2 

6-2 A Summary of 8048 Microcomputer Instruction Set 6-35 

6-3 8048 Series Instruction Set Object Codes 6-41 

7-1 Comparisons of Z80 and 8080A Instruction Execution Cycles 7-4 

7-2 A Summary of the Z80 Instruction Set 7-22 

7-3 A Summary of Instruction Object Codes and Execution Cycles with 8080A Mnemonics 

for Identical Instructions 7-33 

7-4 Z80 PIO Interpretation of Control Signals 7-45 

7-5 Z80 PIO Select Logic 7-47 

7-6 Z80 PIO and 8255 Mode Equivalences 7-49 

9-1 A Summary of the MC6800 Instruction Set 9-19 

9-2 Operation Summary 9-26 

9-3 MC6800 Instruction Set Object Codes 9-30 

9-4 MC6820 Operating Modes 9-49 

9-5 Addressing MC6820 Internal Registers 9-49 

9-6 MC6852 Status Register Bit Set/Reset Conditions 9-67 

9-7 MC6852 Interrupt Summary 9-68 

9-8 MC6828 Address Vectors Created for Eight Priority Interrupt Requests 9-74 

9-9 MC6828 Interrupt Masks -Their Creation and Interpretation 9-78 

9-10 MC6840 Addressable Locations 9-82 

9-1 1 A Summary of MC6840 Options and Control Register Settings 9-99 

9-12 MC6844 DMAC Register Addresses 9-110 

9-13 MC6844 DMAC Modes' Response Times and Transfer Rates 9-116 

9-14 MC6846 I/O Addressable Locations 9-124 



LIST OF TABLES (Continued) 

TABLE PAGE 

10-1 A Comparison of MCS6500 Series and the MC6800 CPU Devices 10-2 

10-2 A Sumnnary of the MCS6500 Microconnputer Instruction Set 10-20 

10-3 Summary of MCS6500 Object Codes, with iViCeSOOMnenrionics 10-26 

10-4 Addressing MCS6522 Internal Registers 10-33 

10-5 Summary of I/O Port A Handshaking Control Signals 10-37 

10-6 A Summary of MCS6522 Interrupt Setting and Resetting 10-47 

10-7 Addressing the MCS6530 Multifunction Support Logic Device 10-52 

10-8 Addressing the MCS6532 Multifunction Support Logic Device 10-55 

11-1 Summary of Signetics2650A Instruction Set 11-17 

11-2 Signetics2650A Instruction Object Codes 11-22 

12-1 COSMAC Instruction Set Summary 12-26 

12-2 COSMAC Instruction Set Object Codes 12-31 

13-1 IM6100 External Signal Sampling Priorities 13-37 

13-2 IM6100 Instruction Set Summary 13-40 

13-3 IM61 00 Instruction Set Object Codes 13-46 

13-4 IM61 01 Interpretation of I/O Instruction Control Bits 3-0 13-57 

13-5 IM6102 MEDIC Pins that should belied to Power or Ground when Certain Functions 

are Unused 13-67 

13-6 IM6102 MEDIC I/O Instructions 13-87 

14-1 8X300 Source and Destination Object Code Interpretations 14-10 

14-2 8X300 Instruction Set 14-18 

14-3 8X300 Instruction Set Object Codes 14-20 

14-4 Interface Vector Byte Options 14-21 

14-5 SpecificationsforSignalslllustrated inFigures 14-10and 14-11 14-24 

1 4-6 8T39 Bus Expander Addresses and IV Byte Addresses That May Be Connected 1 4-27 

15-1 INS8900 and PACE Instruction Set Summary 15-27 

15-2 INS8900 and PACE Instruction Set Object Codes 15-31 

15-3 Branch Conditions for INS8900 and PACE BOC Instruction 15-33 

15-4 PACE BTE Truth Table 15-37 

15-5 Comparing INS8900 System Busses to 8080A System Busses 15-44 

16-1 CP1 600 Bus Control Signals 16-8 

16-2 CP1 600 Instruction Set Summary 16-18 

16-3 CP1 600 Branch Conditions and Corresponding Codes 16-23 

16-4 CP1 600 Instruction Set Object Codes 16-24 

17-1 1650 Series One-Chip Microcomputer Options 17-1 

17-2 1650 Series Microcomputer Register Designations 17-5 

17-3 ASummary of the 1650 Series Microcomputer Instruction Set 17-11 

1 7-4 Mnemonics Recognized by the 1 650 Assembler for Special Cases of General 

Instructions 17-14 

17-5 1650 Instruction Set Object Codes 17-15 

18-1 High-Order Address Bus Line Used by TMS 9900 I/O Instructions 18-23 

18-2 TMS 9900 Instruction Set Summary 18-38 

18-3 TMS 9900 Instruction Set Object Codes 18-43 

18-4 A Summary of Differences Between the TMS 9900 and TMS 9980 Series 

Microprocessors 18-45 

18-5 A Summary of Differences Between the TMS 9980A and TMS 9981 Microprocessors 18-50 

18-6 TMS 9980 Interrupts 

18-7 TMS 9940 CRU Bit Address Assignments 18-59 

1 8-8 TMS 9940 CRU Bits Whose Functions are Determined Under Program Control 1 8-60 





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LIST OF TABLES (Continued) 

TABLE PAGE 

Nova System Bus Signals 19-11 

MicroNova and 9440 Instruction Set Summary 1 9-35 

MicroNova and 9440 Instruction Set Object Codes 1 9-40 

A Summary of Intel 8086 Memory Addressing Options 20-10 

8086 Branch-on-Condition Instructions 20-47 
A Summary of Intel 8086 Memory Addressing Options Identified by the EA 

Abbreviations in Table 20-3 20-50 

The 8086 Instruction Set Summary 20-51 

A Summary of 8086 Instruction Object Codes and Execution Cycles 20-68 

8080A to 8086 Instruction Mapping 20-74 

Effect of 108, CEN, and AEN on Control Signals Output by the 8288 Bus Controller 20-82 

2901 ALU Function Control 22-3 

ALU Source Operand Control 22-3 

ALU Destination Control 22-7 

MC 1 0800 ALU Logical Operations 23-3 

MCI 0800 Arithrrietic Operations 23-4 

A Summary of the MC2 Instruction Set 24-8 

Some Typical Microcomputer Based Product and Development Costs 25-10 

Unit Prices for Microcomputer Based Products 25-1 



QUICK INDEX 



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A Address/Data Lines, Demultiplexing in the INS8900 15-38 

After Sales Service 25-1 

ALE Differences in 8085 and 8085A 5-5 

ALE Generation in 8085 and 8085A 5-18 

AMD 9080A Status Difference 4-6 

Assembler 25-5 

Assembler/Editor Combined 25-5 

B Bidirectional Transceiver Element (BTE) 15-2 

BTE Mode Control Signals 15-37 

Buffering SC/MP Busses 13-29 

Bus Interface Unit (BlU), 8086 20-25 

C CALL Instruction, 8080A Interrupt Response Using 4-54 

Chip Slice Logic, Carry Status and Overflow in 22-5 

Chip Slice Logic, Sign Status in 25-5 

Chip Slice Logic, Zero Status in 22-5 

Context Switch, TMS 9900 18-5 

Context Switch, TMS 9900 Backward 18-6 

Context Switch, TMS 9900 Forward 18-6 

CONTIN and NHALT Signals are Malfunctional 15-15 

Continuing Engineering Costs 25-1 

COSMAC Input/Output Programs 12-23 

COSMAC Instruction Machine Cycle 12-9 

COSMAC Interrupt Service Routine Programs 1 2-23 

COSMAC Negative Set-up Time 12-9 

COSMAC Nested Subroutine 12-22 

COSMAC Timing Variations 12-8 

Cost, Variable Contributing Factors 25-1 

Costs, Variable 25-2 

CPU Initiated DMA Block Data Transfers 15-16 

CP1 600 Direct Addressing 16-3 

CP1 600 Implied Addressing 16-4 

CP1 600 I/O Port Pin Characteristics 16-30 

CP1600PCIT Signal 16-13 

CP1600 Stack Addressing 16-5 

Cycle-Stealing DMA During INS8900 and PACE Internal Machine Cycles 15-18 

Cycle-Stealing DMA in PACE and INS8900 Systems 15-17 

D Debug 25-8 

Demultiplexing the INS8900 Address/Data Lines 15-38 

Demultiplexing the SC/MP Data Bus 3-30 

DEND/IRO Signal, MC6844 DMAC 9-113 

DGRNT, DMAC, TxSTB, TxAKA and TxAKB Signals, MC6844 9-114 

DGRNT, TxRON, and DQRT Signals, MC6844 DMAC 9-112 

DMA and Multiprocessor Logic of the SC/MP 3-1 

DMA Block Data Transfers Initiated by CPU _ 15-16 

DMA Block Data Transfers Initiated by External Logic in PACE and INS8900 Systems 15-17 

DMA Control Signals in IM6102 13-79 

DMA, Cycle-Stealing, During INS8900 and PACE Internal Machine Cycles 15-18 

DMA, Cycle-Stealing, in PACE and INS8900 Systems 15-17 

DMA Modes in IM61 02 13-83 

. DMA Priority Arbitration, MC6844 Fixed 9-116 

DMA Programming in IM6102 13-83 

DMA Registers in IM6102 13-79 

DMAC, DGRNT, TxSTB, TxAKA, and TxAKB Signals, MC6844 9-114 

DQRT, DGRNT, and TxRON Signals, MC6844 DMAC 9-112 

DRQH Signal, MC6844 DMAC 9-114 



QUICK INDEX (Continued) 

INDEX PAGE 

E iCont.) Editor . 25-5 

Editor/Assembler Combined 25-5 

Enabling and Disabling INS8900 and PACE Interrupts 15-21 

Execution Unit (EU), 8086 20-25 

Extend Used to Suspend INS8900 and PACE I/O During DMA Operations 15-17 

Extended Memory, Base Page in IM61 00 13-70 

F FairchildFS Device Set. The 2-1 

Fixed Cost Contributing Factors 25-1 

Fixed Costs 25-2 

Floating INS8900 and PACE System Busses 15-15 

F8 Device Set, The Fairchild 2-1 

F8 Direct Memory Access 2-53 

F8 DMI Memory Refresh 2-52 

F8/3870 Accumulator 2-5 

F8/3870 Data Counters 2-6 

F8/3870 Program Counter 2-6 

F8/3870 Scratchpad 2-6 

F8/3870 Stack Register 2-6 

G Generating the PACE Substrate Bias Voltage 15-35 

H Halt State in 8085 and 8085A 5-24 

Hold State in 8085 and 8085A 5-24 

I IM6100 Base Page in Extended Memory 13-70 

IM6100 Bit Numbering 13-7' 

IM6100 Clock Period Assignments 13-10 

IM6100 Control Panel Switch Register 13-33 

IM6100 Extended Memory Jump 13-77 

IM61 00 Extended Memory Subroutine Accesses 13-77 

IM6100-IM6102 Interrupt Acknowledge 13-70 

IM6100-IM6102 Reset Bootstrap 13-70 

IM6100 Indirect Addressing with Auto-Increment Timing 13-14 

IM61 00 Indirectly Addressed Memory Read Cycle 13-13 

IM6100lndirectly Addressed Memory Write Cycle 13-14 

IM6100 Instruction Fetch Machine Cycle 13-13 

iM61 00 Interrupt Processing Instructions 13-31 

IM6100 Memory Fields 13-70 

IMpI 00 Subroutines in Read-Only Memory 1 3-5 

IM6100 Vectored Interrupt Acknowledge 13-32 

IM6101 Control Registers 13-58 

1M6101 FLAG Instructions 13-61 

IM6ipi FLAG Outputs 13-58 

IM6lbl Interrupt Acknowledge 13-70 

IM6101 I/O Instructions 13-58 

IM6101 Programming 13-56 

IM6101 Read Instruction - 13-58 

IM6101 Reset Bootstrap 13-70 

IM6101 Select Logic 13-56 

IM6101 Sense Inputs 13-58 

1M6101 Sense Interrupt Priority 13-63 

IM6101 SKIP Instructions 13-61 

IM6101 Write Operation 13-58 

IM6102 Data Field Register 13-70 

1M6102 DMA Control Signals 13-79 

IM6102 DMA Modes 13-83 

IM6102 DMA Programming 13-83 



QUICK INDEX (Continued) 



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KCont.) IM6102 DMA Registers 13-79 

IM61 02 Extended Memory Addressing Registers 13-70 

IM6102 Instruction Buffer Register 13-71 

IM6102 Instruction Field Register 13-70 

IM6102 Interrupt Acknowledge 13-70 

IM6102 Interrupt Vector Register 13-78 

IM6102 Jump Across Memory Fields 13-72 

IM61 02 Reset Bootstrap 13-70 

INS8900 and PACE CPU Registers During Interrupts, Saving 15-22 

INS8900 and PACE, Cycle-Stealing DMA during Internal Machine Cycles 15-18 

INS8900 and PACE Data Input Cycle 15-12 

INS8900 and PACE Data Output Cycle 15-13 

INS8900 and PACE Direct Addressing Options 15-24 

INS8900 and PACE Direct Indexed Addressing 1 5-7 

INS8900 and PACE Execution Speed 1 5-1 

INS8900 and PACE Extend Signal for Slow I/O Operations 15-13 

INS8900 and PACE, Extend Used to Suspend I/O During DMA Operations 15-17 

INS8900 and PACE, Floating System Busses 15-15 

INS8900 and PACE Halt State 15-14 

INS8900 and PACE Interrupt Acknowledge and Return from Interrupt 15-21 

iNS8900 and PACE Interrupt Pointers 1 5-21 

INS8900 and PACE Interrupt Priorities 15-21 

INS8900 and PACE Interrupt Response 15-21 

INS8900 and PACE Interrupts, Enabling and Disabling 15-21 

INS8900 and PACE Level Interrupt Response 1 5-22 

INS8900 and PACE Logic Level 15-2 

INS8900 and PACE Machine Cycle 15-12 

INS8900 and PACE Machine Cycle Types 1 5-1 2 

INS8900 and PACE Non-Maskable (Level 0) Interrupt 15-22 

INS8900 and PACE Power Supply 15-1 

INS8900 and PACE Processor Stall 15-15 

INS8900 and PACE Signal Differences 15-10 

INS8900 and PACE Split Base Page 15-16 

INS8900 and PACE Split Base Page to Address I/O 15-7 

INS8900 and PACE Stack Interrupts 15-5,22 

INS8900 and PACE Systems, Cycle-Stealing DMA in 1 5-17 

INS8900 and PACE Systems, DMA Block Data Transfers Initiated by External Logic 1 5-1 7 

INS8900 and 8080A System Busses Compared 1 5-43 

INS8900 Control Signal Polarity Considerations 1 5-39 

INS8900, Demultiplexing the Address/Data Lines 15-38 

INS8900 System, The8212 Used as a Simple Input Port in an 1 5-39 

INS8900 System, The 821 2 Used as an Output Port in an 15-41 

INS8900 System, 8255 PPI Devices Used in an 15-42 

INS8900 Systems, The 8251 USART and 8253 Programmable Counter/Timer Used in 1 5-43 

INS8900, Two 8255 Devices Used for 1 6-Bit I/O Ports with 1 5-43 

INS8900, 6800 Support Devices Compatible with 15-44 

INS8900, 821 2 Used for Input with Handshaking in 1 5-40 

Interrupt Differences in 8085 and 8085A 5-28 

Interrupts During an MC6800 HALT 9-38 

IRQ/DEND Signal, MC6844 DMAC 9-113 

L Label Table 25-8 

Level and Processor Stall Interrupt Similarities 15-15 

Linking Loader 25-8 



QUICK INDEX (Continued) 

INDEX PAGE 

M MCS6500 Slow Memory Interface 10-15 

MCS6500 Wait State 10-14 

MCS6522 Addressing 10-31 

MCS6522 Interval Timer 1 10-39 

MCS6522lntervalTimer1 Free Running Mode 10-41 

MCS6522 Interval Timer 1 One-Shot Mode 10-40 

MCS6522 Interval Timer 2 10-41 

MCS6522 I/O Port A Data Transfer 10-33 

MCS6522 I/O Port B Data Transfer 10-35 

MCS6530 Addressing Logic 10-48 

MCS6532 /^Cidressing 10-54 

MC6800 Bus State Controls 9-6 

MC6800 Clock Signals 9-7 

MC6800 Enable Signal Generation 9-44 

MC6800 HALT, Interrupts During an 9-38 

MC6800 Internal Operations Machine Cycle 9-9 

MC6800 Interrupt Priorities 9-13 

MC680d Machine Cycle 9-7 

MC6800 Machine Cycle Types 9-7 

MC6800 Non-Maskable Interrupt 9-13 

MC6800 Normal External Interrupts 9-13 

MC6800 Read Machine Cycle " 9-7 

MC6800 Reset 9-13 

MC6800 Reset During Power-up 9-15 

MC6800 Reset Operation 9-15 

MC6800 Software Interrupt 9-13 

MC6800 Stretching Address Timing 9-42 

MC6800SWI Instruction 9-13 

MC6800 Synchronous HALT Generation 9-45 

MC6800UseofWAITforDMA 9-16 

MC6800WAI Instruction 9-16 

MC6800 Wait State 9-16 

MC6800 Wait State with Slow Memory 9-9 

MC680b Write Machine Cycle 9-8 

MC6820 Automatic Handshaking 9-53 

MC6820 Control Codes 9-51 

MC6820 Interrupt Logic 9-51 

MC6820 Registers Addressing 9-49 

MC6840 Continuous Mode 9-100 

MC6840 Continuous Mode with Initial Value 9-103 

MC6840 Continuous 8-Bit Counting Square Wave Option 9-103 

MC6840 Control Registers 9-94 

MC6840 Counter/Timer Initialization 9-79 

MC6840Divide-by-Eight Clock 9-95 

MC6840Divide-by-EightMode 9-103 

MC6840 Event Counting 9-104 

MC6840 External Signal Timing 9-80 

MC6840 Frequency Comparison and Pulse Width Measurement Mode 5 9-105 

MC6840 Hardware Initialization 9-102 

MC6840 Interrupt Enable 9-96 

MC6840 One-Shot Mode 9-1 04 

MC6840 Output Signal Enable 9-97 

MC6840 Programmed Initialization 9-94 

MC6840 Status Register 9-97 

MC6840 8-Bit Counting Mode 9-96 

MC6840 1 6-Bit Counting Mode 9-95 

MC6844 Channel Control Registers 9-119 



QUICK INDEX (Continued) 



INDEX PAGE 

M (Cont.) MC6844 Data Chaining 9-119 

MC6844 Data Chaining Control Register 9-117 

uj MC6844 DMAC Address Bus 9-109 

< MC6844 DMAC Data Bus 9-109 

o MC6844 DMAC Device Select 9-109 

DC MC6844 DMAC. DGRNT.TxSTB, TxAKA and TxAKB Signals 9-114 

8 MC6844 DMAC DRQH Signal 9-114 

5 MC6844 DMAC Four-Channel Mode 9-118 

w MC6844 DMAC IRQ/DEND Signal 9-113 

H MC6844 DMAC Two-Channel Mode 9-117 

o MC6844 DMAC TxAKA and TxAKB Signals 9-113 

g MC6844DMAC,TxRON,DQRT, and DGRNT Signals 9-112 

5 MC6844 DMAC TxR0-TxR3 Signals ■ 9-114 

.8 MC6844 DMAC TxSTB Signal 9-113.115 

^ MC6844 DMAC $2 DMA Clock 9-112 

g MC6844 Enable/Priority Control Register 9-116 

BJ MC6844 Fixed DMAPriority Arbitration 9-116 

o MC6844 Interrupt Control Register 9-121 

5 MC6844 Rotating Data Priority Arbitration 9-117 

Q MC6846 Composite Status Register 9-129 

*^ MC6850 Control Register ' 9-59 

@ : MC6850 Interrupt Logic 9-59 

MC6850 MODEM Control Signals 9-58 

MC6850 Serial I/O Control Logic 9-59 

MC6850Seriall/O Data and Control Signals 9-58 

MC6850 Systenn Reset 9-59 

MC6852 Interrupt Logic 9-70 

MC6852 Reset Operation 9-70 

MC6852 Serialization Sequence 9-63 

MC6852 Triple Data Buffers 9-65 

Microconnputer Development Systems, Simple 25-4 

Microcomputer Development Systems. Simulating 25-4 

MicroNova I/O Bus 19-12 

MicroNova Memory Bus 19-12 

MODEM Control Signals 9-58 

Monitor: 25-5 

Motorola A and B Series Parts 9-2 

Multiple Device Selects and Bus Loading (8085A) 5-11 

Multi-8086 Clock Signals. Synchronizing 20-79 

N NEC 8080AExternallnterrupt Differences 4-24 

NEC 8080A Hold Differences 4-17 

NEC 8080A Instruction Execution Time Differences 4-33 

NEC 8080A Instruction Set Differences 4-24. 

NEC 8080A Interrupt Acknowledge Differences 4-24 

■ NHALT and CONTIN Signals are Multifunctional 15-15 

Nova Direct Memory Addressing 19-6 

Nova Indirect Indexed Addressing 19-8 

Nova Indirect Page Zero Addressing 19-6 

Nova Indirect Program Relative Addressing 19-7 

Nova I/O Device Address Space 19-22 

Nova I/O Device Addressing 19-9 

Nova I/O Device Busy and Done Status 19-20 

Nova I/O Device Registers 19-21 

Nova Multiple Indirect Addressing . 19-9 

O Object Programs. Relocatable 25-7 

Overflow and Carry Status in Chip Slice Logic 22-5 , 



QUICK INDEX (Continued) 

INDEX PAGE 

P PACE Address Latches and Decoders ' , 15-2 

PACE and INS8900, Cycle-Stealing DMA during Internal Machine Cycles 15-18 

PACE and INS890P Data Input Cycle 15-12 

PACE and INS8900 Data Output Cycle %'^^ 

PACE and INS8900 Direct Addressing Options 1S-24 

PACE and INS8900 Direct Indexed Addressing . 15-7 

PACE and INS8900 Execution Speed 15-1 

PACE and INS8900, Extend Used to Suspend I/O During DMA Operations 1 5-1 7 

PACE and INS8900, Floating System Eiusses 15-15 

PACE and INS8900 Halt State 15-14 

PACE and INS8900 Interrupt Acknowledge and Return from Interrupt 15-21 

PACE and INS8900 Interrupt Pointers 15-21 

PACE and INS8900 Interrupt Priorities 15-21 

PACE and INS8900 Interrupt Response 15-21 

PACE and INS8900 Interrupts, Enabling and Disabling 15-21 

PACE and INS8900 Logic Level 15-2 

PACE and INS8900Mai=hlne Cycle 15-12 

PACE and INS8900 Machine Cycle Types 15-12 

PACE and INS8900 Non-Maskable (Level 0) Interrupt 15-22 

PACE and INS8900 Power Supply 15-1 

PACE and INS8900 Processor Stall ' 15-15 

PACE and INS8900 Signal Differences 15-10 

PACE and INS8900 Signal for Slow Operations 15-13 

PACE and INS8900 Split Base Page 15-16 

PACE and INS8900 Split Base Page to Address I/O 15-7 

• PACE and INS8900 Stack Interrupts 15-5,22 

PACE and INS8900 Systems Cycle-Stealing DMA 15-17 

PACE and INS8900 Systems DMA Block Data Transfers Initiated by External Logic 15-17 

PACE Clock Signals 15-11 

PACE CPU and INS8900 Registers during Interrupts, Saving 15-22 

PACE DP8302STE Clock Frequency 15-35 

PACE Level Interrupt Problems 15-24 

PACE Level Interrupt, Return from 15-23 

PACE MILE Used in an SC/MP System. The 3-31 

PACE Stack Interrupt Problems 15-22 

Preventing Simultaneous Selection of I/O and Memory on an 8085A 5-1 2 

Preventing Transient Selection on an 8085A 5-1 2 

Processor Stall and Level Interrupt Similiarities 15-15 

Program Linking 25-8 

PSU Address Space 2-40 

R Read-Only Memory, IM6100 Subroutines in 13-5 

Relocatable Loader 25-7 

Relocatable Object Programs 25-7 

Relocating Assembler 25-7 

Reset, 8048, 8748, and 8035 6-17 

Return from PACE Level Interrupt 15-23 
ROMC State . ■ 2-35 

S Saving INS8900 and PACE CPU Registers During Interrupts . 15-22 

SC/MP and SC/MP-II 3-3 

SC/MP and SC/MP-II, Signal Differences Between 3-5 

SC/MP Bus Access Control Signals 3-6 

SC/MP Bus-Sharing Control Signals 3-17 

SC/MP Busses, Buffering 3-29 

SC/MP Control Techniques in Multiprocessor Applications 3-1 9 

SC/MP Data Bus Definition Signals 3-7 



QUICK INDEX (Continued) 

INDEX PAGE 

S iCont.) SC/MP Data Bus, Demultiplexing the 3-30 

SC/MP Data Input Cycle 3-12 

2 SC/MP Data Output Cycle 3-12 

5 SC/MP DMA and Multiprocessor Logic 3-1 

g SC/MP ENOUT Signal Used to Establish Access Pnorities 3-10 

K SC/MP Instruction Execution Speed 3-3 

8 SC/MP I/O Cycle Status Information 3-7 

2 SC/MP I/O Cycle, Suspension of an 3-9 

« SC/MP I/O with Bus Access Logic Continuously Enabled 3-10 

K SC/MP Logic Level 3-3 

1 SC/MP Memory Pages 3-3 
o SC/MP in Multiprocessor Systems 3-18 
w SC/MP NHOLD Signal forSlow I/O Operations 3-13 
^ SC/MP (P-Channel) and SC/MP-II (N-Channel), Signal Differences Between 3-5 
u SC/MP Return-from-lnterrupt Technique 3-15 
i SC/MP Serial I/O 3-1 
g SC/MP System. The PACE MILE Used in an 3-31 
g SC/MP System, The 821 2 Used as an Output Port in an 3-33 

2 SC/MP Systems, The 82 12 I/O Port Used in 3-32 

< SC/MP Timing Control Signals 3-7 

< SC/MP-II (N-Channel) and SC/MP (P-Channel), Signal Differences Between 3-5 
@ Select Problem with 8085 5-14 

Service, After Sales 25-1 

Sign Status in Chip Slice Logic 22-5 

Simple Microcomputer Development Systems 25-4 

Simulating Microcomputer Development Systems 25-4 

Standard Memory Devices Connected to an 8048 Series Microcomputer 6-22 

Subroutine Library 25-8 

Suspension of an SC/MP I/O Cycle 3-9 

Synchronizing Multi-8086 Clock Signals 20-79 

System Timing Element 15-2 

T TMS 1000 Subroutines 1-4 

TMS 5501 Nonstandard Features 4-75 

TMS 5501 Output Signal Inversion 4-69 

TMS 5501 Reset 4-73 

TMS 5501 Wait State 4-70 

TMS 9900 Backward Context Switch 1 8-6 

TMS 9900 Context Switch 18-5 

TMS 9900 Direct Addressing 18-6 

TMS 9900 Forward Context Switch 18-6 

TMS 9900 Implied Addressing 1 8-7 

TMS 9900 Indexed Addressing 18-6 

TMS 9900 Instruction Execution Sequences 18-18 

TMS 9900 Internal Operations Machine Cycle 18-15 

TMS 9900 Interrupt Vector Map 18-27 

TMS 9900 Memory Addresses 18-3 

TMS 9900 Multiple Interrupt Hardware Considerations 18-30 

TMS 9900 Nested Interrupt Priorities 18-29 

TMS 9900 Program Memory Addressing 18-8 

TMS 9940 CRU Bit Utilization 18-59 

TMS 9940 CRU I/O Expansion Mode 1 8-60 

TMS 9940 HOLD Logic 18-64 

TMS 9940 IDLE Logic 18-64 

TMS 9940 Multiprocessor System Interface - 18-61 

TMS 9940 Simple CRU I/O Mode 1 8-59 

TMS 9940 Sync Mode 18-64 



xli 



QUICK INDEX (Continued) 



INDEX PAGE 

TiCont.) TMS 9980 Series Clock Logic 18-49 

Transient Selection, Preventing on an 8085A 5-12 

TTL Level PACE Bus 15-2 

Two 8255 Devices Used for 16-Bit I/O Ports with INS8900 15-43 

TxAKA and TxAKB Signals. MC6844DMAC 9-113 

TxAKA. TxAKB. DMAC. DGRNT. and TxSTB Signals, MC6844 9-114 

TxAKB and TxAKA Signals, MC6844 DMAC 9-1 1 3 

TxRON, DQRT and DGRNT Signals. MC6844 DMAC 9-1 1 2 

TxR0-TxR3 Signals. MC6844 DMAC 9-114 

TxRI Signal. MC6844 DMAC 9-114 

TxR2 Signal. MC6844 DMAC 9-114 

TxR3 Signal. MC6844 DMAC 9-114 

TxSTB Signal, MC6844 D 9-113 

TxSTB Signal. MC6844 DMAC 9-115 

TxSTB. TxAKA, TxAKB, DMAC. and DGRNT Signals. MC6844 9-114 

U Utilities 25-8 

V Variable Cost Contributing Factors 25-1 

Variable Costs 25-2 

W Wait States during 8085 Interrupt Acknowledge 5-29 

Z Zero Status in Chip Slice Logic 22-5 

Z80 Bus Control Signals 7-9 

Z80 CPU Control Signals 7-9 

Z80 Indexed Addressing 7-6 

Z80 LSI Technology 7-1 

Z80 System Control Signals • 7-7 

Z80 Wait States During Interrupt Acknowledge 7-18 

1650 Accumulator 17-4 

1650 Counter/Timer Logic 17-7 

1650 I/O Pin Logic 17-3 

1650 I/O Port Registers 17-3 

1650 Program Counter 17-4 

1650 Program Memory 17-3 
1650 Stackl 7-6 

1650 Status Register 17-5 

1650 Timing 17-8 

1650 Vxx Power Supply 17-8 

2650A Accumulator 11-3 

2650A Branch Instruction Addressing 11-7 

2650A Bus Access Control Signals 11-11 

2650A Bus Contents Identification Signals 11-11 

2650A CPU Execution Control Signals 11-11 

2650A Extended Addressing Options 11-6 

2650A External Device Control Signals 11-12 

2650A Index Registers 11-3 

2650A Interrupt Control Signals 11-12 

2650A Memory Page Selection 1 1-8 

2650A Memory Pages 11-3 

2650A Program Counter 1 1 -3 

2650A Program Relative Addressing Options 11-4 

2650A Stack 11-4 

2901 ALU Operations Specification 24-4 

2901 ALU Source Specification 22-4 



xlii 



QUICK INDEX (Continued) 

INDEX PAGE 

3870 Clock Logic 2-10 

3870 Direct Scratchpad Addressing 2-7 

2 3870 Event Counter Mode 2-17 

5 3870 Expansion 2-3 

3870 Implied Scratchpad Addressing 2-7 
cc 3870 Interrupt Disable 2-13 
8 3870 Interval Timer Mode 2-16 
S 3870 Memory Addressing 2-6 
CO 3870 Pulse Width Measurement Mode 2-16 
H 3870 r Scratchpad Addressing 2-8 

1 3870 Reset 2-10 
o 3870 Scratchpad Memory Addressing 2-6 
« 3870/F8 Accumulator 2-5 
^ 3870/F8 Data Counters 2-6 



3870/F8 Program Counter 2-6 

3870/F8 Scratchpad 2-6 

3870/F8 Stack Register 2-6 



z 
oc 
o 
m 
w 

° 6800 Support Devices Not Compatible with INS8900 15-44 

Q 8T32 IV Byte Access Logic 14-23 

^ 8T32 IV Byte Addressing 14-4 

^ 8T32 IV Bytes 14-4 

8T33 IV Byte Access Logic 14-23 

8T33 IV Byte Addressing 14-4 

8T33 IV Bytes 14-4 

8T35 IV Byte Access Logic 1 4-23 

8T35 IV Byte Addressing 14-4 

8T35 IV Bytes 14-4 

8T36 IV Byte Access Logic 14-23 

8T36 IV Byte Addressing 14-4 

8T36 IV Bytes 14-4 

8X300 Data and I/O Addressing 14-4 

8X300 Program Memory Addressing 14-4 

, 8X300 Rotate and Mask Logic 14-7 

8X300 Shift and Merge Logic 1 4-8 

8035, 8048, and 8748 Reset 6-17 

8041 Buffer Status Register 6-44 

8048 and 8748 Debug Mode 6-15 
8048 Seri( 
8048 Seri( 

8048 Series I/O Port Pin Logic 6-5 

8048 Series I/O Ports 6-5 

8048 Series Machine Cycles and Clock Periods 6-18 

8048 Series Memory Spaces 6-8 

8048 Series Microcomputer, Standard Memory Devices Connected to an 6-22 

8048 Series Microcomputer, 8355 or 8755 Connected to an 6-22 

8048 Series Program Memory Addressing 6-8 

8048 Series Single Stepping 6-15 

8048 Series Verify Mode 6-15 

8048 Wait State 6-20 
8048, 8748, and 8035 Reset 6-17 

8049 Series Microcomputers 6-3 
8080A and INS8900 System Busses Compared 15-43 
8080A and 8086 Registers' Compatibility 20-3 
8080A Carry Status Borrow Logic ■ 4-5 
8080A Carry Status Nomenclature 4-26 



xliii 



es External Memory Access Mode 6-14 

es Internal Execution Mode 6-14 



QUICK INDEX (Continued) 

INDEX PAGE 

8080A Clock Periods 4-7 

8080A Data Bus Definition Signals 4-7 

8080A Direct Addressing 4-5 
8080A Implied Addressing ," 4-4 

8080A Instruction Status 4-10 

8080A interrupt Control Signals 4-7 

8080A Interrupt Response Using CALL Instruction 4-54 

8080A Machine Cycles 4-7 
8080A Slow Memories ,4-13 
8080A Timing Control Signals .4-6 

8080A Wait State Request Logic 4-14 

8085 and 8085A 5-1 

8085 and 8085A, ALE Differences in 5-5 

8085 and 8085A, ALE Generation in 5-18 

8085 and 8085A. Halt State in 5-24 

8085 and 8085A. Hold State in 5-24 

8085 and 8085A, Interrupt Differences in 5-28 

8085 Interrupt Acknowledge 5-29 

8085 Interrupt Acknowledge, Wait States During 5-29 

8085 I/O Write Timing 5-16 

8085 Memory Read Timing 5-15 

8085 Memory Write Timing 5-16 

8085 Multibyte Acknowledge 5-29 
8085, Select Problem with 5-14 
8085A and 8085 5-1 
8085A and 8085, Halt State in 5-24 
8085A and 8085, Interrupt Differences in 5-28 
8085A Bus Control Signals 5-5 
8085A Bus Idle Machine Cycle 5-18 
8085A Clock Periods 5-8 
8085A Control Signals 5-5 
8085A Data Bus Definition Signals 5-5 
8085A Device Select Logic 5-10 
8085A Hold Within a Halt State 5-27 
8085A Interrupt Acknowledge 5-29 
8085A Interrupt Signals 5-5 
8085A Machine Cycles 5-7 
8085A Multibyte Acknowledge 5-29 
8085A Multiple Device Selects and Bus Loading • 5-11 
8085A, Preventing Simultaneous Selection of 1/0 and Memory on an 5-12 
8085A, Preventing Transient Selection on an 5-12 
8085A Reset Signals 5-5 
8085A RIM after TRAP 5-31 
8085A Serial I/O 5-5 
8085A TRAP Interrupt 5-31 

8086 and 8080A Registers' Compatibility - 20-3 
8086 AX Register 20-3 
8086 Base Relative Indexed Addressing 20-13 
8086 BCD Addition 20-43 
8086 BCD Division 20-45 
8086 BCD Multiplication 20-45 
8086 BCD Subtraction 20-43 
8086 Bus Interface Unit (BlU) 20-25 
8086 BX Register 20-3 
8086 Code Segment Register and Program Counter 20-7 
8086 Complex Control Signals ■■ 20-24 
8086 CX Register 20-5 



xiiv 



oc 



u 



QUICK INDEX (Continued) 

INDEX PAGE 

8086 Data Memory Base Relative Addressing 20-1 3 

8086 Data Segment and Stack Segment Registers 20-9 

8086 Direct Indexed Addressing 20-1 2 

8086 Direct Memory Addressing 20-1 1 

8086 DX Register 20-5 

8086 Execution Unit (EU) 20-25 

8 8086 External Memory Addressing 20-20 

2 8086 Extra Segment, Source Index and Destination Index Registers 20-8 

w 8086 HOLD in Maximum Mode System 20-35 

8086 HOLD in Minimum Mode System 20-35 

8086 Implied Memory Addressing 20-12 

o 8086 Indirect Addressing 20-17 

w 8086 Instruction Queue 20-25 

.a 8086 Interrupt Return 20-41 

w 8086 Interrupt Vector Table 20-39' 

DC 8086 I/O Port Addressing 20-17 

m 8086 Maskable Interrupt 20-39.40 

o 8086 Non-Maskable Interrupt 20-39,40 

S 8086 Program Relative Addressing 20-17 

^ 8086 Reset 20-23,79 

< 8086 Segment Registers 20-6 

@ 8086 Simple Control Sgnals 20-24 

8086 Single Instruction Time Identified 20-38 

8086 Software Interrupts 20-38,40 

8086 Stack Segment and Stack Pointer Registers 20-8 

8155 Device Reset 5-38 

8155/8156 I/O Mode 5-38 

8155/8156 I/O Model 5-38 

8155/8156 I/O Port Addresses 5-40 

81 55/81 56 Timer Mode 5-42 

8156/815^ I/O Mode 5-38 

8156/8155 I/O Model 5-38 

8156/8155 I/O Port Addresses 5-40 

82 1 2 I/O Port Used in SC/MP Systems, The 3-32 

8212 Used as a Simple Input Port in an INS8900 System, The 1 5-39 

821 2 Used as an Output Port in an INS8900 System, The 1 5-41 

821 2 Used as an Output Port in an SC/MP System, The 3-33 

821 2 Used in an INS8900 System for Input with Handshaking, The 1 5-40 

8224 Clock Signals 4-46 

8243 Reset 6-53 

8251 USART and 8253 Programmable Counter/Timer Used in INS8900 Systems, The 1 5-43 

8253 Programmable Counter/Timer and 8251 USART Used in INS8900 Systems 1 5-43 

8255 Devices Used for 1 6-Bit I/O Ports with INS8900 1 5-43 

8255 PPI Devices Used in an INS8900 System 1 5-42 

8259 PICU Interrupt Mask 4-63 

8259 PICU Interrupt Masking 4-59 

8259 PICU Interrupt Service Routine Priorities 4-57 

8259 PICU Polling 4-59 

8259 PICU Rotating Interrupt Priorities 4-58 

8284 Wait State Logic 20-79 

8288 Advanced Write Control Signals 20-81 

8288 Bus Controller Interrupt Signals 20-82 

8288 Bus Controller Memory Protect 20-82 

8288 I/O Bus Mode 20-81 

8355 or8755€Qnnected to an 8048 Series Microcomputer 6-22 

8748 and 8048 Dgbug Mode 6-15 

8748 Programming Mode 6-15 

xlv 



QUICK INDEX (Continued) 

INDEX PAGE 

8748, 8048, and 8035 Reset 6-17 

8755 and 8755A 5-51 

8755 or 8355 Connected to an 8048 Series Microcomputer 6-22 

8755A and 8755 5-51 

9080A AMD Status Difference 4-6 

9440 Instruction Fetch 19-23 

9440 Memory Read 19-23 

9440 System Bus 19-14 



xlvi 



c This is the first of two volumes that replace An Introduction to Microcomputers: Volume 2 — Some Real Pro- 

S ducts. This volume describes microprocessors and dedicated support devices. Volume 3 describes general sup- 

2 port devices. 

w We define a "dedicated" support device as one best used with its parent micropirocessor. We define a 

< "general" support device as one which can be iised with any microprocessor. 

o Unfortunately, categorizing support devices as "dedicated" or "general" is not always straightforward. Cer- 

w tainly IM6100 and TMS9900 support devices have CPU interfaces which are peculiar to the parent 

_ microprocessor, so using them with other microprocessors makes little sense. Most MC6800 microprocessor 

lu support devices are also considered dedicated because they use the MC6800 clock signal. This clock signal is 

^ automatically generated by an MC6800 microprocessor or its clock device. It can be derived quite inexpen- 

g sively in other microcomputer systems; nevertheless, we include MC6800 support devices in Volume 2, 

g because in our opinion the added clock logic is not compensated for by any performance capabilities over and 

2 above those which you would find in a competing device that did not require the added clock logic. 

Q When reading Volumes 2 and 3, therefore, you should bear in mind that we have had to be subjective when 

Z^ deciding whether some parts should be described in Volume 2 or Volume 3. Do not automatically use support 

^ parts described in Volume 2 without checking equivalent parts described in Volume 3. Conversely, there may 

be instances where your application is better served by a support device described in Volume 2. In general, you 

can look upon Volume 3 support devices as CPU-independent, while Voliime 2 devices are CPU-dependent. 

In order to cope with the rapid evolution of new parts. Volumes 2 and 3 have been printed loose-leaf. Each 
volume will have six updates per year, appearing at bimonthly intervals. For Volume 2, updates will appear in 
November. January, March, May, July and September. Each September the entire book will be reprinted, in- 
cluding the past year's updates. If you have inserted your updates, you will not need to buy a new book next 
year. For your convenience, an order form may be found at the back of this book. 

SIGNAL CONVENTIONS 

Signals may be active high, active low or active in two states. An active high signal is one which, in the high 
state, causes events to occur, while in the low state has no significance. A signal that is active low causes 
events to occur when in the low state, but has no significance in the high state. A signal that has two active 
states will cause two different types of events to occur, depending upon whether the signal is high or low; this 
signal has no inac tive state. Within this book a signal that is active low has a bar placed over the signal name. 
For example, WR identifies a "write strobe" signal which is pulsed low when data is ready for external logic to 
receive. A signal that is active high or has two active states has no bar over the signal name. 

TIMING DIAGRAM CONVENTIONS 

Timing diagrams play an important part in the description of any microprocessor or support device. Timing 
diagrams are therefore used extensively in this book. All timing diagrams observe the following conventions: 

1) A low signal level is equivalent to no voltage. A high signal level is equivalent to voltage present: 

/———————— Voltage present 



xlvii 



2) A single signal making a low-to-high transition is illustrated like this: 



/ 



high 



3) A single signal making a high-to-low transition is illustrated like this: 

high ■ ■■■! 



low 



4) When two or more parallel signals exist, the notation: 



3E 



signals change 



states that one or more of the parallel signals change level, but the transition (high-to-low or low-to-high) is 
unspecified. 

5) A three-state single signal is shown floating thus: 



Signal 
floating 



r 



6) A three-state bus containing two or more signals is shown floating thus: 



>--.-—-[ 



Bus 
floating 

7) When one signal condition triggers other signal changes, an arrow indicates the relationship as follows: 

Condition 
here 



Causes 

change 

here 

Thus a signal making a low-to-high transition would be illustrated triggering another signal making a high-to-low 
transition as follows: 




A signal making a high-to-low transition triggering a bus change of state would be illustrated as follows: 



^^ 



xlviii 



8) When two or more conditions nnust exist in order to trigger another logic event, the following illustration is used: 

These 
conditions 



cc cause 

2 change 

g here 

U 

- Thus a low-to-high transition of one signal occurring while another signal is low would be illustrated triggering a 

m third event as follows: 



\ 



5 

< 9) When a single triggering condition causes two or more events to occur, the following illustration is used: 



@ 



This 
condition 



causes 

these 

changes 



Thus a low-to-high transition of one signal triggering changes in two other signal levels would be illustrated as 
follows: 




10) All signal level changes are shown as square waves. Thus rise and fall times are ignored. These tihnes are given in 
the data sheets which appear at the end of every chapter. 

INSTRUCTION SET CONVENTIONS 

Every microcomputer instruction set is described with two tables. One table identifies the operations which oc- 
cur when the instruction set is executed, while the second table defines object codes and instruction times. 

Because of the wide differences that exist between one instruction set and another, we have elected not to 
use a single set of codes and symbols to describe the operations for all instructions in all instruction sets. We 
believe any type of universal convention is likely to confuse rather than clarify; therefore each instruction set 
table is preceded by a list of symbols as used within that table alone. 

A short benchmark program is given to illustrate each instruction set. Some comments regarding benchmark 
programs in general are, however, in order. We are not attempting to highlight strengths or weaknesses of 
different devices, nor does this book make any attempt at comparative analyses, since the criteria which make 
one microcomputer better than another are simply too dependent on the application. 



xlix 



ATTENTION WRITERS 

Osborne & Associates is seeking qualified contributors to future updates of Volumes 2 and 3. 
Qualified contributors must have an excellent technical background, they must be able to write clearly, 
and they must be unaffiliated with any manufacturer of semiconductor devices. Faculty at universities 
are particularly welcome as contributors. 

A contributor, when selected, will be assigned a specific category of parts to keep updated. Keep- 
ing parts updated will include describing new parts in the category as they appear, and improving the 
description of parts that are already covered. 

If you would like to become a contributor to Volume 2 and/or Volume 3, please write stating your 
qualifications and the categories of parts that you believe you could cover competently. If possible, send 
us a sample of your work; we suggest two or three pages of a part description following the format pre- 
sented in these books as closely as possible. Send material to: 

OSBORNE & ASSOCIATES, INC. 
P.O. Box 2036 
Berkeley, California 94702 
Attention: Volume 2/3 Contributors 



Chapter 1 

4-BIT MICROPROCESSORS AND THE TMS1000 

SERIES MICROCOMPUTERS 



o 

m 

V) 

O 

< 

< 



The earliest microprocessors were all 4-bit devices; that is to say, data was operated on in 4-bit units, frequently refer- 
red to as "nibbles". Early microprocessors were 4-bit devices simply because the concept of an LSI CPU was am- 
bitious enough; starting with an 8-bit CPU would have been foolhardy. 

But LSI technology has advanced so rapidly that there is an inconsequential difference between the cost of manufac- 
turing an 8-bit CPU chip as against a 4-bit chip. Manufacturers attempted to maintain an artificial price differential bet- 
■ ween their 4-bit and 8-bit CPUs in order to prolong the life of the 4-bit product; but the pressure of competition has all 
but extinguished these price differentials — with the result that the 4-bit microprocessor is a dying product. Price is the 
only advantage that 4-bit microprocessors offer when compared to the more capable 8-bit microprocessor. 

Early 4-bit microcomputers included such devices as the Intel 4004 and 4040 and the National Semiconductor IMP-4. 
These early 4-bit microcomputers require package counts that exceed typical 8-bit microcomputers that are now 
available; therefore the economics of today dictate that the Intel 4004, the Intel 4040 and the IMP-4 offer less 
capability for more money. Only the most unusual application could be more economically implemented using one of 
these three 4-bit microcomputers, rather than a simple 8-bit device such as the 3870, COSMAC, 8048, or one of the 
38-pin MCS6500 series CPUs. We consider the Intel 4004, the Intel 4040 and the IMP-4 to be obsolete devices; 
therefore they are not described. 

It is interesting to note that even though these three 4-bit microcomputers are obsolete, they will continue to have a 
significant market for many years to come, based on products that were designed around them before they became ob- 
solete. The fact that they are obsolete simply means that, were you to design a new product today, you would be better 
off using one of the simple 8-bit microcomputers. That does not mean it would be economical to redesign a product 
that already exists, simply to take advantage of more recent microcomputer developments. The cost of re-engineering 
around a new microcomputer will likely overwhelm any savings that may accrue. 

The TMS1000 series microcomputer devices, initially manufactured by Texas Instruments, are still econom- 
ically very viable — even though they are 4-bit devices. This is because the TMS1000 is a one-chip microcom- 
puter. ROM, RAM, CPU and I/O logic are all provided within a single package. The low cost associated with the 
single-chip TMS1000 microcomputer pacl<age makes this the product of choice for a large number of simple ap- 
plications that can be accommodated within the logical confines of the TMS1000. 

In reality, the TMS1000 is a family of six 4-bit microcomputers whose differences are summarized in Table 1-1. 
The various microcomputers are sufficiently similar for us to describe them together. PMOS and CMOS versions 
are now available. Some CMOS versions manufactured by Motorola have the part number MCI 41 000. 





Table 1-1. TMS1000 Series Microcomputer Summary 










TMS 


TMS 


TMS 


TMS 


TMS 


TMS 


TMS 


TMS 


MC 


MC 




1000 


1200 


1070 


1270 


1100 


1300 


1000C 


1200C 


141000 


141200 


Package Pin Count 


28 


40 


28 


40 


28 


40 


28 


40 


28 


40 


ROM Program Bytes* 


1024 


1024 


1024 


1024 


2048 


2048 


1024 


1024 


1024 


1024 


RAM Data Nibbles" 


64 


64 


64 


64 


128 


128 


64 


64 


64 


64. 


R Signal Outputs 


11 


13 


11 


13 


11 


16 


10 


16 


11 


16 


Data Outputs 


8 


8 


8 


10 


8 


8 


8 


8 


8 


8 


Maximum Rated Voltage 


20 


20 


35 


35 


20 


20 


6 


6 


6.5 


6.5 


Typical Power Dissipation 


15V/ 


15V/ 


15V/ 


15V/ 


15V/ 


15V/ 


5V/ 


5V/ 


5V/ 


5V/ 




90mW 


90mW 


90mW 


90m W 


90mW 


90mW 


15mW 


5mW 


2.5mW 

3V/ 
0.5mW 


2.5mW 

3V/ 
0.5mW 



*A Byte is eight bits "A Nibble is four bits 



1-1 



Figure 1-1 illustrates that part of our general microcomputer system logic which is implemented by the 
TMS1000 series microcomputers. This figure is deceptive, since it would be hard to compare the primitive I/O 
capabilities of the TMS1000 with a device such as the 8255 Programmable Peripheral Interface device, which 
is described in Volume III. Nevertheless, Figure 1-1 does indicate the logic which is provided by a TMS1000 
series microcomputer, albeit in a primitive form. 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Interrupt Priority 
Arbitration 



Bus Interface 
Logic 



Accumulator 
Register(s) 



Data Counter(s) 



Stack Pointer 



Program Counter 



Direct Memory 

Access Control 

Logic 



System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 
Interface Logic 



t/0 Ports 
Interface Logic 



Read Only 
Memory 



RAM Addressing 

and 

Interface Logic 



I/O Ports 



Read/Write 
Memory 



Figure 1-1. Logic of the TMS 1000 Series Microcomputer 

The fact that the TMS1000 series microcomputers are single-chip devices has a number of secondary, non-ob- 
vious Implications. Most inliDortant of all, there are no such things as support devices. The 1024 or 2048 bytes of ROM 
represent the exact amount of program memory which will be present; there can be neither more nor less. Similarly, 
the 64 or 128 nibbles of RAM cannot be expanded. Direct memory access logic is not present — and its presence 
would make very little sense anyway; with the small total ROM and RAM memory available, there simply is not the op- 
portunity to transfer blocks of data long enough to warrant bypassing the CPU. 

Interrupts, similarly, would be of marginal value to a TMS1000 microcomputer. Given the small amount of program 
memory available and the very low cost of the package, it would be hard to justify the complexities of interrupt logic, 
simply to have the microcomputer perform more than one task. 

All devices of the TMS1 000 microcomputer family are implemented using PMOS technology. Selected CMOS parts are 
also available. 



1-2 



A single -15V power supply is required for PMOS parts. CMOS parts use power supplies in the range +3V to +6.5V. 

The fastest clock frequency which can drive a TMS1000 series microcomputer has a 2.5 microsecond cycle time. Ail in- 
structions execute in six clock cycles, or 15 microseconds; but beware of making direct execution speed comparisons 
between the TMS1000 and the 8-bit microcomputers which are described next. A TMS1000 program will usually be 
considerably longer than the 8-bit microcomputer equivalent because the TMS1000 instruction set is more primitive; 
but this is not always true. It is possible for the TMS1000 instruction set to equal or surpass many 8-bit 
microprocessors, in terms of instruction efficiency, for certain control applications. 

The prime manufacturer of the TMS1000 is: 

TEXAS INSTRUMENTS, INC. 
P.O. Box 1443 
Houston, Texas 77001 , 

A second source for CMOS parts with MCMxxxx part numbers (see Table 1-1) is: 

MOTOROLA INCORPORATED 

CMOS Products Division 

3501 Ed Bluestein Blvd. 

Austin, Texas 78721 



2 
< 

o 

< 

® 



TMS1000 PROGRAMMABLE REGISTERS 

TMS1000 programmable registers may be illustrated as follows: 



4-bit Accumulator 



2- or 3-bit X register 
4-bit Y register 



6- or 7-bit Data Counter 



D 



6-bit Program Counter 

4-bit Page register 

1-bit Chapter flag (optional) 



10- or 11-bit Program Counter 



6-bit Subroutine Return register 
4-bit Page Buffer register 



Apart from being only four bits wide, the Accumulator is a typical primary Accumulator. It is the principal source and 
destination for data that is being operated on. 



1-3 



Taken together, the X and Y registers constitute a 6- or 7-bit Data Counter which addresses the 64 or 128 nibbles 
of RAM. The X register is two or three bits wide and the Y register is four bits wide. Since the X and Y registers are in- 
deed separate and distinct registers, RAM is effectively divided into four or eight pages, each of which is 16. nibbles 
long. A four-page RAM nnay be illustrated as follows: 



4-Bit 

DATA 

MEMORY 

NIBBLES 




PageO 



Page 1 



Page 2 



Page 3 



The Y register, in addition, serves as a secondary Accumulator and an output Address register. We will describe 
its use as an output Address register shortly. 

Those TMS1000 series microcomputers that provide 128 nibbles of RAM have a 3-bit X register. RAM is then divided 
into eight 16-nibble pages. 

The Program Counter and Page Address register, talcen together, constitute a 10-bit Program Counter. They are, 
in reality, separate and distinct registers, with the result that program memory is divided into sixteen 64-byte pages. 

Those TMS1 000 microcomputers that provide 2048 bytes of program memory have an additional 1-bit flag, 
referred to as Chapter Logic, which is used to select one of two alternate 1024-byte ROM chapters. 



TMS1000 
SUBROUTINES 



The Subroutine Return register is simply a buffer for the Program Counter register. Similarly, 
the Page Buffer register is a simple buffer for the Page Address register. These two buffer 
registers allow the TMS1000 a single level of subroutine call logic. When a subroutine is called, 

the contents of the Page Address and Page Buffer registers are exchanged, the Program Counter register contents are 
moved to the Subroutine Return register, and a new value provided by the subroutine Call instruction is loaded into the 
Program Counter. This may be illustrated as follows: 



Instruction object code 




Program Counter 



Page Address register 



Subroutine Return register 
Page Buffer register 



1-4 



EC 

o 

GQ 
(0 
O 

< 

Q 
< 



TMS1000 MEMORY ADDRESSING MODE 

TMS1000 microcomputers have separate and distinct program and data memories. There are no instructions 
capable of writing into program memory, and data memory cannot contain instruction object codes. 

Data memory is accessed using implied addressing. The X and Y registers combine to serve as a Data Counter; we 
have just described this use of the X and Y registers. 

Only subroutine Call instructions and Branch instructions address program memory. These instructions address 
program memory using variations of absolute, paged direct addressing. 

We have already illustrated the addressing logic of a subroutine call. 

A Branch instruction loads the Program Counter with a new address, which is provided by the instruction, just as a Call 
instruction does. If the Branch instruction occurs in a subroutine — that is, in the sequence between a subroutine Call 
instruction and a subroutine Return instruction — the Page Address register will not be affected. However, execution 
of a Branch instruction outside a subroutine will load the Page Address register from the Page Buffer register. The two 
types of program branches may be illustrated as follows: 

Instruction object code 



r 






"1 








n 




\ 


Program Counter 








1 












Page Address register" 








J 



Page Buffer register 




Only if Branch opcurs 
outside a subroutine 



TMS1 000 STATUS FLAGS 

The TMS1000 series microcomputers have a single status flag which combines to serve as a Carry status and a 
simple logic decision status. All Branch and subroutine Call instructions are conditional; the Branch or subroutine 
Call occurs only if the status flag is 1. 

The unique feature of the status flag as compared to most status logic is that its passive level is high (1). If an instruc- 
tion causes the status flag to be reset to 0, it will revert to 1 after a single instruction cycle: 



CLOCK 



STATUS 



Revert 




I Instruction | Instruction 

I ^ I 2 , 



Instruction 
3 



Instructions that test the condition of the status flag must directly follow the instruction which modifies the level of the 
status flag. 

TMS1 000 INPUT AND OUTPUT LOGIC 

The only data input to a TMS1000 series microcomputer occurs as 4-bit nibbles, referred to in Texas Instru- 
ments literature as K inputs. Instructions that access the K inputs simply input whatever signal levels exist at the time 
of the access. 

TMS1000 series microcomputers output data referred to as O outputs, and control signals referred to as R out- 
puts. 



1-5 



There are eight data or outputs; but they are created in an unusual way. output logic receives, as inputs, the con- 
tents of the Accumulator, plus the status flag. These five data bits create the eight output signals according to a 
matrix which you must define when you order the TMS1000 microcomputer. This may be illustrated as follows: 



Accumulator 
Contents 



Status flag 





Output 
Matrix 










^' 




^- 















outputs 



As the illustration above would imply, the five inputs select 32 of the possible 256 signal combinations which can be 
output via the eight outputs. 

The control R outputs are treated as 1 1 , 1 3 or 1 6 single control signals. Refer to Table 1 -1 , which identifies the number 
of R output signals available with each of the TMS1000 series microcomputers. You can set or reset R output signals 
individually. The Y register is used to identify the individual R signal which is being set or reset. 

TMS1000 SERIES MICROCOMPUTER PINS AND SIGNALS 

Figures 1-2 through 1-7 illustrate the pins and signals of the TMS1000 series microcomputers. Note that the 
TMS1000 and TMS1 100 microcomputers have identical pins and signals. Since signals are consistent for the entire 
family of microcomputers, they will be described together. 

The four data inputs are provided by K1, K2, K4 and K8. We would name these signals DIO, DI1, DI2 and DI3 to be 

consistent with common microcomputer terminology; however, Texas Instruments literature uses the signal names K1 , 
K2, K4 and K8 to represent the binary level of each signal. 




28 


► 


27 


^ 


26 


^^ 


^^ 


25 


► 


24 


b^ 




23 


►■ 


22 
21 


Ita 


^ 


20 
19 

18 




-^ 


17 
16 


»^ 






15 


^' 



R7 

R6 

R5 

R4 

R3 

R2 

R1 

RO 

Vss'VdD'"MC 141000) 

0SC2 

0SC1 

00 

01 

02 



Pin Name 

K1, K2, K4, KB 
00-07 
R0-R10 
0SC1, 0SC2 
INIT 

Vdd. Vss 



Description 

Data input 

Data output 

Control output 

Timing 

Power on reset 

Power and Ground 



Type 

Input 

Output 

Output 

Input 

Input 



Figure 1-2. TMS1000 and MC141000 Microcomputer Signals and Pin Assignments 



1-6 



< 

Q 

< 

© 




Pin Name 

K1, K2, K4, KB 

00-07 

R0-R12,R13-R15 

0SC1, 0SC2 

INIT 

VdD' Vss 



Description 

Data input 
Data output 
Control output 
Timing 

Power on reset 
Power and Ground 



13 ) 



in MC 14 1200 only 



R2 

R1 

RO 

Vss(Vdd in MCI 41200) 

0SC2 

0SC1 

OO 

01 

02 



Type 

Input 

Output 

Output 

Input 

Input 



Figure 1-3. TMS1200 and MCI 41 200 Microcomputer Signals and Pin Assignments 



R8 

R9 

RIO 

Vdd 

K1 
K2 
K4 
KB 
INIT 
07 
06 
05 
04 
03 





1 28 

2 27 

3 26 

4 25 

5 24 

6 23 

7 TMS1070 22 

8 21 

9 20 

10 19 

11 18 

12 17 

13 16 

14 15 








^ 












^ 




— ► 


► 


— ^ 


^- 


■^ 


-^ 




^ 




^ 







Pin Name 

K1, K2, K4, KB 
00-07 
R0-R10 
0SC1, 0SC2 
INIT 

Vdd- Vss 



Description 

Data input 

Data output 

Control output 

Timing 

Power on reset 

Power and Ground 



R7 
R6 
R5 
R4 
R3 
R2 
R1 

vss 

RO 

0SC2 

0SC1 

00 

01 

02 



Type 

Input 

Output 

Output 

Input 

Input 



Figure 1-4. TMS1070 Microcomputer Signals and Pin Assignments 



1-7 




TMS1270 




Pin Name 

K1,K2, K4, K8 

00-09 

R0-R12 

0SC1, 0SC2 

INIT 

VdD' Vss 



Description 

Data input 
Data output 
Control output 
Timing 

Power on reset 
Power and Ground 



Type 

Input 

Output 

Output 

Input 

Input. 



Figure 1-5. TMS1270 Microcomputer Signals and Pin Assignments 




Pin Name 

K1, K2, K4; K8 
00-07 
R0-R10 
0SC1, 0SC2 
INIT 

VdD' Vss 



Description 

Data input 
Data output 
Control output 
Timing 

Power on reset 
Power and Ground 



Type 

Input 

Output 

Output 

Input 

Input 



Figure 1-6. TMS1100 Microcomputer Signals and Pin Assignments 



1-8 



V) 

w 

< 

a 

m 

Z 
oc 
o 

CO 

» 
o 

< 
o 

< 

@ 




Pin Name 

K1, K2, K4, K8 
00-07 
R0-R15 
0SC1, 0SC2 
INIT 

Vdd- Vss 



Description 

Data input 
Data output 
Control output 
Timing 

Power on reset 
Power and Ground 



Type 

Input 

Output 

Output 

Input 

Input 



Figure 1-7. TMS1300 Microcomputer Signals and Pin Assignnnents 

The O outputs are provided by 00 - 07, or, in the case of the TMS1270, OO - 09. 

The R outputs occur at RO - R15, or some smaller number of R outputs, depending on the microconnputer. 

0SC1 and 0SC2 are timing inputs and outputs. A number of timing options are provided. All IMS 1000 series 
microcomputers contain internal clock logic which you can access in conjunction with an external RC circuit as 
follows: 



0SC1 



0SC2 



^f 



-VA- 



vss 



Vdd 



You can also input an externally created clock signal at 0SC1, in which caseOSC2 must be connected to ground (Vss)- 
When you have more than one TMS1000 series microcomputer in a configuration, it is a good idea to synchronize the 
many microcomputers by driving them with a single clock signal. 

INIT is a power on reset signal. Following power on, INIT should be input high (Vss) for ^^ 'e^st six consecutive clock 
cycles. The Reset operation stores binary ones in the Page Address register and the Page Buffer register. The outputs, 
the R outputs and the Program Counter are all zeroed. Thus, the first instruction executed will have the hexadecimal 
address 3C0i 6- 



Page Address register 



Program Counter 



1 1 1 10 
3 C 



1-9 



TMSIOOO SERIES MICROCOMPUTER INSTRUCTION EXECUTION 

No. microcomputer described in this booi< has simpler instruction execution timing than the TMSIOOO series. All in- 
structions generate one byte of object code. There are no two- or three-byte object codes. Similarly, every instruc- 
tion executes in a single machine cycle, as timed by the system clock. 

TMSIOOO SERIES MICROCOMPUTER INSTRUCTION SET 

There are variations in the instruction sets of the different microcomputers in the TMSIOOO series. However, the 
different instruction sets are similar enough for us to describe them all in Table 1-2. As compared to similar tables 
for other microcomputers in this book. Table 1-2 has an additional column which identifies the instructions which are 
available with each of the TMSIOOO series microcomputers. 

Within the confines of a single-chip microcomputer, the instruction set defined in Table 1-2 is both powerful and effec- 
tive, it would be easy to point out instruction set features which, from a programmer's point of view, are undesirable; 
however, the TMSIOOO series microcomputers are oriented to digital logic. The TMSIOOO is not a product that gets 
programmed; rather, its instruction set is a means of defining an optional portion of the ROM mask. Within this context, 
the instruction set is very adequate. Note that, since you are dealing with a single-chip microcomputer, there is 
nothing to prevent you from redefining the Control Unit and thus creating your own instruction set. 

THE BENCHMARK PROGRAM 

The benchmark program we are using throughout this book in order to exercise the various microcomputer instruction 
sets is essentially meaningless in any TMSIOOO application. Given 64, or at most, 128 nibbles of RAM, the whole con- 
cept of moving data among tables is meaningless. We therefore simplify the problem and look upon lOBUF as external 
logic. Instead of reading from lOBUF, we will input K data. We will assume that each block of K data is preceded by a 
nibble which defines the number of data nibbles to follow: 



Kl 
K8 



n data nibbles 
follow 

Thus, each block of data that is input must be fifteen nibbles or less in length. 

LDX TBHI LOAD TABLE PAGE ADDRESS 

TKA INPUT FIRST K NIBBLE. IT EQUALS DATA NIBBLE TO FOLLOW 

TAY MOVE TO Y. XY NOW ADDRESSES END OF TABLE 

LOOP TKA INPUT NEXT DATA NIBBLE 

TAM SAVE IN MEMORY 

DYN DECREMENT Y 

BR LOOP IF Y NOT 0, RETURN FOR NEXT NIBBLE 

Symbols are used in Table 1-2 as follows: 

Registers: 

A - Accumulator 

X,Y - Data Counter. Y also serves as an output address. 

PC - Program Counter 

PA - Page Address register 

CF - Chapter Flag (one bit) 

SR - Subroutine Return register 

PB - Page Buffer 



Statuses: 



ST - The Status Flag 
C - The status flag reflects a Carry. That is, it is set if there is a Carry from the most significant bit 

(MSB), and reset otherwise. 
NE - The status flag reflects "not equal". That is, it is set if the compared bits are not equal, and reset 

if they are equal. 



1-10 



Inputs and Outputs: 

K - the four input lines 

- the five-bit Output register 

R - the control outputs 



bb 



Two bits in the object code which specify one of the four bits of a RAM location: 



o 

m 

CO 

O 

< 
Q 

< 

@ 




b Operand which specifies one bit of a RAM location 

data 2. 3, or 4 bits of imnnediate data 

label Destination of Branch instruction (6 bits of direct address in the object code) 

R([Y]) The control output line specified by the contents of the Y register. 

X , One bit of immediate data or direct address in the object code. 

[X](MSB) The most significant bit of the X register 

[[X,Y]] The contents of the RAM location addressed by the contents of the Data Counter. 

[[X,Y]](b) The specified bit of the RAM location addressed by the contents of the Data Counter. 

[ ] Contents of location enclosed within brackets. If a register designation is enclosed within the brackets, 

then the designated register's contents are specified. If K or R is enclosed within the brackets, then the 

data at the inputs or control outputs is specified. 

' ► Data is transferred in the direction of the arrow. 

' — ► Data is exchanged between the two locations designated on either side of the arrow. 

Where two object codes are given, the first is the code used in the TMS1000, TMS1200, TMS1070, and TMS1270, 
while the second is the object code used in the TMS1 100 and TMS1300. 

X in one of the rightmost three columns means that the instruction is implemented on the designated TMS1000 device. 



1-11 



Table 1-2. TMS 1000 Series Instruction Set Summary 



TYPE 


MNEMONIC 


OPERAND 


STATUSES 


OPERATION PERFORMED 


OBJECT 
CODE 


TMS1000 
TMS1200 
TMS1070 
TMS 1270 


TMS1100 
TMS1300 


MCI 41 000 
MC141200 


C 


NE 


O 


KNEZ 
TKA 
SETR 
RSTR 
TOO 
CLO 






X 


If [K]^0, ST — 1 

Set status only if data on Input lines is not 0. 
[K]-[A] 

Load Accumulator with data on input lines. 
R([Yl)-1 

Set R output addressed by contents of Y. 
R(tY])— 

Reset R output addressed by contents of Y. 
[0]-([A],ST) 

Transfer data from Accumulator and status flag to the outputs. 
10] -00,. 

Clear the Output register. 


09 
OE 
08 

OD 

OC 

OA 

OB 


X 
X 
X 
X 
X 
X 


X 
X 

X 

X 

X 


X 
X 
X 
X 
X 
X 


>• 
EC 

iui 
2 UJ 

^£ 

c u. 

< UJ 

0. 


TAM 
TMY 
TMA 
XMA 








[Al-[[X,Yn 

Store Accumulator to RAM location addressed by contents of XY Data Counter. 
[(X.Y]]-[Y] 

Load Register Y from RAM. 
[[X.Y]]-[A1 

Load Accumulator from RAM. 
[[X.Y)]— [A] 

Exchange contents of RAM location addressed by Data Counter XY with those of 

Accumulator. 


03 
27 
22 

21 

2E 
Q3 


X 
X 
X 
X 


X 
X 

X 
X 


X 
X 
X 

X 


PRIMARY MEMORY 

REFERENCE 

WITH REGISTER OPERATE 


TAMIY 
TAMIYC 

TAMDYN 

TAMZA 




X 
X 




[Al-UX.Yll; [Y]-[Y]+1 

Store Accumulator to RAM and increment contents of Y register. 
[ A]-[[X,Y]]; [Y]-[Y] + 1; ST -C 

Store Accumulator to RAM and increment contents of Y register. Set status flag 

only if there is a carry. 
[A]-I[X,Y]]; [Y]-[Y]-1:ST-C 

Store Accumulator to RAM and decrement contents of Y register. Set status flag 

only if there is no borrow. 
(A]-I[X,Y1]; [Al-0 

Store Accumulator to RAM and then clear Accumulator. 


20 
25 

24 

04 
26 


X 
X 


X 
X 

X 


X 
X 


SECONDARY MEMORY 

REFERENCE 

(MEMORY OPERATE) 


AMAAC 

SAMAN 

IMAC 




X 
X 
X 




[A]-[[X,Y]]+ [A];ST-C 

Add contents of RAM location to those of Accumulator. Set status flag only if 

there is a carry. 
[A]-[[X,Y]].[A]:ST-C 

Subtract Accumulator contents from those of RAM location. Set status flag only 

if there is no borrow. 
[A]-[[X.Y]]+1;ST-C 

Load contents of RAM location to Accumulator and increment. Set status flag 

only if there is a carry. RAM contents are unchanged. 


25 
06 

27 
3C 

28 
3E 


X 
X 
X 


X 
X 
X 


X 
X 
X 



© ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 1-2. TMS1000 Series Instruction Set Summary (Continued) 



TYPE 


MNEMONIC 


OPERAND 


STATUSES 


OPERATION PERFORMED 


OBJECT 
CODE 


TMS1000 
TMS1200 
TMS1070 
TMS1270 


TMS1100 
TMS1300 ' 


MC141000 
MCI 41 200 


C 


NE 


SECONDARY MEMORY REFERENCE 

(MEMORY OPERATE) 

(CONTINUED) 


OMAN 

ALEM 

MNEA 

MNEZ 
SBU 

RBrr 

. TBm 


b 
b 


X 
X 


X 
X 

X 


[A]-[[X,Y]M:ST-C 

Load contents of- RAM location to Accumulator and decrement. Set status flag 

only If there is no borrow. RAM contents are unchanged. 
If (A]«[[X,Y]],ST-1 

Set status flag only if Accumulator contents are less than or equal to those of 

RAM location addressed by Data Counter XY. 

If [[X,Y)]j'(A],ST-l 
Set status flag only if contents of RAM location are not equal to those of Ac- 
cumulator. 

If [[X,Y]]y£0, ST-1 
Set status flag only if contents of RAM location are tiot equal to zero. 

[[X,Y]](b)-1 
Set specified bit of RAM location addressed by contents of Data Counter XY. 

[(X.Y]Kb)-0 
Reset specified bit of RAM location addressed by contents of Data Counter XY. 

ST — I[X,YlKb) 

Test specified bit of RAM location and set status flag only if the bit is set. 


2A 
07 

29 
01 

00 

26 

3F 

OOn'bObb 

OOllOIbb 

0011 lObb 


X 
X 

X 
X 
X 
X 


X 

X 
X 

X 
X 

X 
X 


X 
X 

X 
X 
X 
X 


< 
5 

lU 

S 
1 


ICY 

TCMIY 

LDX 

LDP 


data 
"data 
data, 
data 


- 




[Yl— data 

Load Register Y immediate. 
([X,Y]1— data; [Yl— IY] + 1 

Load RAM location immediate and increment contents of Register Y. 
[X]— data 

Load Register X immediate. 
IPS]— data 

Load Page Buffer register immediate. 


OlOOxxxx 

OIIOxxxx 

OOinixx 
OOlOlxxx 
OOOIxxxx 


X 
X 
X 
X 


X 
X 

X 
X 


X 
X 

X 


UJ 

oc 

UJ 

Q. 

o 

UJ 

Q 

UI 


ALEC 

YNEC 
A2AAC 
A3AAC 
A4AAC 
ASAAC 
A6AAC 
A7AAC 


data 
data 


X 

X 
X 
X 
X 
X 
X 


X 


If. [A] «< data, ST — 1 

Set status flag only if Accumulator contents are less than or equal to immediate 

data. 
If [ Y] 7^ 'data, ST — 1 

Set status flag only if contents of Register Y are not equal to immediate data. 
[Al— [A] + 2;ST— C 

Add 2 to Accumulator contents. Set status flag only if there is a carry. 
[A]— [A] + 3: ST— C 

Add 3 to Accumulator contents. Set status flag only if there is a carry. 
[A]— [A] + 4;ST— C 

Add 4 to Accumulator contents. Set status flag only if there is a canv. 
[A]— [A] + 5;ST— C 

Add 5 to Accumulator contents. Set status flag only if there is a carry. 
[A]-IA1 + 6;ST-C 

Add 6 to Accumulator contents. Set status flag only if there is a carry. 
[A]-[Al + 7;ST— C 

Add 7. to Accumulator contents. Set status flag only if there is a carry. 


Olllxxxx 

OlOlxxxx 

78 

74 

7C 

72 

06 
7A 
76 


X 
X 

X 


X 
X 
X 
X 
X 

X 


X 
X 

X 



Table 1-2. TMS1000 Series Instruction Set Summary (Continued) 



TYPE 


MNEMONIC 


OPERAND 


STATUSES 


OPERATION PERFORMED- 


OBJECT 
CODE 


TMS1000 
■TMS1200 
TMS1070 
TMS1270 


TMS1100 
TMS1300 


MC141000 
MCI 41 200 


C 


NE 


UJ Q 

0. lU 

°i 

^^ 

5 o 


A8AAC 
A9AAC 
A10AAC 

A11AAC 
A12AAC 
A13AAC 
A14AAC 




X 
X 
X 

X 
X 
X 
X 




[A]-[A] + 8;ST-C 

Add 8 to Accumulator contents. Set status flag only if there is a carry. 
[A]— EA] + 9;ST— C 

Add 9 to Accumulator contents. Set status flag only if there is a carry. 
IA]-[A]+10;ST-C 

Add 10 to Accumulator contents. Set status flag only if there is a carry. 

[A]— [A]+11;ST— C 

Add 1 1 to Accumulator contents. Set status flag only if there is a can7. 
[A]-[A]+12;ST-C 

Add 12 to Accumulator contents. Set status flag only if there is a carry. 
[A]— [A] +13; ST— C 

Add 13 to Accumulator contents. Set status flag only if there is a carry. 
[Al — [A] + 14;ST— C 

Add 14 to Accumulator contents. Set status flag only if there is a carry. 


01 
7E 
71 

05 
79 

75 
7D 
73 
7B 


X 
X 


X 
, X 

X 
X 

X 

X 

X 


X 
X 


a. 
S 

3 

.-5 


RETN 








[PC] — [SR], [PAl— [PB] 
Return from subroutine. 


OF 


X 


X 


X 


So 

m o 


BR 
CALL 


label 
label 






If ST = 1, then [PC] — label; 
outside subroutine, [PA]>^[PB] 
Branch if status flag Is set. 

If ST = 1,then [SR]— [PCl+1, [PB]- >[PA], [PC]-!label 

Call subroutine if status flag is set. A subroutine call within a subroutine will act as 
a branch, and load the Page Buffer from the Page Address register: 
[PC]— LABEL 
[PB]-[PA] 


lOxxxxxx 
llxxxxxx 


X 
X 


X 
X 


X 
X 


REGISTER- 
REGISTER 
MOVE 


TAY 
TYA 








[A]-[Y] 

Transfer Accumulator contents to Register Y. 
[Y]-[A] 

Transfer Register Y contents to Accumulator. 


24 
20 
23 


X 
X 


X 
X 


X 
X 


1 

1- 1- 5 

M M K 
5 5 UJ 
UJ UJ CL 

K e o 


YNEA 






X 


If [Y] it [A], ST — 1 

Set status flag only if contents of Y register are not equal to those of Accumula- 
tor. 


02 


X 


X 


X 


M S 

a ui 

m Ik 

a O 


CLA 
lA 
lAC 




X 




[Al-0 

Clear Accumulator. 
[A]-[A] + 1 

Increment Accumulator. No status affected. 
[A]-[A] + 1;ST-C 

Increment Accumulator. Set status flag only if there Is a can7. 


2F 
7F 
OE 

70 


X 
X 


X 
X 


X 
X 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 1-2. TMS1000 Series Instruction Set Summary (Continued) 



TYPE 


MNEMONIC 


OPERAND 


STATUSES 


OPERATION PERFORMED 


OBJECT 
CODE 


TMS1000 
TMS1200 
TMS1070 
TMS1270 


TMS1100 
TMS1300 


MC141000 
MC141200 


C 


NE 


UJ 

is 

111 lU 

St = 

Oz 

Si 

i§ 

lU 


DAN 

lYC 

DYN 

CPAIZ 

COMX 
COMX 
COMC 




X 
X 
X 
X 




[Al-rA]-1;ST— C 

Decrement Accumulator. Set status flag only if there is no borrow. 
[Y]-IY] + 1;ST— C 

Increment Register Y. Set status flag only If there is a carry. 
[Y]~[Y]-1;ST-C 

Decrement Register Y. Set status flag only if there is no bon^ow. 
[A] — tA]+1;if [A] =0,ST — 1 

Negate Accumulator contents (twos complement). Set status only if result is 

zero. 
[X]-[X] 

Complement contents of X register (ones complement). 
[X](MSB)— [XKMSB) 

Complement most significant bit of X register. 
CF— CF 

Complement Chapter flag. 


07 
77 
2B 
05 
2C 
04 
2D 
3D 

00 

09 

OB 


X 
X 
X 
X 

X 


X 
X 
X 
X 

X 
X 


X 
X 
X 
X 

X 



DATA SHEETS 

This section contains specific electrical and timing data for the TMS 1000 series microcomputer. 



o 

m 

V) 

o 

< 

< 
(Q) 



1-D1 



TMS 1000/1200 AND TMS 1100/1300 

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE 
(UNLESS OTHERWISE NOTED)* 

Voltage applied to any device terminal (see Note 1) —20 V 

Supply voltage, Vqd -20 V to 0.3 V 

Data input voltage -20 V to 0.3 V 

Clock input voltage -20 V to 0.3 V 

Average output current (see Note 2): outputs — 24 mA 

R outputs -14 mA 

Peak output current: outputs —48 mA 

R outputs -28 mA 

Continuous power dissipation: TMS 1000/1100 NL 400 mW 

TMS 1200/1300 NL 600 mW 

Operating free-air temperature range 0°C to 70°C 

Storage temperature range — 55°Cto150°C 

•Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" 
section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 

RECOMMENDED OPERATING CONDITIONS 



PARAMETER 


MIN 


NOM 


MAX 


UNIT 


Supply voltage, Vqd (see Note 3) 


-14 


-15 


-17.5 


V 


High-level input voltage, Vm (see Note 4) 


K 


-1.3 


-1 


0.3 


V 


INIT or Clock 


-1.3 


-1 


0.3 


Low-level Input voltage, V|l (see Note 4) 


K 


Vdd 




-4 


V 


INIT or Clock 


Vdd 


-15 


-8 


Clock cycle time, tc(^) 


2.5 


3 


10 


MS 

MS 


Instruction cycle time, t^ 


15 




60 


Pulse width, clock high, t^{^H) 


1 


MS 


Pulse width, clock low, tyv((i>L> 


1 


MS 


Sum of rise time and pulse width, clock high, t^ 


+ tw(<i>H) 


1.25 


MS 


Sum of fall time and pulse width, clock low, tf + tw((f)L) 


1.25 


MS 


Oscillator frequency, fojc 


100 




400 


kHz 


Operating free-air temperature, T/^ 







70 


°C 



NOTES: 1. Unless otherwise noted, all volteges are with respect to Vss- 

2. These average values apply for any 100-ms period. 

3. Ripple must not exceed 0.2 volts peak-to-peak in the operating frequency range, 

4. The algebraic convention where the most-positive (least-negative) limit is designated as maximum is used in this specification for 
logic voltage levels only. 



vss - 



Vdd 




V|H(0) 



'lL(0) 



I |< tvy{0L) — ►! \*— tw(0H) 



I*- 



<c(0) 



NOTE: Timing points are 90% (high) and 10% (low). 

FIGURE 7 - EXTERNALLY DRIVEN CLOCK INPUT WAVEFORM 

Data sheets on pages 1-D2 through 1-D5 are reproduced by permission of Texas Instruments Incorporated, 



1-D2 



TMS 1 000/1 200 AND TMS 1 1 00/1 300 

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE 
(UNLESS OTHERWISE NOTED) 



PARAMETER 


TEST CONDITIONS 


MIN TYpt MAX 


UNIT 


l| Input current, K inputs 


V| =0V 


50 300 500 


mA 


High-level output voltage 
°" (see Note 1) 


outputs 


IO = -10mA 


-1 .1 1 -0.6* 


V 


R outputs 


IO = -2mA 


-0.75 -0.4 


'OL Low-level output current 


Vql = Vdd 


-100 


HA 


Average supply current from Vqq 
'DD(av) TMS 1000/1200 (see Note 2) 


All outputs open 


-6 -10 


mA 


Average supply current from Vdq 
DD(av) Tivisi 100/1300 (see Note 2) 


All outputs open 


-7 -11 


mA 


Average power dissipation 
'^^' TMS 1000/1200 (see Note 2 


All outputs open 


90 175 


mW 


Average power dissipation 
'^^* TMS1 100/1 300 (see Note 2) 


All outputs open 


105 193 


mW 


'osc Internal oscillator frequency 


^ext^SOkn, Cext=47pF 


250 300 350 


kHz 


Cj Small-signal input capacitance, K inputs 


V| =0, f = 1 kHz 


10 


PF 


Cj(0) Input capacitance, clock input 


V|=0, f = 100 kHz 


25 


pF 



< 

Q 
< 



^All typical values are at Vdq = — 15 V, T/\ = 25°C. 

JParts with Vqh °* ~^ ^ minimum, —1 .3 V typical, are available if requested. 

NOTES: 1. The algebraic convention where the most-positive (least-negative) limit is designated as maximum is used in this 

specification for logic voltage levels only. 
2. Values are given for the open-drain O and R output configurations. Pull-down resistors are optionally available on all 

outputs and increase Iqq (see Section 4.4). 



SCHEMATICS OF INPUTS AND OUTPUTS 



TYPICAL OF ALL K INPUTS 



^ 



Vss 



'n 



-OVdd 



TYPICAL OF ALL O AND R 
OPEN-DRAIN OUTPUTS 



n 



Vss 





1 



TYPICAL OF ALL O AND R 

OUTPUTS WITH OPTIONAL 

PULL-DOWN RESISTORS 




The outputs have nominally 60 J2 on-state impedance; however, upon request a 130-f2 buffer can be mask program- 
med (see note [J] section 4.3). 

The value of the pull-down resistors is mask alterable and provides the following nominal short-circuit output currents 
(outputs shorted to Vss): 

outputs: 100, 200, 300, 500, or 900 (lA 
R outputs: 100, 150, or 200 ^lA. 



1-D3 



TMS 1000/1200 AND TMS 1100/1300 

INTERNAL OR EXTERNAL CLOCK 

If the internal oscillator is used, the 0SC1 and 0SC2 ternninals are shorted together and tied to an external resistor to 
Vqd 3""^ 3 capacitor to Vss- If an external clock is desired, the clock source may be connected to 0SC1 and 0SC2 
shorted to Vsg. 



CONNECTION FOR INTERNAL OSCILLATOR 

1( -OVss 



TYPICAL BUFFER CHARACTERISTICS 

O OUTPUTS 
HIGH-LEVEL OUTPUT CURRENT 

v$ 
HIGH-LEVEL OUTPUT VOLTAGE 



I _io 



1 1 . 


1 — 
r 


— - 


~7 


n 


MAX 

■o(p« 


. 1 
flATED 


Ta 


•25C 


/ 






'/ 


L 


>k) 








/ 




/ 






1 


■^ 


^ 






*^ 


/ 




■ < 


■^ 








'•7 


« 






,/ 


A 










/ 


-/ 


M 


w 


A- 


"I 


MAX- 


RATF 


D 


/ 




/ 




/ 




L 


•Odv) 




/ 














A 


k 










.■astP 






'V 








OH A 











TYPICAL INTERNAL OSCILLATOR FREQUENCY 
EXTERNAL RESISTANCE 




20 40 60 80 100 120 140 160 180 200 
Rext ~ ExUrnal Rttiitlnca — V.U 



R OUTPUTS 
HIGH-LEVEL OUTPUT CURRENT 

vs 
HIGH-LEVEL OUTPUT VOLTAGE 



-1 -2 -3 -4 

Vqh - High-Lavti Output Voltag* - V 




-1 -2 -3' -4 

Vqh - Hi«h-Lav«l Output Voltcgs - V 



1-D4 



o 

m 

CO 

O 

< 

Q 

< 

® 



TMS 1070/1270 

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE 
(UNLESS OTHERWISE NOTED)* 

Voltage applied to any device terminal (see Note 1) —20 V 

Supply voltage, Vqd -20 V to 0.3 V 

Data input and output voltage with V^D appHed (see Note 2) -35 V to 0.3 V 

Clock input and IN IT input voltage -20 V to 0.3 V 

Average output current (see Note 3): outputs —2.5 mA 

R outputs -12mA 

Peak output current: outputs —5 mA 

R outputs -24 mA 

Continuous power dissipation: TMS 1070 NL 400 mW 

TMS 1270 NL 600 mW 

Operating free-air temperature range C to 70 C 

Storage temperature range • • —55 C to 150 C 

•Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress rating only and 
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" 
section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 

RECOMMENDED OPERATING CONDITIONS 



PARAMETER 


MIN 


MOM 


MAX 


UNIT 


Supply voltage, Vqq (see Note 4) 


-14 


-15 


-17.5 


V 


High-level Input voltage, ^\^ (see Note 5) 


K 


-6 




0.3 


V 


INIT or Clock 


-1.3 


-1 


0.3 


Low-level Input voltage, V|l (see Note 5) 


K (See Note 2) 


-35 




-a 


V 


INIT or Clock 


Vdd 


-15 


-8 


Clock cycle time, tc(0) 


2.5 


3 


10 


MS 
AXS 


Instruction cycle time, tj. 


15 




60 


Pulse width, clock high, tj^(0H) 


1 


MS 


Pulse width, clock low, t^{(p[_) 


1 


MS 


Sum of rise time and pulse width, clock high, tr + t 


M<pH) 


1.25 


MS 


Sum of fall time and pulse width, clock low, tf t tw(0L) 


1.25 


MS 


Oscillator frequency, fosc 


100 




400 


kHz 


Operating free-air temperature, Ta 







70 


"C 



ES: 1. Unless otherwise noted, all voltages are with respect to Vss. 

2. Vdd must be within the recommended operating conditions specified in 5.4. 

3. These average values apply for any 100-ms period. 

4. Ripple must not exceed 0.2 volts peak-to-peak in the operating frequency range. 

5. The algebraic convention where the most-positive (least-negative) limit is designated as maximum is used in this specification for 
logic voltage levels only. 

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE 
(UNLESS OTHERWISE NOTED) 



PARAMETER 


TEST CONDITIONS 


MIN 


TYP* 


MAX 


UNIT 


l| Input current, K inputs 


V| =0 V 


40 


100 


300 


mA 


High-level output voltage 
'^^ (see Note 1) 


outputs 


Iq = —1 mA 


-1 


-0.5 




V 


R outputs 


IO = -10mA 


-4.5 


-2.25 




Iql Low-level output current 


Vol = Vdd 


-100 


mA 


iDD(av) Average supply current from Vqd 


All outputs open 




-6 


-10 


mA 


P(/\\/) Average power dissipation 


All outputs open 




90 


175 


mW 


fosc Internal oscillator frequency 


Rext = 50 kfi. 


Cext = 47pF 


250 


300 


350 


kHz 


Cj Small-signal input capacitance, K inputs 


V| = V, 


f = 1 kHz 


10 


PF 


Cj(0) Input capacitance, clock input 


V| = V, 


f = 100 kHz 


25 


PF 



''aII typical values are at Vqd = — 15 V, T/^ = 25°C. 

NOTE 1: The algebraic convention where the most-positive (least-negative) limit is designated as maximum is used in this specification . 
for logic voltage levels only. 



1-D5 



Chapter 2 
THE MOSTEK 3870 
(AND FAIRCHILD F8) 



^ The F8 has had a profound impact on the microcomputer industry. When it first appeared, the F8 was discussed 

u as an off-beat product with a strange set of chips and a ridiculous instruction set. The chip set was strange 

u because logic was organized with the goal of minimizing chip counts; in contrast, microprocessors such as the 

< 8080A and 6800 were designed with logic distributed functionally on chips - one traditional CPU logic function 
03 per chip. The F8 instruction set is indeed strange, and in some cases quite limiting, but it reflects the simple 
^ chip design of the F8 CPU. 

oc 

o Many microprocessors are now going into consumer products. In this marketplace, the two-chip F8 system pro- 

co vided by a 3850 CPU and a 3851 PSU gained an early dominant position. Other microprocessors available when 

_ the F8 was introduced required seven or more chips to provide the same capabilities as the two-chip F8. The 

< economics of consumer product volumes rendered the inefficiencies of the F8 instruction set inconsequential; 
° as a result, in 1977 the F8 was the world's leading microprocessor in terms of CPU sales. 

© In recognition of the F8 success story, most microprocessor manufacturers have introduced one-chip and two- 

chip microcomputer systems. 

Since the F8 3850 CPU/3851 PSU configuration was the world's first two-chip 8-bit microcomputer system, the F8 was 
the easiest 8-bit microprocessor to convert into a one-chip microcomputer. Fairchild, the F8 prime source, and 
Mostek, the F8 second source, both designed one-chip microcomputers around the F8. Fairchild designed the 
3859, which was a simple combination of the 3850 CPU and 3851 PSU on a single chip. Mostek developed a 
more ambitious one-chip microcomputer, the 3870. Mostek developed the 3870 ahead of the Fairchild 3859; 
therefore, Fairchild dropped the 3859 and became a second source for the 3870. Thus, the original F8 second 
source, Mostek, is now the new prime source, while the original prime source, Fairchild, is now a second source. 

The majority of F8 customers have small configurations which convert readily to the 3870. This being the case, the 
3870 is the F8 product being actively marketed, while the old F8 chip set is now manufactured to meet the needs of 
existing customers and to represent a possible expansion for any customer whose application will no longer fit within 
the confines of the 3870. In this chapter, therefore, we begin by examining the 3870 in detail. Descriptions of the 
F8 CPU and its support devices follow. 

These are the F8 devices described: 



THE FAIRCHILD 
F8 DEVICE SET 



-The 3850 CPU. 

- The 3851 Programmable Storage Unit (PSU), which provides read-only memory plus 
various additional logic functions. 

-The 3852 Dynamic Memory Interface (DMI), which primarily provides interface logic for dynamic or static 
read-write memory. 

- The 3853 Static Memory Interface (SMI), which primarily provides interface logic for static read/write memo- 
ry. 

- The 3854 Direct Memory Access (DMA), which, in conjunction with the 3852 DMI, implements Direct Memo- 
ry Access logic. 

- The 3856 and 3857 16K Programmable Storage Units (PSU 16), which are variations of the 3851 PSU biit pro- 
vide more read-only memory. 

- The 3861 PIO, which provides the additional logic functions of the 3851 PSU but has no read-only memory. 

- The 3871 PIO, which is equivalent to the 3861 PIO but has logic characteristics identical to th9 3870. 
Some additional 3870 series products are planned for delivery in late 1978 and early 1979. 



2-1 



The 3872 is identical to the 3870, except that program memory is doubled from 2048 to 4096 bytes. The 4096 bytes of 
program memory are configured as 4032 bytes of read-only memory and 64 bytes of read/write memory. Thus, the 
3872 will have 1 28 bytes of read/write memory, of which 64 are in the scratchpad and an additional 64 are in external 
memory. 

The 3873, which will probably be available in early 1979, is equivalent to a 3870 with one serial I/O channel added. 

The 3876, which will probably be available in late 1 978, is equivalent to a 3870 with 64 bytes of additional read/write 
memory; that is to say, in addition to the 2048 bytes of program memory there will be 64 bytes of scratchpad memory 
and an additional 64 bytes of external read/write memory. This additional 64 bytes of external read/write memory will 
have a low power standby option, allowing you to maintain data in these 64 bytes while power has been removed from 
the rest of the device. 

Figure 2-1 illustrates logic associated with individual F8 devices, and the 3870 one-chip microcomputer. 

All devices of the F8 family require +5V and -1-1 2V power supplies. The 3870, however, uses a single -I-5V power sup- 
ply. 

Using a 500 ns clock, instruction cycle time is 2 /asec. Instruction execution times range from 1 to 6.5 instruction cy- 
cles, or 2 to 13 /xsec. 

N-channel isoplanar MOS technology is used for the F8. 

N-channel ion injection technology is used for the 3870. 



The 3870 Microcomputer 

3850 CPU 3851, 3856 or 3857 Program Storage 

Unit (PSU) 



I/O Port I/O Port 



interrupt Request 
I/O Port I/O Port 



I 



n n 



64-byte RAM 



ALU 
and 
CU 



r' 
r 

I 



Prog Timer 



ROM 



Mem Addr Log 



1 



Interrupt Request 



3853 Static 

Memory Interface 

(SMI) 



I 



Prog Timer 



RAM 

INTERFACE 

LOGIC 



I 



STATIC 
RAM 



I 



SYSTEM BUS 










RAM 


DYNAMIC 




INTERFACE 


or 


^ |» 


LOGIC 


STATIC 




DMA CONTROL 


RAM 









/ 



DMA , 
CONTROL 
LOGIC 



3852 Dynamic Memory Interface 
(DMI) 

A maximum of 65,536 bytes of memory may be present in an F8 microcomputer system. 



3854 Direct 

Memory Access 

(DMA) 



Figure 2-1. A Fairchild/Mostek F8 Microcomputer System 



2-2 



< 

@ 



The principal manufacturer for the F8 is: 



The second source is: 



FAIRCHILD SEMICONDUCTOR 

464 Ellis Street 

Mountain View, CA 94040 



Ij MOSTEK, INC. 

g P.O. Box 169 

^ Carrollton. TX 75006 

o The principal manufacturer for the 3870 is: 

~. MOSTEK, INC. 

{" P.O. Box 169 

< Carrollton, TX 76006 

y 

g Second sources are: 

< FAIRCHILD SEMICONDUCTOR 
2 464 Ellis Street 

2 Mountain View, CA 94040 

DC 

m MOTOROLA, INC. 

o Semiconductor Products Division 

S 3501 Ed Bluestein Blvd. 

g Austin, TX 78721 



THE 3870 ONE-CHIP MICROCOMPUTER 

Functions implemented on the 3870 microcomputer are illustrated in Figure 2-2. 

Some caution rnust be exercised when looking at Figure 2-2; functions shown as present should not always be 
considered equal to larger systems. For example, read/write memory and memory addressing are shown as completely 
present; however, only 64 bytes of read/write memory are provided, with no possibility of expansion. I/O ports and in- 
terface logic are shown as provided, but the 3870 itself has only four I/O ports. Programmable timers and interrupt han- 
dling logic are shown as present, yet only one interrupt request line is available and only one programmable timer is 
present ~ again with no possibility for expansion. 

There is, in fact, a sharp contrast between the expansion philosophy of the 3870 as compared to 
the Intel 8048. The 3870 is simply not expandable; if your application overflows the 3870 you 
can keep your programs, but you must revert to the F8 chip set. In contrast, the 8048 is ex- 
pandable, albeit in a somewhat clumsy fashion. Thus, when an application overflows a 3870, you can keep your pro- 
grams but you must throw away your 3870 chips. When an application overflows the 8048, you can keep the 8048 
already in hand, using expansion capabilities to support new functions. 



3870 
EXPANSION 



2-3 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



1 


' 




♦ 


Interrupt Priority 




Bus Interface 


Arbitration 




Logic 


\ 




J 


I 


\ 


1 




' 


r > 



Accumulator 
Register(s) 



Data Counteris) 



Stack Pointer 



Program Counter 



Direct Memory 

Access Control 

Logic 



System Bus 



I 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 
Interface Logic 



I/O Ports 
Interface Logic 



Read Only 
Memory 



I/O Ports 



RAM Addressing 

and 
Interface Logic 



Read /Write 
Memory 



Figure 2-2. Logic of the Fairchild/Mostei< 3870 Microcomputer 



2-4 



3870/F8 PROGRAMMABLE REGISTERS 

These are the programmable registers of the 3870 and F8: 



o 

CO 
V) 

o 

< 

Q 
< 



8 bits 



1 1 bits in the 3870,16 bits in the F8 



11 bits in the 3870,16 bits in the F8l 



T 6 bits 



5 bits 



Accumulator (A) 
1 1 bits in the 3870, |1 6 bits in the F8 Program Counter (PCO) 

Program Counter buffer, or Stack register (PCI) 
Data Counter (DCO) 



1 1 bits in the 3870,16 bits in the F8|Data Counter buffer (DC1) 

Scratchpad Address register (ISAR) 



Status register (W) 



W register 



DCO register 



PCI (Stack) register • 



DCO or PCO registers • 



H is equivalent to a Data 
Counter buffer register 
K is equivalent to a Stack 
register buffer 
Q is equivalent to a Data 
Counter or Program Counter 
buffer register 



*\ 



J 
HU 
HL 
KU 
KL 
QU 
QL 



Scratchpad 


Scratchpad By 
Decimal Octal 



1 1 

2 2 


te Address 
Hexadecimal 









1 




2 



9 


11 


9 


10 


12 


A 


11 


13 


B 


12 


14 


C 


13 


15 


D 


14 


16 


E 


15 


17 


F 


16 


20 


10 


58 


72 


3A 


59 


73 


38 


60 


74 


3C 


61 


75 


3D 


62 


76 


3E 


63 


77 


3F 



There is one 8-bit Accumulator, which may be likened to the Primary Accumulator (AO) of 
our hypothetical microcomputer. Wherever there is a choice, this Accumulator is the usual 
source or destination for data operations associated with any instruction's execution. 



3870/F8 
ACCUMULATOR 



2-5 



The 64-byte scratchpad may be viewed either as a small read-write memory, or as 64 8- 3870/F8 

bit secondary Accumulators. The first 11 scratchpad bytes may be accessed directly, as SCRATCHPAD 

though they were secondary Accumulators. Remaining RAM bytes can only be accessed using 

a form of implied memory addressing, where a 6-bit register (identified as the ISAR register) must provide the address 

of the byte being accessed. The ISAR register is in every way identical to a 6-bit Data Counter. . 

Data Counter DCO is an implied addressing register, as described for our hypothetical 3870/F8 DATA 
microcomputer. COUNTERS 



Data Counter DC1 is simply a buffer for the contents of Data Counter DCO. Implied address- 
ing via Data Counter DC1 is not allowed. The only instruction that accesses Data Counter DC1 is an instruction which 
will exchange the contents of Data Counters DCO and DC1. 

Program Counter PCO serves the same function in a 3870 or F8 system as it does in 
our hypothetical microcomputer. 



3870/F8 PROGRAM 
COUNTER 



The Stack register (PCI) is, in reality, a buffer for Program Counter PCO; the Stack register 3870/F8 STACK 

does not address an area in read-write memory, and there are no Push or Pop instructions as REGISTER 
described in Volume I, Chapter 6. Interrupts and Jump-to-Subroutine instructions save the ^— — ^^— ^^— 
contents of Program Counter PCO in Stack register PCI, before loading a new address into Program Counter PCO: 



Old Address from PCO 
is moved to PCI 



New Address 




Old Address In 
PCI is lost 



Program Counter PCO 



Stack register PCI 



The classical Stack can be implemented in a 3870 or F8 system, but a short program needs to be written to do this. 

Read-only memory is always addressed using implied addressing, with auto-increment, via MEMORY 
Data Counter DCO. No other memory addressing modes are provided. ADDRESSING 



There are a number of instructions which load immediate data into Data Counter DCO; data may also be transferred 
between Data Counter DCO and scratchpad bytes, and it is possible to add the contents of the Accumulator to Data 
Counter DCO. 

In order to understand scratchpad addressing, one has to view it as representing neither 64 SCRATCHPAD 
Accumulators nor 64 bytes of read-write memory, but rather as something between the MEMORY 
two. ADDRESSING 



3870 MEMORY ADDRESSING MODES 

The 3870 microcomputer has two separate and distinct memories: 

1) There is the 64-byte scratchpad, which is the only read/write memory available. 

2) There are 2048 bytes of read-only memory, which must contain all programs, but may also contain constant data. 

We will refer to addressing of the 64-byte scratchpad as "scratchpad addressing", while "memory addressing" 
refers to the 2048 read-only memory bytes. 

It is important to note that the scratchpad and the read-only memory have separate and distinct address spaces. 
Scratchpad locations have addresses in the range through 63-| q- while read-only memory locations have addresses in 
the range through 2047io- Thus, addresses through 63io can access both a scratchpad byte and a read-only 
memory location; however, this will never cause confusion since separate and distinct instructions access scratchpad 
as against read-only memory. Since no one instruction can access both scratchpad and read-only memory, there is no 
possibility for confusion. 



2-6 



Instructions which access scratchpad memory use the four low-order object code bits to identify Scratchpad Address- 
ing mode, as follows: 

■Bit No. 
Scratchpad access instruction object code 

0000' 



7 6 

1 


5 4 


3 2 


- 

1 1 



< 

o3 
111 

Z 
oc 
o 
m 

V) 

O 

< 
o 

< 



Ml/ 



101 

1100 

1101 



1110 



Directly address one of Scratchpad bytes through 1 1 

S - Implied addressing via ISAR 
I - Implied addressing via ISAR 
with auto-increment of three 
low-order ISAR bits. 
D - Implied addressing via ISAR 
with auto-decrement of three 
low-order ISAR bits. 



There are a number of register-register instructions that operate on the Accumulator and on one of the first 12 
scratchpad bytes, using object codes as follows: 

— Bit No. 



7 6 5 4 3 2 1 



0000 



1011 



One scratchpad byte from bytes through 1 1 is specified 



An instruction that accesses the Accumulator and one of the 
scratchpad bytes is specified 



This type of object code treats the first 1 2 scratchpad bytes as secondary Accumulators. 

Any scratchpad byte may be addressed via the ISAR register using implied addressing; that 
is to say, the 6-bit number in the ISAR (which can have a value in the range through 63) iden- 
tifies the one scratchpad byte which will be accessed by the next scratchpad referencing instruc- 
tion. 

The ISAR register provides implied addressing, and implied addressing with auto-increment or 
auto-decrement; however, only the low-order three bits of the ISAR register are involved in the 
auto-increment or auto-decrement operation: 



DIRECT 

SCRATCHPAD 

ADDRESSING 



IMPLIED 

SCRATCHPAD 

ADDRESSING 




These three bits may be incremented or decremented by an im- 
plied addressing scratchpad memory reference with auto-in- 
crement/decrement. 

Specifies an instruction that accesses the Accumulator and one 
of the scratchpad bytes 



F8 scratchpad bytes may therefore be accessed as contiguous 8-byte buffers, with wraparound auto-increment or 
auto-decrement within each 8-byte buffer. 



2-7 



r SCRATCHPAD 
ADDRESSING 



Instructions shown in Table 2-2 use the symbol r in the operand to represent scratchpad ad- 
dressing. This is what the symbol r represents: 

- If r is a number between and 11, one of scratchpad bytes through 1 1 is addressed directly. 

- If r is S, implied addressing via ISAR is specified. 

- If r is I, implied addressing via ISAR, with auto-increment of the low-order three implied address bits, is specified. 

- If r is D, implied addressing via ISAR, with auto-decrement of the low-order three address bits, is specified. 

Given the various ways in which scratchpad memory can be addressed, this is the most effective way of configuring 
scratchpad: 




















89 ABCDEF10 














718 














F20 












2728 












2F30 












37 


38 












3F 



































































































































Secondary 
Accumulators 



H K Q 

fli 



Buffer 1 



Buffer 2 



Buffer 3 



Buffer 4 



Buffer 5 



Buffer 6 



Data Counter (DCO) or Program Counter (PCO) buffer 

Stack (PCD buffer 

Data Counter (DCO) buffer 

Status register (J) buffer 



Treat scratchpad bytes through 8 as nine secondary Accumulators; access these bytes using direct scratchpad ad- 
dressing. 

Wherever possible, use scratchpad bytes 9 through F only as buffers for their associated registers; when accessing 
these bytes, use the specific instructions which transfer data between these scratchpad bytes and their associated 
registers. 

Although you can address scratchpad bytes 9, A, and B by using direct addressing, do not do so when these 
scratchpad bytes are being used as buffers for the Status registers (W) and Data Counter (DCO). 

While indirect addressing via ISAR can access any scratchpad byte, you should avoid addressing scratchpad bytes 
through F in this fashion. Wherever possible, use ISAR only to address scratch bytes IO15 through 3Fi6; divide this 
area into 8-byte buffers as illustrated. Because I addressing auto-increments only the three low-order ISAR bits, this 
form of scratchpad byte addressing will wrap around within one 8-byte buffer, as follows: 



ISAR 



X 


X 


X 











X 


X 


X 










X 


X 


X 





1 





X 


X 


X 





1 




X 


X 


X 


1 








X 


X 


X 


1 







X 


X 


X 


1 


1 





X 


X 


X 


1 


1 




X 


X 


X 











X 


X 


X 











Similarly, D implied addressing via ISAR will wrap around within eight scratchpad byte divisions, as follows: 



ISAR 



X 


X 


X 











X 


X 


X 


1 


1 




X 


X 


X 


1 


1 





X 


X 


X 


1 







X 


X 


X 


1 








X 


X 


X 





1 




X 


X 


X 





1 





X 


X 


X 










X 


X 


X 











X 


X 


X 


1 


1 





2-8 



o 
ea 

Ui 

O 

< 

Q 

< 

@ 



3870/F8 STATUS FLAGS 

The Status register, also called the W register, holds five status flags, as follows: 

4 3 2 10 Bit No. 

Status register (W) 



Sign 

Carry 

Zero 

Overflow 

Interrupt Control Bit 



cozes 



The 0, Z, C and S status flags are identical to the flags with equivalent synnbols, as described in Volume I, Chapter 6 for 
our hypothetical microcomputer. 

The Interrupt Control bit is treated as a fifth status; this status will not be modified by arithmetic or logic operations, 
but it will be transferred, as a unit with the other four status flags, to or from Scratchpad byte 0. 

3870 PINS AND SIGNALS 

3870 pins and signals are illustrated in Figure 2-3. 




Pin Name 

PO-0 - PO-7 
P1-0-P1-7 
P4-0 - P4-7 
P5-0 - P 5-7 
STROBE 
EXT IN T 
RESET 
TEST 

XTL1, XTL2 
Vcc- GND 



Description 

I/O Port 
I/O Port 1 
I/O Port 4 
I/O Port 5 
Ready Strobe 
External Interrupt 
External Reset 
Test Line 
Time/Clock 
Power Supply Lines 



Type 

Bidirectional 

Bidirectional 

Bidirectional 

Bidirectional 

Output 

Input 

Input 

Input 

Input 

Input 



Figure 2-3. 3870 Microcomputer Signals and Pin Assignments 



2-9 



32 of the 40 signals implement four 8-bit I/O ports, which are addressed as I/O Ports 0, 1, 4 and 5. 

Pins POO through P07 implement i/0 Port 0. 

Pins P10 through PI 7 implement I/O Port 1. 

Pins P40 through P47 implement I/O Port 4. 

Pins P50 through P57 implement I/O Port 5. 

I/O port characteristics are described following signal definitions. 

STROBE is a handshaking control signal associated with I/O Port 4. Whenever data is output to I/O Port 4, STROBE 
is pulsed low for approximately three clock periods. 

External interrupt requests are input via EXT INT. 



3870 
RESET 



RESET is a master reset input. When it is grounded, the following events occur: 

1) Program Counter contents (PCO) are pushed onto the Stack register (PCI). 

2) The ICB bit of the Status register is reset to 0; this disables all interrupts. 

3) I/O Port 4 and 5 pins all output +5V. Reset does not affect I/O Port and 1 pins. 

4) Other internal registers are not affected. 

The TEST input is used to test hardware. Normally the TEST pin is connected to ground, or it is left unconnected. 
When a voltage between 2V and 2.6V is connected to TEST, I/O Ports 4 and 5 become output and input connections to 
the internal Data Bus, as follows: 



<t 



Data Bus 



I/O Port 5 is a wire-OR input to the internal Data Bus; it is 
logically false. (Port pin 1 = Data Bus 0) 



I/O Port 4 is the internal Data Bus output; it is logically true. 
(Port pin 1 = Data Bus 1) 



When a voltage level between -I-6V and +7V is applied to the TEST pin, I/O Ports 4 and 5 are connected to the internal 
Data Bus as illustrated above; but, in addition, internal program memory is disconnected from the Data, Bus. This allows 
instruction codes to be entered via I/O Port 5. 

The TEST pin should be used for test purposes only. Do not use TEST during normal 3870 operations. You can- 
not, for example, use TEST as a means of transferring data between the Data Bus and external logic via I/O Ports 4 and 
5. Also, you cannot use TEST to supercede internal program memory with an external program memory. This is 
because timing associated with the test conditions differs markedly from normal instruction execution timing. 

XTL1 and XTL2 are clock signal inputs. These two clock signal inputs can be used in one of 
four ways. 



3870 CLOCK 
LOGIC 



If XTL1 and XTL2 are both grounded, then an internal oscillator within the 3870 generates the clock signal. In- 
ternal oscillator frequencies ranging between 1.7MHz and 4MHz are allowed. 

An external crystal may be connected across XTL1 and XTL2; in this case the external crystal determines clock fre- 
quency. Any frequency in the range 1 MHz to 4 MHz is allowed. There are internal 20 pF capacitors between XTL1 and 
ground and XTL2 and ground; therefore, external capacitors are not required. This may be illustrated as follows: 



XU1 



XTL2 



T 



1 MHz to 4 MHz 



2-10 



o 
ca 
w 
O 

< 
a 

< 

@ 



If an external clock signal is used, then it should be applied to pin XTL2, and pin XTL1 should be left open. 

The internal clock signal generated will have a frequency that is half of the external clock signal frequency. For exam- 
ple, in order to generate a 1 MHz internal clock signal, a 2 MHz external clock signal nriust be applied to pin XTL2. 

It is also possible to generate the internal 3870 clock signal using resistor capacitor (RC) or inductor capacitor 
(LC) circuits. The RC mode may be illustrated as follows: 



XTL2 



XTL1 



T 



R 



? 



vcc 



(Capacitor C is optional) 



R = 4Kft Minimum 

Capacitance = 20.5 pF + 2.5 pF + C 

Minimum frequency = 1/(1.1 RC + 65 ns) 

Maximum frequency = 1/(RC + 15 ns) 

The external capacitor C is optional, since there is a 20.5 pF internal capacitor. 
The LC mode may be illustrated as follows: 



XTL1 



XTL2 




(Capacitor C is optional) 



Inductor L = 0.1 mH (minimum) 
Inductor quality = (Q)=40 
If the external capacitor (C) is present, it must be 30 pF or less. 
Capacitance = 10 pF ± 1.3 pF + C 
Frequency = 1/(2 tt ^Alc) 

3870 INSTRUCTION TIMING AND EXECUTION 

All 3870 instructions execute as a sequence of "long" and "short" machine cycles. A long machine cycle lasts 
six clock periods. A short machine cycle lasts four clock periods. For each 3870 instruction. Table 2-2 identifies the 
sequence of long and short machine cycles via which the instruction executes. By referring to this table, you can com- 
pute instruction execution times as a function of clock frequency. 

Note that Table 2-2 refers to ROMC states. ROMC states have no meaning when you are using a 3870; however, they 
constitute five signals output by the 3850 CPU in an F8 configuration, as described later in this chapter. Since Table 
2:2 applies to both the 3870 and the F8, ROMC states are identified. 

3870 I/O PORTS 

The 3870 has four 8-bit I/O ports, which we defined when describing 3870 pins and signals. I/O ports are ad- 
dressed via port numbers 0, 1,4, and 5. I/O port addresses 6 and 7 are also reserved by the 3870; I/O Port 6 is 
used to output control codes and to input interrupt status. I/O Port 7 is used to access interval timer logic. 

0, 1,4, 5, 6, and 7 are the only I/O port addresses which have any meaning within a 3870. Output instructions that ad- 
dress any other I/O port act as "no operation" instructions. Input instructions that address any other port will clear the 
Accumulator. Nevertheless, the 3870 instruction set, as defined in Table 2-1, includes both long-form and short-form 
I/O instructions, allowing any I/O port to be accessed with addresses in the range through 255. This permits the 3870 
instruction set to be completely compatible with the full F8 instruction set - a necessity if 3870 programs are to be 
transportable to larger F8 configurations. 



2-11 



Every one of the 3870 I/O port pins is truly bidirectional. Logic associated with each pin may be illustrated as 
follows: 




The pin logic illustrated above is present in the 3870 microcomputer and the 3871 PIO only; other devices have 
the F8 I/O pin characteristics. 

If you do not understand digital logic, then you will not understand the illustration above, but that is not particularly im- 
portant. The above illustration explains exactly how bidirectional I/O port pin logic works. Fronn a progrannnner's point 
of view, this simply translates into the fact that you can ffeely input and output data without worrying about prior I/O 
port contents. However, all I/O port pins have inverted logic. This means that when you write 1 to an I/O port pin a 
voltage will be generated, while a -I-5V voltage will be generated if you output to the pin. Conversely, external logic 
will cause your program to input 1 if it grounds a pin, while it will cause your program to input if it applies -I-5V to the 
pin. 

The output buffer portion of I/O port pin logic determines the pin characteristics. Standard TTL logic is provided 
by the standard output buffer, which may be illustrated as follows: 

Vcc 



J 



6Kn (typical) 



^:l 



2-12 



o 

m 

CO 

O 

< 
a 

f* 

@ 



You can buy 3870 devices with different output buffers at I/O Ports 4 and 5, but not at I/O Ports and 1. I/O Ports 
and 1 pins can only have the standard output buffer illustrated above. There are two optional output buffer designs 
avaiiabie for pins of I/O Ports 4 and 5. A direct drive output is similar to the standard output, but it sources more cur- 
rent. Logic is illustrated as follov\/s: 



IKH (typical) 




The other option is an open drain output, which may be illustrated as follows: 



a 



The open drain output allows you to tie pins together; you can then wire-AND two or more pins when data is output. 
Consider the following configurations: 



P43 3 



P44 3 



P45 3 



If all outputs are high, then the wire-AND will be high; however, if any one of the three outputs goes low, then the wire- 
AND resulting from all three outputs will also go low. 

3870 INTERRUPT LOGIC 

External logic can input an interrupt request to the 3870 via the EXT INT signal. 

Interrupt requests may also be generated internally by timer/counter logic. 

There are two levels of interrupt enable/disable logic within the 3870. There is a Control 
register (described later in this chapter) which has bits and 1 set aside to selectively ena- 
ble or disable external interrupts and timer/counter interrupts, respectively. If one or both of 
these interrupts are enabled, then any interrupt request is still subject to master ena- 



3870 

INTERRUPT 

DISABLE 



2-13 



ble/disable logic, which is specified by the Interrupt Control bit of the Status register (bit 4 of the W register). 
This may be illustrated as follows: 



4 3 2 10 



Latch 



*. To CPU 

- Bit No. 

— Status register (W) 



For all bits: 
1 = enable 
= disable 



Bit No. 
Control register 



n 



Latch 



-I I External Interrupt 

Timer/Counter Interrupt 



A timer/counter interrupt request is latched. If timer/counter interrupt logic has been disabled via Control register 
bit 1, then an interrupt request will be held until timer/counter interrupts are subsequently enabled; the interrupt re- 
quest will then occur. 

External interrupt requests are not latched. An external interrupt request will only occur if the EXT INT signal makes 
an active transition while external interrupts have been enabled by Control register bit 0. 

Any intei-rupt request that reaches Status register logic will be latched. Thus, if Status register bit 4 is when 
either an external interrupt request or a, timer/counter interrupt request occurs, then the interrupt request will be held 
pending until Status register bit 4 is subsequently set to 1. 

A reset or power-on operation disables all interrupts; the Status and Control registers are cleared. 

Timer/counter interrupt requests have priority over external interrupt requests. Thus, if a timer/counter interrupt 
request and external interrupt request occur simultaneously and both are enabled, then the timer/counter interrupt re- 
quest will be acknowledged. 

When any interrupt request is acknowledged, further interrupts are disabled via the Status register; however, in- 
terrupt enable/disable logic associated with the Control register is not affected. Thus, an external interrupt request will 
be held pending for the duration of a timer/counter interrupt s^lvice routine's execution. However, the external inter- 
rupt request will be removed if, at any time while it is held pending, external interruptsarespecifically disabled via bit 
of the Control register. 

If a timer/counter interrupt request is generated while an external interrupt service routine is being executed, then 
Status register interrupt disable logic will prevent the timer/counter interrupt request from interrupting the external in- 
terrupt service routine. However, the timer/counter interrupt request will be held pending until interrupts are subse- 
quently enabled at the Status register. If for any reason timer/counter interrupts have been specifically disabled via 
Control register bit 1 , then any subsequent timer/counter interrupt request will be delayed until timer/counter interrupt 
logic is specifically enabled via bit 1 of the Control register. 

When an interrupt request is acknowledged, theProgram Counter (PCO) contents are saved on the Stack register (PCI). 
For a Timer interrupt request, a new value, 020i6' 'S loaded into the Program Counter: 



02016 




PCO 



PCI 



2-14 



z 
oe 
o 
a 
m 
o 

S 
< 
a 

< 

@ 



When an external interrupt request is acknowledged. Program Counter (PCO) contents are saved in the Stack register 
(PCI), then the new value OAOig is loaded into the Program Counter (PCO). Thus, interrupt service routines for timer 
and external interrupts must originate at memory locations 020i6 ^i^d OAO15, respectively. 

Since a reset or power-on clears the Program Counter, the beginning of program memory must be allocated thus: 



Program 
Memory 



000 



020 



OAO 



Initialization begins here 

Timer interrupt service routine 
begins here 



Extemal interrupt service routine 
begins here 



TIMER/COUNTER LOGIC 

3870 timer/counter logic represents a significant enhancement over prior F8 logic. 

3870 timer/event counter logic consists of an 8-bit binary Counter register together with a Buffer register and 
associated logic. The two registers are accessed as I/O Port 7. Data output to I/O Port 7 is written into the Counter 
register and the Buffer register. Data input from Port 7 is read from the Counter register only. This may be illustrated 
as follows: 



Out to 
I/O Port 7 




Buffer Register 



iz 



Counter Register 



=> 



In from I/O Port 7 



Timer/Counter 
Logic 



The scheme illustrated above allows timer/counter logic to operate in a "free running" mode. Whenever the contents 
of the Counter register decrement to 0, the new Counter register contents are taken from the Buffer register, and a 
timer interrupt request occurs. This may be illustrated as follows: 

Counter Buffer 

Register Register 
Contents Contents 



02 
01 



XX 
XX 



00 

XX 
XX- 1 

xx-2 
etc. 



Timer interrupt request 



XX 
XX 
XX 
XX 

etc. 



You can read Counter register contents at any time, even while the timer/counter is operating, by inputting from I/O 
Port 7; Counter register contents will be input. 

Timer/counter logic can be operated in Interval Timer mode, in Pulse Width Measurement mode, or in Event 
Counter mode. The contents of a Control register (which is accessed as I/O Port 6) determine the mode in which 
timer/counter logic will operate. We will describe the Control register after discussing timer/counter operating 
modes. 



2-15 



In Interval Timer mode, timer/counter logic is used to compute time intervals. In order to 3870 
corhpute a time interval, the timer/counter register contents are decremented at fixed INTERVAL 
"decrerherit" intervals. The decrement interval is equal to a number of clock periods, as TIMER MODE 

specified by the control code. The decrement interval may range between a low of two clock ^— ^— — — 
periods and a high of 400 clock periods. If, for example, a 500 nanosecond clock is employed and the decrement inter- 
val is 1 00 clock periods, then the Counter register contents will be decremented once every 50 microseconds. If the in- 
itial value output to I/O Port 7 is 200io (C8-16). then in Interval Timer mode, timer/counter logic will time out once ev- 
ery 10 milliseconds. 

Time interval = 0,5 x 100 x 200 microseconds 

The time delays which can be generated using timer/counter logic in Interval Timer mode are given by the following 
equation: 

Time interval = Reset value x Decrement time interval 

The reset value is the value written oiJt to I/O Port 7; it may have any value in the range through 255. is in fact 
eqiiivalent to a count of 256, since the decrement ends with a Timer interrupt request when Counter register contents 
decrement from 1 to 0. 

In Interval Timer mode, timer/counter logic operates as follows: 

1) An initial value must be output to I/O Port 7. This becomes the reset value. 

2) Using an appropriate control code, you select Interval Timer mode and options. The control code also starts and 
stops timer/counter logic in Interval Timer mode. 

3) Once started by an appropriate control code, the Counter register continuously decrements, reloads, and redecre- 
ments. 

4) In order to stop the timer/counter when operating in Interval Timer mode, you must output an appropriate control 
code. 

Each time the Counter register decrements to Oi a timer interrupt request is generated. If timer interrupt requests are 
enabled, then the interrupt request will be acknowlebged; if timer interrupt requests are disabled, the interrupt request 
will be latched and will be held pending until timer mterrupt requests are subsequently enabled. 

If interrupts are enabled when timer/counter logic times out in Interval Timer mode, there will be a small time delay 
before the interrupt is acknowledged; no interrupt cah be acknowledged until the conclusion of the currently executing 
instruction, plus the next instruction if it is privileged. (Privileged instructions are instructions which cannot be inter- 
rupted; they are identified in Table 2-1.) In the worst case, it is possible for 49 clock periods to elapse between the 
timer/counter timing out and a timer interi^upt being acknowledged; on the average, between 24 and 30 clock periods 
will separate these two events. If long delays between a time-out and interrupt acknowledge are not acceptable, then 
you must avoid executing privileged instructions while timer/counter logic is operating in Interval Timer mode. 

In Pulse Width Measurerrient mode, timer/cciunter logic measures the duration of a pulse 
which is input on the EXT INT pin. Under prograin control, you can measure a low pulse: 



3870 

PULSE WIDTH 

MEASUREMENT 

MODE 



EXT INT 



START STOP 

TIMER TIMER 



or you can measure a high pulse: 

J 1 



EXT INT 



-♦ 



START STOP 

TIMER TIMER 

Stop and start logic represents the only difference between Pulse Width Measurement mode and Interval Timer mode. 
As illustrated above, it is EXT INT signal transitions that start and stop timer/counter logic in Pulse Width mode. In ad- 
dition, you can use control codes to stop timer/counter logic in Pulse Width mode. 



2-16 



o 

CO 
CO 

o 

< 
a 
< 



An external interrupt request occurs at the trailing edge of the EXT INT pulse. This external interrupt request will be 
acknowledged only if external interrupts have been enabled. If external interrupts are disabled, no interrupt request oc- 
curs. That is to say, if external interrupts are enabled at some point after the end of a pulse, no interrupt request will be 
pending. 

Within the pulse itself, timer/counter decrement logic works exactly as described for Interval Timer mode. The Counter 
register contents are decremented once each decrement interval; the decrement interval is defined in Interval Timer 
mode. If the timer/counter does not time-out within the pulse width, then on the trailing edge of the pulse the 
timer/counter is stopped. By inputting from I/O Port 7, you read the contents of the Counter register at the trailing edge 
of the pulse; the difference between this input value and the initial reset value can be used to compute the pulse dura- 
tion, as follows: 

Pulse duration = (Initial reset value - final Counter register contents) x decrement time interval 

For example, suppose the initial reset value output to I/O Port 7 is IOOiq (64-|6). while the final value input from I/O 
Port 7 is 16io OO-is): if the control code has set timer/counter logic to decrement once every 100 microseconds, then 
the pulse width must be 8.4 milliseconds: 

Pulse width = (100 - 16) X 100 microseconds 

If the Counter register does time-out within a pulse, then a timer interrupt request occurs, the Buffer register contents 
are loaded into the Counter register, and decrementing restarts. Program logic must respond to the timer interrupt re- 
quest by incrementing a scratchpad counter; the total pulse time is computed as follows: 

Pulse duration = (Initial reset value - final Counter register contents) 
X decrement time interval 
X initial reset value x decrement time interval 
X scratchpad counter contents 

Suppose, for example, that the initial reset value output to I/O Port 7 is 200i q (CBi q), and that the Counter register has 
timed out three times within the pulse width; the scratchpad counter will now contain 3. If the final value input from 
I/O Port 7 is 53-|o (35 ig) and the decrement time interval specified by the control code is 50 microseconds, then the 
total pulse timer interval is 37.35 milliseconds: 

Pulse interval = (200 - 53) x 50 + 200 x 3 x 50 
= 37,350 microseconds 



3870 
EVENT 
COUNTER 
MODE 



In Event Counter mode, the Counter register contents are decremented on "active" transi- 
tions of the EXT INT input. An "active" transition on this signal may be high-to-low or low-to- 
high, as selected by the control code. 

In the Event Counter mode, when the Counter register decrements to a timer interrupt request is 
latched, as described for the Interval Timer mode. Thus, if the timer interrupts are enabled, the in- 
terrupt request will be acknowledged following execution of the next non-privileged instruction; if timer interrupts are 
disabled, the interrupt request will be held until interrupt requests are re-enabled. Active transitions on the EXT INT 
signal, while decrementing the Counter register contents, also cause interrupt requests to occur if external interrupts 
are enabled. Since it would be pointless to have an external interrupt request occur on every decrement, external inter- 
rupts are normally disabled in Event Counter mode. 

THE 3870 CONTROL CODE 

Operation of 3870 timer/counter logic and interrupt logic is controlled via an 8-bit control code which must be 
output to I/O Port 6. I/O Port 6 is a write-only location. When you input from I/O Port 6, you do not read the con- 
tents of the Control register; rather; the level on the EXT INT pin appears at bit 7 of the Accumulator. This may 
be illustrated as follows: 



EXT INT 




Accumulator 



2-17 



If you need to read the control code after writing it out, then you must l<eep a copy of it in one of the scratchpad bytes. 
Control code bits are assigned as follows: 




■K 

-i: 
■I? 



External interrupts disabled 
External interrupts enabled 

Timer/counter interrupts disabled 
Timer/counter interrupts enabled 

EXT INT is active low ^ ' 

EXT INT is active high t * 

Stop timer/counter in any mode 

Start timer/counter in Interval Timer or Event Counter modes 

Interval Timer mode if bits 7, 6, 5 are not 000 

Event Counter mode if bits 7, 6, 5 are 000 

Pulse Width Measurement mode. (Do not use 000 for bits 7, 6, 5 in 

this mode) 

2 pre-scalar 1 

5 pre-scalar \ 

20 pre-scalar I 



■Bit No. 



nzn: 



1 

1 

1 1 

1 
1 1 
1 10 



Event Counter mode 

-r 2 pre-scalar\ 

■T 5 pre-scalar I 

•T 10 pre-scalar I Pre-scalar x Clock period gives decrement time in- 

-j- 20 pre-scalar > terval in interval Timer or Pulse Width Measure- 

•f 40 pre-scalar I ment modes 

-r 100 pre-scalar I 

-r 200 pre-scalar y 

Bits and 1 are used to selectively enable or disable interrupt requests. External interrupt requests occur via 
active transitions on the EXT INT input signal; timer/counter interrupt requests are generated within 
timer/counter logic. You have the option of enabling both external interrupts and timer/counter interrupts; you 
can enable one but not the other, or you can disable both. 

Recall that timer/counter interrupt requests are latched; if timer/counter interrupt logic is disabled (control code bit 1 is 
0) when the timer/counter interrupt request occurs, then the interrupt request will remain pending until timer/counter 
interrupts are subsequently enabled (control code bit 1 is 1), or until the 3870 is reset A reset removes the latched in- 
terrupt request. External interrupts are not latched; an external interrupt request will be generated only as EXT INT 
makes an active transition while control code bit is 1. A timer/counter interrupt request occurs whenever the 
timer/counter register decrements from 1 to 0, as previously described. 

An external interrupt request occurs whenever an "active" transition is sensed on the EXT INT pin. Bit 2 of the 
control code determines what an "active" transition of EXT INT will consist of. If bit 2 is 0, then a low level on 
EXT INT is considered active, and high-to-low transition causes an external interrupt request. If bit 2 of the control code 
is 1, then a high level on EXT INT is considered active and a low-to-high signal transition will cause an external inter- 
rupt request. 

Control code bit 3 is the start/stop bit. This bit must be used to start and stop timer/counter logic when operating in In- 
terval Timer mode or Event Counter mode. When timer/counter logic is operating in Pulse Width Measurement mode, 
then leading and trailing edges of an active EXT INT pulse start and stop timer/counter logic; within a pulse, however, 
the start/stop bit of the Control code can be used to stop and then restart timer/counter logic. 



2-18 



z 
cc 
o 
m 
w 
O 

< 
a 

< 

© 



In Interval Tinner mode or Pulse Width mode, bits 5, 6 and 7 select the decrement time interval. The important point to 
note is that bits 5, 6 and 7 are cumulative. Thus, you have seven pre-scalar options shown with the control code. 

In Interval Timer mode or in Pulse Width mode, the Counter register contents are decremented once every decrement 
time interval. A decrement time interval is equal to the internal clock pulse time multiplied by the pre-scalar. Assuming 
a 500 nanosecond internal clock pulse width, 010 in Control register bits 7, 6 and 5 would generate a decrement time 
interval of 2.5 microseconds. A decrement time interval of 50 microseconds would be generated by 110 in Control 
register bits 7, 6 and 5. 

THE 3870/F8 INSTRUCTION SET 

Table 2-1 summarizes the 3870/F8 instruction set; instructions are grouped into categories that conform with 
our hypothetical microcomputer instruction set, as described in Volume I, Chapter 7. 

With reference to Table 2-1 , refer to the addressing modes description for an explanation of "r", which occurs in the 
operand column to represent some of the scratchpad addressing options. 

One of the more confusing aspects of 3870/F8 programming is understanding the ways in which data may be moved 
between different registers; this information is therefore summarized in Figure 2-4. 

The following symbols are used in Table 2-1: 

A The Accumulator 

addr A 16-bit memory address 

C Carry status 

data3 A 3-bit binary data unit 

data4 A 4-bit binary data unit 

data5 A 5-bit binary data unit 

DCO Data Counter register 

DC1 Data Counter buffer 

dpchr Scratchpad Data or Program Counter Half Registers. These are KU (Register 12), KL (Register 13), QU 

(Register 14) and QL (Register 15). 

disp An 8-bit signed binary address displacement 

FMASK A 4-bit mask composed of a portion of the Status register (W): 



-Bit No. 



AAA 



-FMASK 



' Sign status 
• Carry status 

■ Zero status 

■ Overflow status 



H Scratchpad Data Counter Register H (Registers 10 and 11) 

I The Interrupt Control Bit in the Status register (W). 

ISAR Indirect Scratchpad Address Register 

J Scratchpad Register 9 

K Scratchpad Registers 12 and 13 

Overflow status 

p4 A 4-bit I/O port number 

p8 An 8-bit I/O port number 

PCO Program Counter 

PCI Stack register 

Q Scratchpad Registers 14 and 15 



2-19 



s 

sr 
TMASK 



Any of the following operands and Scratchpad addressing modes: 

R direct address of bytes through 1 1 

S implied addressing via ISAR 

I implied addressing via ISAR, with auto-increment of the low-order 
three ISAR bits 

D implied addressing via ISAR, with auto-decrement of the low-order 
three ISAR bits 
Sign status 

The register specified by the r argument 
A 3-bit mask composed of a portion of the Status register (W): 




W The CPU Status register 

Z Zero status 

x<y,z> Bits y through z of the quantity x. For example, A <3,0> represents the low-order four bits of the Ac- 
cumulator; addr <15,8> represents the high-order eight bits of a 16-bit memory address 
Contents of location enclosed within brackets. If a register designation is enclosed within the brackets, 
then the designated register's contents are specified. If an I/O port number is enclosed within the brackets, 
then the I/O port contents are specified. If a memory address is enclosed within the brackets, then the con- 
tents of the addressed memory location are specified. 

Implied memory addressing; the contents of the memory location or register designated by the contents of 
a register 
Logical AND 
Logical OR 
Logical Exclusive OR 

♦— ' Data is transferred in the direction of the arrow 

•• — ► Data is exchanged between the two locations designated on either side of the arrow 

Under the heading of STATUSES in Table 2-1 , an X indicates statuses which are modified in the course of the instruc- 
tions' execution. If there is no X, it means that the status maintains the value it had before the instruction was ex- 
ecuted. A or 1 means the status is cleared or set, respectively. 



[] 



A 

V 
V- 



2-20 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 2-1. 3870/F8 Instruction Set Summary 











STATUSES 




TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 




OPERATION PERFOrtMED 


C 


z 


s 











INS 


P4 


1 





X 


X 









tA]-[P4l 
Input to Accumulator from I/O port. 




IN 


P8 


2 





X 


X 









[A]~[P8l 


5 




















Input to Accumulator from I/O port. 




OUTS 
OUT 


P4 
P8 


1 
2 














[P41*-[A1 . 

Output to I/O port from Accumulator. 
[P8]-[A] 

Output to I/O port from Accumulator. 




LM 




1 














[A]>-[[DCO]], [DC0]*-[DC0]+1 
Load the Accumulator via DCO and auto-Increment DCO. 




ST 




1 














[[DCO]]>-[Al, [DCO]— [DCO+1] 
Store the Accumulator via DCO and auto-increment DCO. 




LR 


A,r 


1 














(A]~[SRI 
Load the contents of the specified register, SR, into the Accumulator. Increment or decrement 
ISAR if specified by r. 




LR 


A,DPCHR 


1 














[A]— [DPCHR] 
Load Accumulator with the conterits of the specified DPCHR. 




LR 


r,A 
















[SRJ-IA] 


u . 




















Load the contents of the Accumulator into the specified register. Increment or decrement ISAR 


u 

z 




















if specified by r. 


lU 


LR 


DPCHR,A 


1 














[DPCHR1^[A] 


s 




















Load the contents of the Accumulator Into the specified DPCHR. 


UJ 

. ff 


LR 


DCO.H 


1 














[DCO]-[H] 


^ 




















Load the contents of Scratchpad registers 10 and 11 into DCO. 


o 

s 

111 


LR 


DCO.Q 


1 














[DCO]-[Q] 




















Load the contents of Scratchpad registers 14 and 15 into DCO. 


s 

> 

K 


LR 


H.DCO 


1 














[H]-tDCO] 




















Load the contents of DCO into Scratchpad registers 10 and 11. 


LR 


Q.DCO 


1 














[a]-(DCoi 


£ 


LR 
LR 
LR 
PK 


PCI.K 
K,PC1 
PCO.Q 


1 
1 
1 

1 














Load the contents of DCO into Scratchpad registers 14 and 15. 
ipc1]-lK] 

Load the contents of Register K into the Stack register. 
[k]-lPC11 

• Load the contents of the Stack register into Register K. 
[PC0]~tQl 

Load the contents of Register Q into the Program Counter. 
[PC1]-[PC0], [PCO]-IQi . 

Save the pontents of the Program Counter In the Stack register, then load the contents of 

Register Q into the Program Counter. 



Table 2-1. 3870/F8 Instruction Set Sunnmary (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUSES 


OPERATION PERFORMED 


C 


z 


s 


o 






111 
i 

«t 2 
§^ 

Ul 
M 


AS 
ASD 
NS 
XS 
DS 


r 
r 
r 

r 
r 


1 
1 
1 

1 


X 
X 

b 


X 


X 
X 
X 
X 
X 


X 
X 
X 
X 
X 


X 
X 


X 






lAl-LAl+lSR] 
Add binary the contents of the specified register to the contents of the Accumulator. Increment 
or decrement ISAR if specified by r. 

[A1-IA]+[SR1 
Add decimal the contents of the specified register to th« contents of the Accumulator; that is, 
both numbers are assumed to be BCD digits. Increment or decrement ISAR if specified by r. 

[A]— [A] A [SRl 
' AND the contents of the specified register with the contents of the Accumulator. Increment or 
decrement ISAR if specified by r. 

tA]-^[A]V-[SRl 
Exclusive-OR the contents of the specified register with the contents of the Accumulator. Incre- 
ment or decrement the ISAR if specified by r. 

[SR]— [SRl-1 
Decrement the specified register. Increment or decrement ISAR if specified by r. 


Ul 

o 

s 

Ul H 

Q ~ 

Z 

o 

M 


AM 
AMD 
NM 
OM 
XM 
CM 




1 

1 
1 
1 
1 
1 


X 
X 




X 


X 
X 
X 
X 
X 
X 


X 
X 
X 
X 
X 
X 


X 
X 

6 




X 






[A1-IA1+ [[DCO]], [DC01-[DC0] + 1 
Add Accumulator contents to the contents of the memory location addressed by DCO. Incre- 
ment DCO. 

[A]— [A]+I[DCO]], [DC0]-[DC0]+1 
Decimal add Accumulator contents to the contents of the memory location addressed by DCO. 
Increment DCO. 

IA]'-[A] A [[DCOll, IDCO]— [DCO]+ 1 
AND Accumulator contents with the contents of the memory location addressed by DCO. Incre- 
ment DCO. 

[Al-[A] V llDCOU, [DCO]— [DC01+ 1 
OR Accumulator contents with the contents of the memory location addressed by DCO. Incre- 
ment DCO. 

lAl-EAl-V-EEDCOl], [DC0l-[DC0]+1 
Exclusive-OR Accumulator contents with the contents of the memory location addressed by 
DCO. Increment DCO. 

[[DCO]] - [A], [DCO]'-[DCO]+ 1 
Subtract the contents of the Accumulator from the contents of the memory location addressed 

' by DCO. Only the status flags are affected. Increment DCO. 


Ul 

D 

Ul 


LISU 
LISL 
DCI 
US 

LI 


DATA3 
DATA3 
ADDR 
DATA4 

DATA8 


1 
1 
3 
1 

2 














: [ISAR<5.3>]— DATA3 

Load immediate into the upper three bits of the ISAR. 
[ISAR<2.0>H3ATA3 

Load immediate into the lower three bits of the ISAR. 
[DCOl— ADDR 

Load immediate data into the DCO. 
[A<3,0>] — DATA4 

Load immediate data into the lower four bits of the Accumulator. Clear the high four bits of the 

Accumulator. 
[A1—DATA8 

Load immediate data into Accumulator. 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 2-1. 3870/F8 Instruction Set SunnmarY (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUSES 


OPERATION PERFORMED 


C 


z 


s 









< 

E 
lU 
0. 

o 
III 



Ul 

s 


Al 
Nl 
01 
XI 
CI 


DATA8 
DATA8 
DATA8 
DATAB 
DATA8 


2 
2 
2 
2 
2 


X 



X 


X 
X 
X 
X 
X 


X 
X 
X 
X 
X 


X 



X 






[Al-[A] + DATA8 

Add immediate to Accumulator: 
[A]-[A] ADATA8 

AND immediate with Accumulator. 
[A]— [A1VDATA8 

OR immediate with Accumulator. 
lAl— [A1V-DATA8 

Exclusive-OR immediate with Accumulator. 
DATA8- [A] 

Compare immediate: subtract Accumulator contents from immediate data, but only the status 

flags ai'e affected. 


a. 
S 


Pt 
BR 

JMP 


ADDR 
DISP 
ADDR 


3 
2 
3 














[PC1]-(PC0], [PCO]— ADDR 

Save Program Counter in Stack register, then load immediate address Into Program Counter. 
IPCOI— [PCOl + DISP 

Add immediate displacement to contents of Program Counter. 
[PCO] — ADDR, [A]— ADDR<15,8> 

Load immediate address into Program Counter, toad the high order byte of the address into the 

Accumulator. 


z . 


■ b -■ 



z 



u 
.z 



T- 

u 

z 


BT 

BF 
BP 
BC 
BZ 

BM 
BNC 
BNZ 
BNO 
BR7 


. DATA3,DISP 

DATA4,DISP 
DISP 
DISP 
DISP 
DISP 
DISP 
DISP 
DISP 
DISP 


2 

2 
2 
2 
2 

2 
2 
2 
2 
2 














If DATA3 VTMASK tS then [PCOl~[PCO] + DISP 

OR the 3 bits of immediate data with the current TMASK. If any resulting bit is a 1, add the dis- 
placement to PCO. 
If DATA4 = FMASK, then [ PCO]-! PCO] + DISP 

If the 4 bits of immediate data are equal to FMASK, add the displacement to PCO. 
!f is] = 1 then [PCO]— [PCO] + DISP 

Branch relative if the Sign bit is set. 
If [C] = 1 then IPCO]— IPC0] + DISP 

Branch relative if the Carry bit is set. 
If [Z] =5 1 then IPCO]— t PCO] + DISP 

Branch relntive if the Zero bit is set. 
If Is] =otnen irCOl— [PCO] + DISP 

Branch relative if the Sign bit is reset. 
If IC] =Othen IPCO]— I PCO] + DISP 

Branch relative if the Carry bit is reset. 
If IZ] =Othen-lPCO]— [PCO] + DISP 

Branch relative if the Zero bit is reset. 
If 10] =Othen IPCO]— IPC0] + DISP 

Branch relative if the Overflow bit is reset. 
If IISAR<2.0>]=7then IPCO]— IPC0] + DISP 

If the low three bits of the ISAR are not all 1s, branch relative. 



Table 2-1. 3870/F8 Instruction Set Summary (Continued) 



OPERAND(S) 



OPERATION PERFORMED 



Ul 111 

■? > 

K O 



XDC 
LR 
LR 

POP 



A,IS 
IS.A 



[DCOl— •[DC1] 

Exchange :the contents of DCO with the contents of DC1. 
[Al— [ISAR] 

Load the contents of ISAR into the Accumulator. 
[ISAR]— [Al 

Load the contents of the Accumulator into the ISAR. 
[PCO]— [PCI] 

Load the contents of the Stack register, into the Program Counter. 



GC QC ul 

jU jU P 

W W K 

a a 

ul m tk 

ce e O 



ADC 



[DCO]— [DCO] + [A] 
Add the contents of DCO to the contents of the Accumulator, which is treated as a signed binary 
number. Store the, result in DCO. 



SR 



COM 
LNK 
INC 
CLR 



) ►[7 



Shift the contents of the Accumulator right one bit. The most significant bit becomes a 0. 

I — ^ 

0000 1 7 I o| 

nr A 

Shift the contents of the Accumulator right four bits. The most significant four bits become Os. 



Shift the contents of the Accumulator left one bit. The least significant bit becomes a 0. 

i I 

Shift the contents of the Accumulator left four bits. The least significant four bits become Os. 

[A]-[a"] 

Complement Accumulator contents. 
[A]— [A] + C 

Add the Carry to the contents of the Accumulator. 
[A]-[A]+1 

Increment the contents of the Accumulator. 
[A].-0 

Clear the Accumulator. 



ADAM OSBORNE & ASSOCIATES. INCORPORATED 



Table 2-1. 3870/F8 Instruction Set Summary (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUSES 


OPERATION PERFORMED 


C 


z ■ 


, s 


0. 






3 
K 

oe 
IS 

z 


Dl 
El 


















[l]-0 

Set the interrupt enablff bit in the Status register,. W. to 0. 
[11-1 

Set the Interrupt enable bit in the Status register, W, toL - 


M 

3 


LR 
LR 


W,J 
J,W 
















(W]-[J] 

Move the contents of Scratchpad register 9 into the Status register, W. 
[J]-[W3 

Move the contents of the Status register, W, Into Scratchpad register 9. 




NOP 


















No operation is performed. This is not a Halt. 



THE 3870 BENCHMAt^K PROGRAM 

The fact that the 3870 has just 64 bytes of read/wrtte memory makes the benchmark program used in this book 
somewhat meaningless. We will therefore substitute a program similar to the one given in Chapter 1 for the 
TMSIOOO. A block of data is to be input via I/O Port 0. The first byte of data identifies the length of the data block to 
follow: this data block must be less than 48 bytes in length so that it will fit into scratchpad memory starting at 
scratchpad byte 10-ig. Here is the necessary program: 

INPUT FIRST BLOCK LENGTH BYTE 
SAVE IN SCRATCHPAD BYTE 
INITIALIZE ISAR 



LOOP 



INS 





LR 


0,A 


LISU 


1 


LISL 





INS 





LR 


S,A 


LR 


A,IS 


INC 




LR 


IS.A 


DS 





BNZ 


LOOP 



INPUT DATA BYTE 

SAVE IN NEXT SCRATCHPAD BYTE 

INCREMENT ALL SIX ISAR BITS 



DECREMENT SCRATCHPAD BYTE 
RETURN IF NOT ZERO 



Accumulator 



ISAR 



E^ 



LRr.A 
LR A,r 



Register 
Address 
Pointer 



CPU 
General 
Registers 



Status 



^M 



ICB 

Overflow 

' Zero 

Carry 

Sign 



3 



n 



Ji a 



LR J,W 7 
LR WJ 8 



H: 

C 
D 



15 



Data Counter 



Memory 
Address 
Pointer 



3 



]3iJ 



10 



3F 



PI, Interrupt, Reset 



PK 



15 




Program Counter 



LR PO,Q i i 



POP 






Interrupt 
Reset 



'r 



Stack Pointer 



63 



LR DC.H 
LR H,DC 
LR DC,Q 
LR Q,DC 



Figure 2-4. Instructions That Move Data Between the Scratchpad and Various Registers 



2-26 



Table 2-2. Timing and ROMC States for F8 Instruction Set 



o 
m 
w 
O 

< 
o 

< 

@ 



MNEMONIC 


OPERANDIS) 


CYCLE 


ROMC 
STATE 


AOC 
Al 


DATA8 


L 
S 
L 


A 


'3 






S 





AM 




L 
S 


2 



AMD 




L 
S 


2 



AS 


r 


S 





ASO 
BF ( 


r 
DATA4,DISP 


S 
S 
S 


1C 

1C 


Branch < 




L 


1 


I 




S 









S 


1C 


No ( 

Branch ( 

BR7 ( 


DISP 


s 
s 
s 


3 

3 


No BratKh \ 
Branch 
BT ( 


DATA3,DISP 


s 

L 

s 
s 



1 
Q 
1C 


NO { 




s 


3 


Branch \ 




s 
s 





Branch \ 
CI 


DATA8 


L 
S 
L 


1 

3 






S 





CM 




L 
S 


2 



COM 
DCI 


ADDR 


S 

L 



11 






S 


3 






L 


E 






S 


3 






S 





01 




S 


IC 






s 





DS 


r 


L 





El 




S 


IC 






S 





IN 


P8 


L 


3 






L 


IB 






S 





INC 
INS 


Oor 1 


S 
S 
S 



IC 



INS 


2 

through 

15 


L 
L 
S 


IC 
1B 



(INTERRUPT) 


L 


IC 






L 


08 






L 


13 


JMP 


ADOR 


S 

L 



3. 






L 


C 






L 


14 






S 





LI 


DATA8 


L. 


3 






S 





US 


DATA4 


S 





List 


DATA3 


S 




















ROMC 


MNEMONIC 


OPERANDIS) 


CYCLE. 


STATE 


USU 


DATA3 


S 





LM 




L 


2 






S 





LNK 




S 





LR 


A,IS 


s 





LR 


'a,kl 


S 





LR 


A,KU 


s 





LR 


A,QL 


s 





LR 


A.QU 


S 





LR 


A,r 


s 





LR 


DCO,H 


L 


16 






L 


19 






S 





LR 


DCO.Q 


L 


16 






L 


19 






s 





LR 


H.DCO 


L 


6 






L 


9 






S 





LR 


IS,A 


s 





LR 


J,W 


s 





LR 


K,P 


L 


7 






L 


B 






S 





LR 


KL,A 


S 





LR 


KU,A 


s 





LR 


P,K 


L 


15 






L 


18 






S 





LR 


PCO.Q 


L 
L 
S 




LR 


CDCO 


L 


6 






L 


9 






S 





LR 


QL,A 


S 





LR 


au,A 


S 





LR 


r,A 


S 





LR 


W,J 


s 


IC 






s 





Nl 


DATA8 


L 


3 






S 


0. 


NM 




L 


2 






S 





NS 


r 


S 





01 


DATA8 


L 


3 






S 





OM 




L 


2 






S 





OUT 


PS 


L 


3 






L 


1A 






S 





OUTS 


Oor 1 


S 


IC 






S 





OUTS 


2 


L 


IC 




through 


L 


1A 




15 


S 





PI 


ADDR 


L 


3 






S 


D 






L 


C 






L 


14 






S 






2-27 



Table 2-2. Timing and ROMC States for F8 Instruction Set (Continued) 









ROMC 


MNEMONIC 


OPERAND (S) 


CYCLE 


STATE 


PK 




L 


12 






L 


14 






S 





POP 




S 


4 






S 





(RESET) 


S 


1C 






L 


8 






S 





SL 


1 


S 





SL 


4 


S 





SR 


1 


s 





SR 


4 


•i s 





ST 




L 


5 






S 





XI 


DATA8 


L 


3 






S 





XM 




L 


2 






S 





XS 


r 


S 






The following symbols are used in Table 2-3: 

aaaa Four bits choosing the register addressing mode; 
0000-1011 Registers - B directly addressed 

1100 ISAR addresses the register 

1 101 ISAR addresses the register. Increment low three bits of ISAR. 

1110 ISAR addresses the register. Decrement low three bits of ISAR. 

1111 NOP. No operation is performed if aaaa=Fi g. 

cc Two bits choosing a Scratchpad register: 

00~KU Scratchpad Register 12 

01 -KL Scratchpad Register 13 
:iO~QU Scratchpad Register 1,4 

11~QL Scratchpad Register 15 
d One bit of immediate data, 

eeee A 4-bit port number, 
qqqq A 16-bit address, 
rr An 8-bit signed displacement, 
as An 8-bit port number, 
yy One byte (8 bits) of immediate data. 

When two numbers are given in the "Machine Cycles" column (for example, 3/3.5), the first is the execution time if no 
branch is taken, and the second is execution time if the branch is taken. 



2-28 



Table 2-3. 3870/F8 Instruction Set Object Code 



z 

DC 

o 

CD 
CO 

o 

< 

Q 

< 

@ 





OBJECT 




MACHINE 


INSTRUCTION 


CODE 


BYTES 


CYCLES 


ADC 


8E 


1 


2.5 


Al DATA8 


24 YY 


2 


2.5 


AM 


88 


1 


2.5 


AMD 


89 


1 


2.5 


AS r 


llOOaaaa 


1 


1 


ASD r 


llOlaaaa 


1 


2 


BC DISP 


82 RR 


2 


3/3.5 


BF DATA4,DISP 


lOOldddd 
RR 


2 


3/3.5 


BM DISP 


91 RR 


2 


3/3.5 


BNC DISP 


92 RR 


2 


3/3.5 


BNO DISP 


98 RR 


2 


3/3.5 


BNZ DISP 


94 RR 


2 . 


3/3.5 


BP DISP 


81 RR 


2 


3/3.5 


BR DISP 


90 RR 


2 


3.5 


BR7 DISP 


8F RR 


2 


3/3.5 


BT DATA3,DISP 


lOOOOddd 
RR 


2 


3/3.5 


B2 DISP 


84 
RR 


2 


3/3.5 


CI DATA8 


25 YY 


2 


2.5 


CLR 


70 


1 


1 


CM 


8D 


1 


2.5 


COM 


18 


1 


1 


DCI ADDR 


2A QQQQ 


3 


6 


Dl 


1A 


1 


2 


DS r 


OOllaaaa 


1 


1.5 


El 


IB 


1 


2 


IN P8 


26 SS 


2 


4 


INC 


IF 


1 


1 


INS P4 


lOIOeeee 


1 


4 


JMP ADDR 


29 OQQQ 


3 


. 5.5 


LI DATA8 


. 20 YY 


2 


2.5 


LIS DATA4 


Ollldddd 


1 


1 


LISL DATA3 


OllOlddd 


1 


1 


LISU DATA3 


OllOOddd 


1 


1 


LM 


16 


1 


2.5 





OBJECT 




MACHINE 


INSTRUCTION 


CODE 


BYTES 


CYCLES 


LNK 


19 






LR A.DPCHR 


OOOOOOcc 






LR A,IS 


OA 






LR A,r 


OlOOaaaa 






LR DCH 


10 






LR DC.Q 


OF 






LR DPCHR,A 


OOOOOIcc 






LR H.DC 


11 






LR IS,A 


OB 






LR J,W 


IE 






LR K.PCI 


08 






LR PCO.Q 


OD 






LR PCI.K 


09 






LR CDC 


OE 






LR r,A 


OlOlaaaa 






LR W,J 


ID 






Nl DATA8 


21 YY 




2.5 


NM 


8A 




2.5 


NOP 


2B 






NS r 


nilaaaa 






01 DATA8 


22 YY 




2.5 


OM 


8B 




2.5 


OUT P8 


27 SS 






OUTS P4 


lOlleeee 






PI ADDR 


28 QQQQ 




6.5 


PK 


OC 






POP 


1C 






SL 1 


13 






SL 4 


15 






SR 1 


12 






SR 4 


14 






ST 


17 




2.5 


XDC 


2C 






XI DATA8 


23 YY 




2.5 


XM 


8C 




2.5 


XS r 


1 1 lOaaaa 







THE 3850 CPU 

Beginning with the 3860 CPU, we are going to describe the individual devices of the F8 microcomputer system. 
The 3850 CPU and the 3851 PSU descriptions depend on the preceding 3870 discussion for a frame of 
reference. That is to say, these two F8 devices are described as variations of the 3870, rather than as stand- 
aione devices. 

Functions implemented on the 3860 CPU are illustrated in Figure 2-6. 

These are the functions which one would expect to find on a CPU chip, and which are on the 3860 CPU: 

-The Arithmetic and Logic Unit 

-The Control Unit and Instruction register 

- Logic needed to interface the System Bus with the control signals which are input and output by the CPU 

- Accumulator register 

There is no memory addressing logic, and there are no memory addressing registers on the 3860 CPU. Stack 
Pointer, Program Counter and Data Counter registers are all maintained on memory chips and memory interface 
chips. 

With the F8 scheme, memory addressing logic will be duplicated if more than one memory device is present in 
an F8 microcomputer system. We will discuss shortly how potential contention problems are resolved under 
these circumstances. 



2-29 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Clock Logic 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Interrupt Priority 
Arbitration 



Bus Interface 
Logic 



Accumulator 
Register(s) 



Data Counters) 



Stack Pointer 



Program Counter 



System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 
Interface Logic 



1/0 Ports 
Interface Logic 



Read Only 
Memory 



I/O Ports 



Direct Memory 

Access Control 

Logic 



RAM Addressing 

and 

Interface Logic 



Read/Write 
Memory 



Figure 2-5. Logic of the Fairchild F8 3850 CPU 



Two advantages accrue from having no memory address logic on the CPU chip: 

1) No address lines are needed on the System Bus, so neither the CPU nor connecting devices need 16 address pins. 
These 16 pins are used instead to implement two 8-bit I/O ports at each device. 

2) The real estate on the CPU chip which would have been used by Address registers and memory addressing logic is 
available for other purposes; it is used to implement 64 bytes of read/write memory. 

Having I/O ports and read/write memory on the CPU chip paves the way for some very low-cost small 
microcomputer configurations; for example, the 3850 CPU and the 3851 PSU form a two-device microcomputer 
system, with all of the necessary prerequisites for reasonable performance. Until the advent of the 3870 single-chip 
microcomputer, this two-chip configuration represented the lowest cost 8-bit microcomputer on the market. 

The disadvantage of removing memory addressing logic from the CPU chip is that standard memory devices can 
no longer connect directly to the System Bus. This bus has no address lines; therefore, separate logic devices must 
create the interface needed by standard memories. In the F8 system this is done by the 3852 DM! and the 3853 SMI 
devices. 

Clock signal generation logic is aiso part of the 3850 CPU. This is now standard among microcomputers. 



2-30 



o 

m 
w 
o 

< 
o 

< 

® 



F8 PROGRAMMABLE REGISTERS AND STATUS FLAGS 

F8 programmable registers and status flags are Identical to the 3870. For details, refer to the earlier discussion. 

F8 ADDRESSING MODES 

3870 and F8 addressing modes are identical, both for scratchpad memory and for external program memory. But 
memory addressing logic is implemented on F8 memory devices, not on the 3860 CPU. 

Every 3851 PSU contains its own Program Counter (PCO), Stack register (PS1), and Data Counter (DCO). The 3851 PSU 
has no Data Counter buffer (DC1). 

The 3852 DMI and 3853 SMI devices contain all four Address registers: PCO, PCI, DCO and DC1. 

Since Address registers are present on every PSU, DMI or SMI device in an F8 microcomputer system, these 
registers will be duplicated in any F8 system that contains more than a minimum amount of memory. So long as 
the microcomputer system has been correctly configured, this presents no problem. Every memory device contains 
identical connections to the common System Bus, and instructions that modify the contents of any Address register do 
so identically for all memory devices. For example, if there are three memory devices, and therefore three Program 
Counters in an F8 system, every Program Counter is incremented identically after a byte of object code is fetched. This 
being the case. Address registers on different memory devices will always contain identical address information. 

Every F8 device that contains memory addressing logic also contains a memory address mask which you must 
define when ordering the device. This mask identifies the device's addressed space. Thus, a memory device will only 
respond to memory accesses within its address space. So long as no two devices have overlapping address spaces 
(and if they do, that is a logic design error) there is no chance for memory contentions to arise. In order to illustrate 
this point, consider the very simple example of an F8 configuration that contains two 3851 PSUs. Each 3851 PSU con- 
tains 1024 bytes of read-only memory. Let us assume that 3851 PSU #1 responds to memory addresses in the range 
OOOOie through 03FFi 6- while PSU #2 responds to memory addresses in the range 0400i6 through 07FFi6- This may 
be illustrated as follows: 

These two Program 
Counters always 
contain the 
PSU 1 same information PSU 2 



15 


14 


13 


12 


11 


10 


9 


8 


7 


6 


5 


4 


3 


2 


1 







































DCO or PCO 


^ 

















IVIASK 



15 


14 


13 


12 


11 


10 


9 


8 


7 


6 


5 


4 


3 


2 


1 





1 
































1 

1 
1 


DCO or PCO 


E 














1 


MASK 



PSU 1 responds only If PCO or DCO bits 10 through 
15 are 000000, because 
OOOOie =00000000000000002 
03FFi6 =00000011111111112 

MASK 



PSU 2 responds only if PCO or DCO bits 10 through 
15 are 000001, because 
040016 =00000100000000002 
07FFi6 =00000111111111112 

MASK 



Any memory reference instruction will identify a memory address as the contents of either the Program Counter (PCO) 
or the Data Counter (DCO). When this address is in the range OOOOig through OSFFiq, PSU #1 will respond but PSU 
#2 will not. If this address is in the range 0400i6 through 07FFi6. then PSU #2 will respond but PSU #1 will not. A 
memory address of O8OO16 or more will result in neither PSU responding. 

There is one circumstance under which memory addressing contentions can arise. Since the 3851 PSU does not con- 
tain a DC1 register, it does not respond to the XDC instruction which exchanges the contents of the DCO and DC1 
registers. Therefore, in an F8 configuration that contains 3851 PSUs together with 3852 DMI and/or 3853 SMI devices, 
execution of an XDC instruction will result in 3851 PSU DCO registers containing different information from 3852 DMI 
or 3853 SMI DCO registers. If an external data memory reference instruction is now executed, it is possible for a 3851 
PSU and 3852 DMI or 3853 SMI device to simultaneously consider itself selected. For example, consider an F8 con- 
figuration which contains a 3851 PSU and 3853 SMI. Suppose the 3851 PSU mask causes it to respond to addresses in 
the rangeOOOOis through OSFFig. while the 3853 SMI responds to all other memory addresses. Now, if Data Counter 
DCO contains 02A3i6 while the Data Counter buffer (DC1) contains 0A7Fi6. then, following execution of an XDC in- 



2-31 



struction, nothing will happen to the contents of the 3851 PSU DCO register; however, the 3853 SMI DCO register will 
contain 0A7Fi6- Any instruction that accesses data memory via DCO will now cause both the 3851 PSU and the 3853 
SMI to consider themselves selected. 

In F8 configurations that include the 3851 PSU together with 3852 DMI or 3853 SMI devices, the best way of avoiding 
memory addressing problems is to not use the XDC instruction. If you do use the XDC instruction, you must be particu- 
larly careful to ensure that DCO is never within a 3851 PSU's address space when the XDC instruction is executed. 

F8 CLOCK CIRCUITS 

Three ways of generating an F8 system clock have been advertised; these are the RC mode. Crystal mode, and 
External mode. Only Crystal mode has worked consistently in practice. 

Using the Crystal mode, a crystal in the 1 to 2 MHz range connects across the XTLX and XTLY pins; along with 
two capacitors (Ci and C2), which provide a highly precise clock frequency: 




The external crystal (and capacitors), together with internal circuitry, combine to form a parallel resonant crystal 
oscillator. The two capacitors should be approximately 15pF. The crystal should have these characteristics: 

Frequency: 1 to 2 MHz 
Mode of Oscillation: Fundamental 
Operating Temperature Range: to 70°C 
Equivalent Resistance: 1 to 1.5 MHz ~ 475(1 
1.5 to2MHz~350n 

Resonance: Parallel 
Drive Level: lOmW 
Load Capacity: ~ 15pF 
Frequency Tolerance 
Holder (case) Style: 



Per customer's requirements 



You can use an external clock to synchronize an F8 system with external logic. The clock signal must be input to the 
3850 XTLY pin as follows: 

Vss 





RC 






3850 
CPU 


External 


XTLY 


Clock 


XTLX 







2-32 



Table 2-4. ROMC Signals and What They Imply 



ROMC 
4 3 2 10 


HEX 


CYCLE 
LENGTH 


. FUNCTION 





00 


S,L 


Instruction Fetch. The device whose address space includes the contents of the FCO register must place 
on the Data Bus the op code addressed by PCO. Then all devices increment the contents of PCO. 


1 


01 


L 


The device whose address space includes the contents of the PCO register must place on the Data Bus 
the contents of the memory location addressed by PCO. Then all devices add the 8-bit value on the Data 
Bus, as a signed binary number, to PCO. 


10 


02 


L 


The device whose DCO addresses a memory word within the address space of that device must place 
on the Data Bus the contents of the memory location addressed by DCO. Then all devices increment 
DCO. 


11 


03 


L,S 


Similar to 00, except that it is used for Immediate Operand fetches (using PCO) instead of instruction 
fetches. 


10 


04 


S 


Copy the contents of PCI into PCO. 


10 1 


05 


L 


Store the Data Bus contents or write bus contents into the memory location pointed to by DCO. Incre- 
ment DCO. 


110 


06 


L 


Place the high order byte of DCO on the Data Bus. 


111 


07 


L 


Place the high order byte of PCI on the Data Bus. 


10 


08 


L 


All devices copy the contents of PCO into PCI. The CPU outputs zero on the Data Bus in this ROMC 
state. Load the Data Bus into both halves of PCO thus clearing the register. 


10 1 


09 


L 


The device whose address space includes the contents of the DCO register must place the low order 
byte of DCO onto the Data Bus. 


10 10 


OA 


L 


All devices add the 8-bit value on the Data Bus, treated as a signed binary number, to the Data Counter. 


10 11 


OB 


L 


The device whose address space includes the value in PCI must place the low order byte of PCI on the 
Data Bus. 


110 


OC 


L 


The device whose address space includes the contents of the PCO register must place the contents of 
the memory word addressed by PCO onto the Data Bus. Then all devices move the value which has just 
been placed on the Data Bus into the low order byte of PCO. 


110 1 


OD 


S 


All devices store in PCI the current contents of PCO, incremented by 1. PCO is unaltered. 


1110 


OE 


L 


The device whose address space includes the contents of PCO must place the contents of the word ad- 
dressed by PCO onto the Data Bus. The value on the Data Bus is then moved to the low order byte of 
DCO by all devices. 


1111 


OF 


L 


The interrupting device with highest priority must place the iow order byte of the interrupt vector on the 
Data Bus. All devices must copy the contents of PCO into PCI. All devices must move the contents of 
the Data Bus into the low order byte of PCO. 


10 


10 


L 


Inhibit any modification to the interrupt priority logic. 


10 1 


11 


L 


The device whose memory space includes the contents of PCO must place the contents of the ad- 
dressed memory word on the Data Bus. All devices must then move the contents of the Data Bus to the 
upper byte of DCO. 


10 10 


12 


L 


All devices copy the contents of PCO into PC1. All devices then move the contents of the Data Bus into 
the low order byte of PCO. 


10 11 


13 


L 


The interrupting device with highest priority must move the high order half of the interrupt vector onto 
the Data Bus. All devices must move the contents of the Data Bus Into the high order byte of PCO. The 
Interrupting device will reset its interrupt circuitry (so that it is no longer requesting CPU servicing and 
can respond to another interrupt). 


10 10 


14 


L 


All devices move the contents of the Data Bus into the high order byte of PCO. 


10 10 1 


15 


L 


All devices move the contents of the Data Bus into the high order byte of PCI. 


10 110 


16 


L 


All devices move the contents of the Data Bus into the high order byte of DCO. 


10 1 1 1 


17 


L 


All devices move the contents of the Data Bus into the low order byte of PCO. 


110 


18 


L 


All devices move the contents of the Data Bus into the low order byte of PCI. ■ 


110 1 


19 


L 


All devices move the contents of the Data Bus into the low order byte of DCO. 


1 1 0. 1 


1A 


L 


During the prior cycle an I/O port timer or Interrupt control register was addressed. The device contain- 
ing the addressed port must move the current contents of the Data Bus into the addressed port. 


110 1 1 


IB 


L 


During the prior cycle the Data Bus specified the address of an I/O port. The device containing the ad- 
dressed I/O port must place the contents of the I/O port on the Data Bus. (Note that the contents of 
timer and interrupt control registers cannot be read back onto the Data Bus.) 


1110 


1C 


LorS 


None. 


1110 1 


ID 


S 


Devices vyith DCO and DC1 registers must switch registers. Devices without a DC1 register perform no 
operation. 


11110 


IE 


L 


The device whose address space includes the contents of PCO must place the low order byte of PCO 
onto the Data Bus. 


11111 


IF 


L 


The device whose address space includes the contents of PCO must place the high order byte of PCO on 
the Data Bus. 



2-33 



F8 CPU PINS AND SIGNALS 

3850 CPU pins and signals are illustrated in Figure 2-6. A description of these signals is useful as a guide to the 
way in which the F8 microcomputer system works. 




I/O 00 
ROMCO 
R0MC1 
R0MC2 
R0MC3 

Pin Name 

*DBO - DB7 

*(S>, WRITE 

I/O 00 - 1/0 07 

I/O 10-1/0 17 

♦ ROMCO - R0MC4 

* EXT RES 

♦ INT REQ 

•ICB 

RC 

XTLX 

XTLY 

Vss- Vqd, Vqg 



Description 

Data Bus Lines 
Clock Lines 
I/O Port Zero 
I/O Port One 
Control Lines 
External Reset 
Interrupt Request 
Interrupt Control Bit 
Clock Oscillator 
Crystal Clock Line 
External Clock Line 
Power Lines 



INT REQ 

ICB 

R0MC4 

Type 

Bidirectional 

Output 

Bidirectional 

Bidirectional 

Output 

Input 

Input 

Output 

Input 

Output 

Input 



♦These signals connect to the System Bus. 



Figure 2-6. Fairchild 3850 CPU Signals and Pin Assignments 

The Data Bus lines (DBO - DB7) and the control lines (ROMCO - R0MC4) provide the heart of all data and control 
information flow. 

The Data Bus lines are conrimon, bidirectional lines, and are the only conduit for data to be transmitted between devices 
of an F8 microcomputer system. 

A lack of address lines on the System Bus usually means that data and addresses must be multiplexed on a 
single set of eight lines — which slows down all memory reference operations; they must now proceed in three 
serial increments, rather than in one parallel increment. In the F8 System Bus. multiplexing is rarely needed, 
since addresses originate within memory devices, or memory interface devices, whence they are transmitted 
directly to memory. In other words, the only time addresses are ever transmitted on the Data Bus is when they are 
being transmitted as data. 

Refer to Figure 2-1. Suppose a memory reference instruction needs to access a byte of dynamic RAM. ROMC control 
signals (described in the next paragraph) specify that the memory byte whose address is implied by the Data Counters 
(DCO) is to be referenced. Every memory device receives the ROMC control signals, but only the 3852 DMI finds that its 
address space includes the Data Counter implied address; therefore, only the 3852 DMI will respond to the memory 
reference instruction. The 3852 DMI then outputs an address directly to dynamic RAM; this address is not transmitted 



2-34 



o 
ffi 
u> 
o 

< 

Q 

< 

@ 



ROMC STATE 



via the System Bus. If the memory reference instruction requires data to be input to or output from dynamic RAM, the 
data transfer occurs directly between the System Bus and Dynamic RAM, bypassing the 3852 DMI entirely. 

Since the 3851 PSU, the 3852 DMI and the 3853 SMI devices all contain Address registers and 
address generation logic, they also contain rudimentary Arithmetic and Logic Units equivalent to 
very primitive CPUs. These primitive CPUs are driven by 5-bit instructions called ROMC states. ROMC states are out- 
put by the 3850 CPU via five control iines, ROI\^C0 - ROfACA. Each five-bit combination of ROMC signal states 
identifies one of 32 possible operations which the memory devices may have to perform to accomplish one step of an 
instruction's execution. For example, ROMC state 00000 causes the contents of memory bytes addressed by the Pro- 
gram Counter to be transmitted to the CPU; this is the "instruction fetch" ROMC state. Table 2-4 summarizes the in- 
terpretation of ROMC states. 

<i) and WRITE are two timing signals output by the 3850 CPU to synchronize events within the rest of the F8 system. 



The EXT RES line disables interrupts and loads a address into all Program Counters, causing program execution to 
restart with the instruction code stored in external memory byte 0. 



INT REQ and ICB are signals used for overall interrupt control. INT REQ is the master jihe on which all interrupt re- 
quests are transmitted to the 3850 CPU. ICB is output low by the CPU if interrupts are enabled, and it is output high by 
the CPU if interrupts are disabled. 

The two I/O ports which are part of the 3860 CPU device use pins 1/000 • 1/007 and 1/010 - 1/01 7, respectively. 

RC, XTLX and XTLY are the three pins used for clock inputs. 

F8 TIMING AND INSTRUCTION EXECUTION 

All instructions are executed in cycles, which are timed by the trailing edge of WRITE. 

There are two types of instruction cycle, the short cycle which is four $ clock periods long, and the long cycle 

which is six <I> clock periods long. The long cycle is sometimes referred to as 1 .5 cycles. WRITE high appears only at the 
end of an instruction cycle. Timing may be illustrated as follows: 



WRITE 



WRITE 




The simplest instructions of the F8 instruction set execute in one short cycle. The most complex instruction (PI) re- 
quires two short cycles plus three long cycles. 

Table 2-2 summarizes the sequence in which short (S) and long (L) machine cycles are executed for each F8 in- 
struction. ROMC states defining operations performed during each machine cycle are summarized in Table 2-4. 



2-35 



The trailing edge of the WRITE pulse triggers the next ROMC state to be output on the ROMCO - R0MC4 lines: 



WRITE 



ROMC 




One short machine cycle ■ 



For any instruction that only accesses the Accumulator or scratchpad nnemory, no further System Bus activity is .re- 
quired, since all subsequent operations will occur within the F8 CPU. This inactivity on the System Bus is used to over- 
lap the last (or only) machine cycle of one instruction with the instruction fetch for the next instruction. For instructions 
that execute in a single machine cycle, accessing only logic within the 3850 CPU, timing may be illustrated as follows: 



WRITE 




Short machine 
cycle 1 



Instruction 2 execute 

Instruction 3 fetch 

Short machine 

cycle 2 



Instruction 3 execute 

Short machine 

cycle 3 



Instructions that do access external memory or I/O ports will always terminate with a machine cycle that does not 
cause any System Bus activity; the next instruction is fetched during this machine cycle. This may be illustrated as 
follows: 



WRITE 




Instruction 1 execute 



Long machine cycle 1 



Instruction 1 execute 

Instruction 2 fetch 
Short machine cycle 2 



If for any reason data is to be transferred via the Data Bus during a machinecycle, then the data appears on the Data 
Bus at some time which depends on the data source or destination. For details, see the data sheets at the end of this 
chapter. There are no accompanying control signals since none are needed; the ROMC state identifies events which are 
occurring. Timing for any machine cycle that involves data transfer via the Data Bus may be illustrated as follows: 



4) 



WRITE 



ROMC 



DATA 




\_r~\_j~"u_/~A_j~"^ 



X 



]CX 



ROMC stable 



X 



Data stable 



2-36 



F8 I/O PORTS 

Logic associated with each F8 I/O port pin may be illustrated as follows: 



o 

< 

< 




External logic 



^x r 



The characteristics of F8 I/O port pins differ markedly from the 3870. The only point of similarity is the fact that both 
have inverse logic; when you output a 1-bit, OV is output to external logic; when you write a 0-bit, a +5V voltage is 
output to external logic. Conversely, external logic must input OV for a 1 input bit and +5V for a input bit. 

On reset or power up, F8 I/O port pins are indeterminate. You must therefore start every Reset instruction sequence 
with instructions that initialize all I/O port pins. In contrast, the 3870 clears I/O Port 4 and 5 pins on reset; this gener- 
ates +5V outputs since logic is inverted. 

When using 3870 or F8 I/O ports, the following restrictions apply: 

1) You must write to every I/O port pin that is to receive data input. This is because external logic cannot write a 
to any I/O port pin that previously had a 1 bit output by the CPU. 

2) The CPU cannot output a bit (-I-5V output) to an I/O port pin if the pin is connected to external logic that is input- 
ting a' 1 bit (OV input). 

A SUMMARY OF F8 INTERRUPT PROCESSING 

The interrupt handling capabilities of the F8 system are described with the 3851 PSU and 3853 SMI devices. 
Although many different interrupt priority arbitration schemes could be implemented, the simplest scheme 
would be to daisy chain 3851 PSUs, terminating the daisy chain with a 3853 SMI if present. 

As soon as an interrupt is acknowledged, the contents of Program Counters (PCO) are saved in Stack registers (PCI); 
then an interrupt vector address is loaded into the Program' Counters. This address is a permanent mask option for 
PSUs, with the exception of bit 7, which discriminates between timer interrupts and external interrupts. The interrupt 
address vector is completely programmable for the 3853 SMI, again with the exception of bit 7, which discriminates 
between timer interrupts and external device interrupts. 

Post-interrupt housekeeping operations must be handled via an appropriate program. Defining just what this program 
consists of is not simple; an F8 system has only the Accumulator and Status register which must be saved, but at the 
other extreme, it has the entire scratchpad which could be saved. 

THE F8 INSTRUCTION SET 

The F8 and 3870 instruction sets are identical; for details see Table 2-1 and associated text. 



2-37 



THE BENCHMARK PROGRAM 

Now consider our benchmark program; for the F8 it lool<s lii<e this: 

LOAD TABLE BASE ADDRESS 
LOAD DISPLACEMENT TO FIRST FREE BYTE 
ADD TO BASE ADDRESS 
SAVE THIS ADDRESS IN DC1 
LOAD I/O BUFFER BASE ADDRESS 
LOOP LM LOAD NEXT BYTE FROM I/O BUFFER 

SWITCH ADDRESSES 
STORE IN NEXT BYTE OF TABLE 
SWITCH ADDRESSES 
DECREMENT I/O BUFFER LENGTH 
RETURN IF NOT END 

IF END, STORE SECOND BYTE OF CURRENT 
TABLE ADDRESS AS DISPLACEMENT TO 
. FIRST FREE BYTE 

The benchmaric program above mal<es the following assumptions: 

1) The I/O buffer can be located anywhere in read/write nnemory. 

2) The number of occupied bytes in the I/O buffer is maintained in scratchpad byte 0. Thus, decrementing scratchpad 
byte to zero provides the I/O buffer length. 

3) The permanent data table beginning memory address has all Os for the low-order eight bits: 



DCI 


TABLE 


LM 




ADC 




XDC 




DCI 


lOBUF 


LM 




XDC 




ST 




XDC 




DS 





BNZ 


LOOP 


LR 


H.DC 


LR 


A,HL 


DCI 


TABLE 


ST 





The table is not more than 256 bytes long, and the displacement to the first free byte is stored in the first byte of the ta- 
ble. Since the table beginning address has Os in the low-order eight bits, the displacement to the first free byte also 
becomes the low-order eight bits of the first free byte address: 



Table beginning address 



Address of first free byte 



pqOO 


rs 














■ 




pqrs 





















pq and rs are hexadecimal digits 



All of the above assumptions are valid — and, depending upon the application, may also be realistic. Removing any of 
the above assumptions will make the FB program longer, by removing one of the inherent strengths of the F8 instruc- 
tion set. 



2-38 



THE 3851 PROGRAM STORAGE UNIT (PSU) 



The 3851 PSU has been the principal read-only memory program storage device in small F8 microcomputer 
systems. In addition to providing 1024 bytes of read-only memory, the 3851 PSU has two 8-bit I/O ports, a pro- 
grammable timer, and interrupt logic. 

The 3851 PSU can also be used in non-F8 microcomputer systems. The most important and non-obvious advan- 
tage of including a 3851 PSU in a non-F8 microcomputer system is the fact that 3851 PSU memory will lie outside of 
the microcomputer address space. This is because the 3851 PSU relies on its ov\/n memory addressing logic, which ex- 
ists independent of and parallel to any other memory addressing logic. 

Figure 2-7 illustrates functions provided by the 3851 PSU. Device pins and signals are given in Figure 2-8. Pins and sig- 
nals which are unique to the 3851 PSU are described as part of the general 3851 PSU discussion. 



o 

< 
o 

< 

@ 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Interrupt Priority 
Arbitration 



Bus Interface 
Logic 



L 



Accumulator 
RegisteKs) 



Data Counter<s) 



Stack Pointer 



Program Counter 



Direct Memory 

Access Control 

Logic 



W 



System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 

Interface Logic 



I/O Ports 
Interface Logic 



Read Only 
Memory 



I 



I 



RAM Addressing 

and 

Interface Logic 



I/O Ports 



Read/Write 
Memory 



Figure 2-7. Logic of the.Fairchild F8 3851, 3856 and 3857 Programmable Storage Unit 



2-39 




I/O BO 



Pin Name 



I/O AO - I/O A7 
I/O BO - I/O B7 
DBO - DB7 
ROMCO - R0MC4 
^, WRIT E 
EXT IN T 
PRI IN 



PRI OUT 
INT REG 



DBDR 

^SS' VdD' Vqg 



Description 

I/O Port A 
I/O Port B 
Data Bus 
Control Lines 
Clock Lines 
External Interrupt 
Priority In 
Priority Out 
Interrupt Request 
Data Bus Drive 
Power Supply Lines 



Type 

Input/Output 

Input/Output 

Tristate, Bidirectional 

Input 

Input 

Input 

Input 

Output 

Output 

Output 

Input 



Figure 2-8. 3851 PSD Signals and Pin Assignments 

THE 3851 PSU READ-ONLY MEMORY 

Every 3851 PSU has 1024 bytes of read-only memory, pj^s memory addressing logic. The read-only memory 
must be defined when the chip is created. 

3851 PSU memory addressing logic consists of a Program Counter (PCO), a Data Counter (DCO), and a Stack 
register (PCI), which is in fact a buffer for the Program Counter. 



There is also a 6-bit page select mask, which must be specified when the chip is created; the PSU 
page select represents the high-order six bits of the memory address for all ROM bytes of the ADDRESS 
PSU. As such, the page select defines the PSU's address space. SPACE 

When a ROMC state output by the 3850 CPU, and received by the 3851 PSU, identifies a memory 
reference operation, the ROMC state also identifies whether the memory address is to be found in PCO or in DCO. In 
response to this ROMC state, PSU memory addressing logic will compare its 6-bit page select mask with the high-order 
six bits of the specified Address register's contents: 



15 14 13 12 n 10 9 8 



|x|x|x|x|x|x 



7 6 5 4 



3 2 



1 Bit No. 
j j PCO or DCO 



I I 

|y|y|y|y|y|y| Page Select Mask 



2-40 



If there is coincidence, the 3851 PSU will respond to the memory reference operation: if there is no coincidence, the 
3851 PSU addressing logic modifies the contents of Address registers, as might be required by the ROMC state, but it 
does not respond to the actual memory reference instruction. 



3851 PSU INPUT/OUTPUT LOGIC 

Every 3851 PSU has four I/O port addresses assigned to it. These four I/O ports have addresses which are 
specified via a 6-bit I/O port address mask, which you must define when you order a 3851 PSU. This mask is in- 
terpreted as the 6 high-order bits of an 8-bit I/O port address. These are the four addressable I/O ports: 

I/O port address mask: XXXXXX 

XXXXXXOO I/O Port A 

XXXXXX01 I/O Port B 

XXXXXX10 Interrupt control port 

XXXXXX1 1 Programmable Timer register 

Suppose the 6-bit I/O port mask is specified as 000011 2. I/O Ports OCig- ODig, OEis andOFis will then be selected. 

An I/O port mask of 000000 is illegal, since I/O port addresses and 1 are reserved for the two 3850 CPU I/O ports. 

The two 8-bit I/O ports of a 3851 PSU are identical to the 3850 CPU I/O ports which we have already described, 
except for one detail: there are three optional I/O port pin logic configurations available with a 3851 PSU. 

The first option is the standard configuration which we described for the 3850 CPU I/O port pins. 

The second option is open drain configuration, which may be illustrated as follows: 



@ 



I/O Port 



o<-n 



(a) 



Hysteresis Circuit 



Vdd 



r 



Vdd 



_r\ 



(b) 



TTL Input 



r 



(c) 



TTL Output 



This open drain configuration allows you to wire-OR outputs from a number of pins. 



2-41 



The third option is a driver pull-up configuration designed specifically to drive LED displays. This configuration may be 
illustrated as follows: 



I/O Port 



Vdd 

O 



(a) 



(b) 



n 



-| — — vw 



- I 



Vdd 




J 



LED 



(c) 



3851 PSU INTERRUPT LOGIC 

The 3851 PSU can receive external interrupt requests or interrupt requests from its programmable timer. These 
two sets of interrupt logic can be selectively enabled or disabled via a control code written to the interrupt con- 
trol I/O port. This control code is interpreted as follows: 

I/O Port No: X X X X X X 1 



7 6 


5 4 3 2 


- 

1 1 



-Bit No. 



Don't care 
bits 



Control code 

Disable all Interrupts 

1 Enable external interrupt 

Disable timer interrupt 

1 Disable all interrupts 

1 1 Enable timer interrupt 
Disable external Interrupt 



External interrupt request logic may be illustrated as follows: 



From 














external 
logic 






^- INT REQ 


To thfe CPU 






From higher 




A 






To lower 


priority device 
in daisy chain 


PR! IN — 


T 




priority device 
in daisy chain 









An external interrupt request is genera ted by external logic pulling EXT INT low. The interrupt request will be passed 
on to the CPU by outputting INT REQ low, providing these two conditions are met: 

1) External interrupts have been enabled via the interrupt control code (01 in the two low-order bits). 

2) The PRI IN signal is low. 



2-42 



If EXT INT is low and external interrupts are enabled, an interru pt i s being requested: whether or not it is 
acknowledged, PRI OUT is output high. The combination of the PRI IN and PRI OUT signals is designed to implement 
daisy chain interrupt priority logic, which may be illustrated as follows: 



o 

00 

w 
o 

< 

Q 

< 

@ 



INT REQ 



a 



Device 1 



4^ 



PRIIN 



Device 2 



PRI OUT 



PRIIN 



Device 3 



PRI OUT 



PRIIN 



Device 4 



PRI OUT 



PRIIN 



PRI OUT 



EXT INT 



EXT INT 



EXT INT 



EXT INT 



When an active interrupt request occurs at one device, outputting PRI OUT high disables external interrupt logic at all 
lower priority devices in the daisy chain. 

An interval timer interrupt request is generated when the programmable timer I/O port decrements to zero. This 
interrupt request will be acknowledged if programmable timer interrupts have been enabled via the interrupt control 
I/O port (1 1 in the two low-order bits). 

There is no priority arbitration between external interrupts and programmable timer interrupts, since one or the other 
but nGt both can be enabled at any time. 

When the CPU acknowledges an interrupt request, the 3851 PSU responds by saving Program Counter (PCO) 
contents in the Stack register (PCI), then loading an interrupt service routine starting address into the Program 
Counter (PCO). This interrupt service routine starting address is a mask option which you must specify when or- 
dering the 3851 PSU. One bit of the interrupt address vector (it is bit 7) is set aside to identify the interrupt re- 
quest as external or as coming from the programmable timer. This may be illustrated as follows: 



15 14 13 12 11 10 



X X 



■ Bit No. 
Interrupt address vector 



( inserted for programmable timer interrupt 

'1 1 ir 



inserted for external interrupt 
Mask defined address bits 



The actual interrupt response sequence consists of five machine cycles, during which ROMC states are output in the 
order IO15, IC16. 0^16' I^iq. 00i6- Table 2-4 identifies functions performed in response to each ROMC state. 



2-43 





Table 2-5. 


Relationshi 


D Between 


Programmable Timer Contents and Effective Timer Counts 




TIMER 


TIMER 


TIMER 


TIMER 


TIMER 


TIMER 


TIMER 


TIMER 


TIMER 


TIMER 


CONTENTS 


COUNTS 


CONTENTS 


COUNTS 


CONTENTS 


COUNTS 


CONTENTS 


COUNTS 


CONTENTS 


COUNTS 


FE 


254 


F5 


203 


BC 


152 


62 


101 


2A 


50 


FD 


253 


EA 


202 


79 


151 


C4 


100 


55 


49 


FB 


252 


D4 


201 


F2 


150 


88 


99 


AA 


48 


F7 


251 


A9 


200 


E4 


149 


11 


98 


54 


47 


EE 


250 


52 


199 


C9 


148 


22 


97 


A8 


46 


DC 


249 


A4 


198 


93 


147 


44 


96 


50 


45 


B8 


248 


49 


197 


27 


146 


89 


95 


AO 


44 


71 


247 


92 


196 


4E 


145 


13 


94 


41 


43 


E3 


246 


25 


195 


9C 


144 


26 


93 


83 


42 


C7 


245 


4A 


194 


38 


143 


4C 


92 


06 


41 


8E 


244 


94 


193 


70 


142 


98 


91 


OD 


40 


ID 


243 


29 


192 


El 


141 


30 


90 


1A 


39 


3B 


242 


53 


191 


C3 


140 


61 


89 


35 


38 


76 


241 


A6 


190 


86 


139 


C2 


88 


6B 


37 


ED 


240 


4D 


189 


OC 


138 


84 


87 


D7 


36 


DA 


239 . 


9A 


188 


18 


137 


08 


86 


AF 


35 


B4 


238 


34 


187 


31 


136 


10 


85 


5E 


34 


68 


237 


69 


186 . 


63 


135 


20 


84 


BD 


33 


D1 


236 


D3 


185 


C6 


134 


40 


83 


7B 


32 


A3 


235 


A7 


184 


8C 


133 


81 


82 


F6 


31 


47 


234 


4F 


183 


19 


132 


02 


81 


EC 


30 


8F 


233 


9E 


182 


33 


131 


05 


80 


D8 


29 


IF 


232 


3C 


181 


67 


130 


OB 


79 


BO 


28 


3F 


231 


78 


180 


CE 


129 


16 


78 


60 


27 


7E 


230 


FO 


179 


9D 


128 


2C 


77 


CO 


26 


FC 


229 


EO 


178 


3A 


127 


59 


76 


80 


25 


F9 


228 


CI 


177 


74 


126 


B3 


75 


00 


24 


F3 


227 


82 


176 


E9 


125 


66 


74 


01 


23 


E6 


226 


04 


175 


D2 


124 


CC 


73 


03 


22 


CD 


225 


09 


174 


A5 


123 


99 


72 


07 


21 


9B 


224 


12 


173 


4B 


122 


32 


71 


OF 


20 


36 


223 


24 


172 


96 


121 


65 


70 


IE 


19 


6D 


222 


48 


171 


2D 


120 


CA 


69 


3D 


18 


DB 


221 


90 


170 


5B 


119 


95 


68 


7A 


17 


B6 


220 


21 


169 


B7 


118 


2B 


67 


F4 


16 


6C 


219 


42 


168 


6E 


117 


57 


66 


E8 


15 


DS 


218 


85 


167 


DD 


116 


AE 


65 


DO 


14 


B2 


217 


OA 


166 


BA 


115 


5C 


64 


A1 


13 


64 


216 


14 


165 


75 


114 


B9 


63 


43 


12 


C8 


215 


28 


164 


EB 


113 


73 


62 


87 


11 


91 


214 


51 


163 


D6 


112 


E7 


61 , 


OE 


10 


23 


213 


A2 


162 


AD 


111 


CF 


60 


1C 


9 


46 


212 


45 


161 


5A 


110 


9F 


59 


39 


8 


8D 


211 


8B 


160 


B5 


109 


3E 


58 


72 


7 


IB 


210 


17 


159 


6A 


108 


7C 


57 


E5 


6 


37 


209 


2E 


158 


D5 


107 


~ F8 


56 


CB 


5 


6F 


208 


5D 


157 


AB 


106 


F1 


55 


97 


4 


DF 


207 


BB 


156 


56 


105 


E2 


54 


2F 


3 


BE 


206 


77 


155 


AC 


104 


C5 


53 


5F 


2 


7D 


205 


EF 


154 


58 


103 


8A 


52 


BF 


1 


FA 


204 


DE 


153 


B1 


102 


15 


51 


7F 






Timer counts are decimal numbers 
Timer contents are hexadecimal numbers 



2-44 



3851 PSU PROGRAMMABLE TIMER LOGIC 

The 3851 PSU has a single programmable timer which is addressed as the fourth I/O port (XXXXXX112). This 
timer is free running unless it contains the value FP15. The value FF^s stops the timer. 

The interval timer is a polynomial shift register. Table 2-6 gives the correlation between timer counts and timer 
register contents. 

H The programmable timer decrements once every 31 clock periods. Using a 500 nanosecond clock, therefore, the timer 

EC register will decrement once every 15.5 microseconds. 

o 

c In order to generate any specific time interval, you must load an initial value into the programmable timer register by 

o outputtirig the appropriate timer contents to the programmable timer I/O port address. For example, in order to have an 

S initial value of 1 0O1 q. you must load the programmable timer I/O port with the value C4-\q. Loading the programmable 

V) timer with the initial value 28i6 will generate an initial count of 164io- These correlations can be read off Table 2-5. 

< Once the programmable timer times out, it reloads the value FEi q, representing 254i q counts, and starts to decrement 

g again. 

^ 3851 PSU DATA TRANSFER TIMING 

<^ When data is Input to the 3851 PSU from the Data Bus, no control signals are needed since the ROMC state sig- 

z nals identify the presence of data on the Data Bus. When data is output by the 3851 PSU, however, the control 

o output DBDR is low. Timing may be illustrated as follows: 

m 

w 

o 

< 

< 
@ 



WRITE 




\__ri_j 



ROMC' 
DATA OUT ■ 



i 



DBDR 





The purpose of the low DBDR signal is to prevent Data Bus contentions from ever arising. This is also a very useful sig- 
nal in non-F8 microcomputer systems that include a 3851 PSU, since it can be used as a data read strobe. . 

USING THE 3851 PSU IN N0N-F8 CONFIGURATIONS 

The 3851 PSU is easily included in non-F8 microcomputer configurations. The trick is to generate ROIVIC states 
as memory addresses. A ROMC state of 1C idles the 3851 PSU. Appropriate logic is illustrated in Figure 2-9. 

Let us consider some examples. For simplicity, we will use 8080A assembly language mnemonics and assuririe that the 
3851 PSU is selected by addresses FFED-|6 through FFFFiS' This is how data input and data output via 3851 RSU I/O 
ports could be implemented, in conjunction with the logic of Figure 2-9: , ' . 

F8 Instructions ROMC States 8080A Instructions 

IN PORT 03 MVI A,PORT 

IB STA 0FFE3H 

00 LDA OFFFBH 

OUT PORT 



03 


MVI 


A.PORT 


1A 


LXI 


OFFFAH 




MVI 


B.DATA 




STA 


0FFE3H 




MOV 


M.B. 



2-45 



SELECT 
LOGIC 



-•k.AO 



-A4 



CLOCK 

DERIVATIVE 

LOGIC 



2 IN 
1 OUT 
SELECT 



111002 



-^-fc. 



•A5 

.A15 
•DO 



■D7 



INT REQ 

■^ CLOCK 
-•^SYNC 



DBO — DB7 



WRITE 
ROMC 
R0MC4 



3851 
PSU 



DBDR-^h 



TTT 



I/O AO - I/O A7 



I/O BO - I/O B7 



Figure 2-9. Conceptual Logic to Include a 3851 PSU in a Non-F8 Microcomputer System 

Possibly the most useful application for a 3851 PSU in some other microcomputer system would be to imple- 
ment lookup tables. The 1024 bytes of read-only memory could store data tables of that size. The Program Counter 
and Data Counter are active Address registers which can be used to identify the location which must be looked up. 

By way of illustration, consider a decimal multiplication table look-up program. 100 bytes of read-only memory could 
be set aside to store the product of any two single decimal digits. This may be illustrated as follows: 



Memory location: 
Contents: 



00—09 10 11 12—19 20 21 22—29 30 31 etc. 
00—00 00 01 02—09 00 02 04—1 8 00 03 etc. 



Now, in order to compute any decimal multiplication, the two decimal digits are loaded into the eight low-order Data 
Counter bits; the contents of the memory location addressed by the Data Counter are then read. Again assuming that 
the 3851 PSU is selected by memory addresses FFED-ig through FFFFig. and using 8080A assembly language 
mnemonics in conjunction with Figure 2-9, appropriate instructions may be illustrated as follows: 



ROMC States 


8080A In 


structions 


19 






02 


MVI 


46H 




STA 


0FFF9H 




LDA 


0FFE2H 



These instructions seek 4x6; 24 will be returned to the Accumulator. 

These are just some conceptual examples of how the 3851 PSU can be used in non-F8 configurations. Clearly, the 
specific microprocessor being used to drive the 3851 PSU will have a significant influence on the exact interface used 
and the 3851 logic capabilities which are or are not accessible. 



2-46 



THE 3861 AND 3871 PARALLEL I/O (PIO) DEVICES 



o 

ca 

o 

< 

Q 

< 

@ 



The 3861 PIO contains the I/O ports, programmable timer, and interrupt logic of the 3851 PSU. This device con- 
tains no memory; it is otherwise identjpal to the 3861 PSU. Figure 2-8 provides 3861 PIO signals and pin assign- 
ments. 

The 3871 has the I/O ports, timer/counter and interrupt logic of the 3870 single-chip microcomputer. 3871 PIO 
signals and pin assignment^ are identical to the 3861 PSU illustrated in Figure 2-8, with the exception that the 
3870 STROBE signal associated with I/O Port 4 is output at pin 12. 

THE 3856 AlSfP 3857 16K PROGRAMMABLE 
STORAGE UNITS (16K PSU) 

These two devices are enhancements of and replacements for the 3851 PSU which we have just described. 

Superficially, Figure 2-7 represents tf^e logic implemented on all three PSUs — the 3851, 3856 and 3857. Table 2-6 
summarizes the differences between the devices. These are the most significant features of the 3856 and 3857 
PSUs: 

1) RESET sets all I/O port pins and address lines to zero. In the 3851, PSU RESET leaves I/O port pins indeterminate — 
and this has caused problems in many applications. 

2) The interval timers of the 3856 and 3857 PSUs are binary decrementers rather than polynomial shifters — with the 
result that you can read timer contents directly and determine lapsed times. Also, a programmable option allows 
you to measure pulse widths being input to the PSU. 

3) The 3857 PSU uses the 1 6 pins of the two 8-bit I/O ports for 1 6 address lines, so that additional ROM or RAM can 
be interfaced directly to a 3857 PSU -r- v/ithout requiring a 3852 DMl or 3853 SMI, as was the case with the 3851 
PSU. 

4) The 3856 and 3857 PSUs both provide 2K bytes of ROM for program storage; this is twice the program memory 
available on the 3851 PSU. This significantly increases the scope of two-device F8 microcomputer systems. 

Figures 2-10 and 2-1 1 illustrate the pins anc| signals of the 3856 and 3857 16K PSUs respectively. 



Table 2-6. A Summary of Differences Between 3851, 3856 and 3857 PSUs 



FUNCTION 


3851 PSU 


3856 PSU 


3857 PSU 


ROM 


1024 |}ytes 


2048 bytes 


2048 bytes 


I/O Ports 


2x8 bits 


2x8 bits 


None 


Address lines 


None 


None. . 


16 


Interrupt 


Priority in and 


Priority in and 


Priority in only. 


signals 


Priority out 


Priority out 


Must be end of 
daisy chain. 


Interrupt 


Enable timer or 


Enable timer and/or 


Enable timer and/or 


options 


external, but not 
both 


external 


external 


Timer register 


b-Dit Polynomial 


8-bit Count down 


8-bit Count down 


Timer decrement 


31 clock cycles 


2, 8, 32 or 128 


2, 8, 32 or 128 


iritervai 




clock cycles 


clock cycles 


Timer stop/start 


No 


Yes 


Yes 


control 








Timer readback 


No 


Yes 


Yes 


Timer read 


No 


Yes 


Yes 


pulse width? 








RESET zero 


No 


Ye? 


No I/O ports 


I/O ports? 









2-47 




I/O BO 



Pin Name 



I/O AO - I/O A7 
I/O BO - I/O B7 
STROBE 
DBQ-DB7 
ROMCO - R0MC4 
^, WRIT E 
EXT IN T 
PRI IN 
PRI OUT 
INT REG 



DBDR ■ 

VSS' VdD' Vqg 



Description 

I/O Port A 
I/O Port B 

STROBE for I/O Port A 
Data Bus 
Control Lines 
Clock Lines 
External Interrupt 
Priority In 
Priority Out 
Interrupt Request 
Data Bus Drive 
Power Supply Lines 



Type , 

Input/Output 

Input/Output 

Output ' 

Tristate, Bidirectional 

Input 

Input ' 

Input 

Input 

Output 

Output 

Output 



Figure 2-10. 3856 PSU Signals and Pin Assignnnents 



2-48 



o 
m 
<n 
O 

< 
a 
< 

© 



ADDR10 
ADDR09 

Vgg 
Vdd 




RAM WRITE 
ADDR06 



Pin Name 

ADDR00-ADDR15 
CPU READ 
RAM WRITE 
DBO - DB7 
ROMCO - R0MC4 
<&, WRIT E 
EXT IN T 
PRIIN 



INT RE Q 
DBDR 

VsS' VdD' Vgg 



Description 

Address Lines 
Memory Read Enable 
Memory Write Signal 
Data Bus 
Control Lines 
Clock Lines 
External Interrupt 
Priority In 
Interrupt Request 
Data Bus Drive 
Power Supply Lines 



Type 

Output 

Output 

Output 

Tristate, Bidirectional 

Input 

Input 

Input 

Input 

Output 

Output 



Figure 2-1 1. 3857 PSU. Signals and Pin Assignments 

ADDITIONAL F8 SUPPORT DEVICES 

There are three additional F8 support devices: the 3852 Dynamic Memory Interface, the 3853 Static Memory 
Interface, and the 3854 Direct Memory Access device. We are going to summarize these devices rather than 
give complete descriptions, since these devices are infrequently used. 

Only F8 configurations with a substantial amount of memory use these devices — and there are very few such F8 con- 
figurations; however, in every case there are better alternatives. For example, the 3854 Direct Memory Access device 
should not be used to implement direct memory access logic in-non-F8 configurations; the Z80 DMA device is clearly 
superior. In fact, signal peculiarities and timing problems associated with the 3852 DMI, 3853 SMI and 3854 DMA 
devices make them unattractive components in non-F8 configurations. 

If you do need to use the 3852 DMI, the 3853 SMI, or the 3854 DMA devices, you will have to refer to vendor literature, 
since the discussion which follows provides performance summaries only — not product detail. 

THE 3852 DYNAMIC MEMORY INTERFACE (DMI) 

Primarily, this device contains the necessary address generation and memory refresh logic needed to include 
dynamic read/write memory in an F8 system. 

Because of the way in which the F8 microcomputer system is organized, however, memory refresh and direct 
memory access logic are closely related. That is why, in Figure 2-12, a small part of the direct memory access 
control logic is shown as being implemented on the 3852 DMI chip. 



2-49 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Interrupt Priority 
Arbitration 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Bus Interface 
Logic 



Accumulator 
Register<s) 



Data Count©r<s) 



Stack Pointer 



Program Counter 



3852 OMI 




System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



3852 DMI 



ROM Addressing 

and 
Interface Logic 



I/O Ports 
Interface Logic 



RAM Addressing 

and 
lr>terface Logic 



Read Only 
Memory 



I/O Ports 



Read/Write 
Memory 



Figure 2-12. Logic of the Fairchild F8 3852 Dynamic Memory Interface (DMI), and of the 
3854 Direct Memory Access (DMA) Devices 



2-50 



Figure 2-13 illustrates pins and signals of the 3852 DMI. 

Conceptually, memory addressing logic of the 3852 DMI Is very similar to 3857 PSU memory addressing logic: 
there are, however, some differences between the 3862 DMI memory addressing and the 3851 or 3856 PSU: 

1) The 3852 DMI contains two Data Counters, DCOand DC 1. The presence of the auxiliary Data Counter (DC 1) has no 
inrimediate impact on memory addressing logic within the 3852 DMI. However, as we discussed earlier, its pre- 
sence in an F8 system that also includes a 3851 PSU calls for programming caution. 

2) Data and address flows surrounding a 3852 DMI are totally unlike the 3851 or 3856 PSU. In the case of these PSUs, 
addresses are transmitted entirely within the logic of the PSU; the only communication needed between a PSU and 
the CPU is via the eight Data Bus lines of the System Bus. The DMI, on the other hand, generates a 1 6-bit address, 
which it outputs directly to the read/write memory which it is controlling. 

These address pins are equivalent to 3857 PSU address pins — that is, the address pins which a CPU would have, 
if the CPU contained memory addressing logic for the microcomputer system. In other words, the 3852 DMI cre- 
ates the address lines and control signals, which, so far as the read/write memory is concerned, are lacking on the 
F8 System Bus. The F8 System Bus does, however, contain data lines needed by the read/write memory to actually 
transmit data to or from the CPU. 



Data and address flows around the 3852 DMI may be illustrated as follows: 



o 

CQ 
O 

< 
a 
< 



Data lines i 
Control lines 

Data being 
written or read 
flows via this 
connection 



Dynamic 
RAM 



Data being input to, 
or out from address 
registers uses this 
connection 



c 
c 



Address lines 



Control lines 



Master 
Enable 



Address 
Space 
Logic 



z 



System 
Bus 



U V w 



il 



3857 PSU 

or 
3852 DMI 



3) Unlike the 3851, 3856 or 3857 PSU, the 3852 DMI has no on-chip logic to determine address space for read/write 
memory which the DMI is controlling. Address space determination is made by logic in between the DMI and the 
read/write memory. Typically, selected high-order address lines output by the DMI are gated through elementary 
Boolean logic components to create the master enable signal used to strobe attached read/write memory. This is il- 
lustrated above. 



2-51 



Vgg 

* 

WRITE 

MEMIOLE 

CPU SLOT 

RAM WRITE 

CYCLE REQ 

ADDR7 

ADDR6 

ADDR5 

ADDR4 

ADDR3 

ADDR2 

ADDR1 

ADDRO 

DBO 

DB1 

DB2 

DB3 

VSS 

Pin Name 

DB0-DB7 
ADDRO -ADDR 15 
<1>, WRITE 
MEMIDLE 
CYCLE REQ 
CPU SLOT 
CPU READ 
REGDR 
RAM WRITE 
ROMCO - R0MC4 
Vss. Vqd, Vqg 




Description 

Data Bus Lines 
Address Lines 
Clock Lines 
DMA Timing Une 
RAM Timing Line 
Timing Line 
RAM Timing Line 
Register Drive Line 
Write Line 
Control Lines 
Power Lines 



Vdd 

R0MC4 

R0MC3 

R0MC2 

R0MC1 

ROMCO 

CPU READ 

REGDR 

ADDR 15 

ADDR 14 

ADDR 13 

ADDR12 

ADDRII 

ADDR10 

ADDR9 

ADDR8 

DB7 

DB6 

DB5 

DB4 



Type 

Tristate, Bidirectional 
Tristate, Output 
Input 
Output 
Output 
Input/Output 
Output 
Input/Output 
Tristate, Output 
Input- 
Input 



Figure 2-13. 3852 DMI Signals and Pin Assignments 



The process of refreshing dynamic memory and implementing direct memory access are integraiiy related in an 
F8 system. 

The presence of a separate DMI interface device means that there can be a limited overlap 
between a memory reference operation which was Initiated by the CPU and a memory 
reference operation that Is not Initiated by the CPU. 



F8DMI 

MEMORY 

REFRESH 



Two types of memory reference operations are not initiated by the CPU: memory refresh . 
and direct niemory access. 

Let us consi()er how a direct memory access may follow a CPU-initiated memory read operation. These are the 
events which occur: 

1) Upon receiving apt appropriate ROMC state from the CPU, the 3852 DM! outputs a 16-bit memory address, 
together' vyjth a read strobe; these outputs from the 3852 DMI are received by read/write memory. 

2) Read/write memory responds by placing data directly on the Data Bus. The data must remain stable on the Data 
Bus until the CPU has had time to read the data. 



2-52 



While data is stable on the Data Bus, DMA logic may apply a new mennorY address to 
read/write memory. Following the arrival of address and control signals at read/write memory, 
there is a fixed time delay before read/write memory responds by placing data on the Data 
Bus. This time delay can overlap with time when prior data must be stable on the Data Bus. 
This may be illustrated as follows: 



F8 DIRECT 

MEMORY 

ACCESS 



Address Bus 



\/ Memory \/ \/ DMA SJ 

^ Refresh Address ^ ^^^ Address ^ 



Data Bus ■ 



Data stable \/ \/" 

to CPU /iVVv 



DMA 
Data Stable 



-^ overlap \^- 



^ DMI logic outputs control signals which identify the way in which each memory access period is being used: 

g there are three possibilities: 

w 1) Memory is communicating with the F8 System Bus. 

2 2) Memory is not communicating with the System Bus, but since it is dynamic memory it is being refreshed. 

Q 3) Memory is not communicating with the System Bus and is available for external access. 

< 

(g) Cases 2 or 3 above may follow case 1 in separate memory access periods of the same instruction cycle. 

THE 3854 DIRECT MEMORY ACCESS (DMA) DEVICE 

This device receives memory access period identification signals output by the 3852 DMI. Based on the direct 
memory access requirements specified by the currently executing program, the DMA device accesses 
read/write memory, during available memory access periods, as defined by the 3852 DMI. Figure 2-14 illustr- 
ates 3854 DMA pins and signals. 

These are the variables which must be specified for a direct memory access operation: 

1) The beginning address for the memory buffer into which data must be written, or out of which data must be read. 

2) The length of the buffer. 

3) Whether data is to be written or read out of the buffer. 

Once a direct memory access operation has been initiated, it proceeds in parallel with other events occurring 
within the F8 microcomputer system, using memory access periods which are defined by the 3852 DMI as 
available for direct memory access. In other words, direct memory access operations in no way slow down program 
execution that may be occurring in parallel. 

DMA data transfer may be high-speed or low-speed. Low-speed DMA transfer means that each DMA access is 
enabled by a signal from the external device, stating that it is ready to transmit or receive data. High-speed access 
assumes that the external device will always be ready to transmit or receive data; therefore, every single available 
memory access period is utilized. 

As a direct memory access operation proceeds, after each access the memory address is incremented and the buffer 
length is decremented. Memory address, buffer length and DMA controls are stored in buffers which the CPU accesses 
as though they were I/O ports. The contents of these I/O ports may be written into, or read at any time. This means 
that the F8 DMA system allows total flexibility for every type of programmable DMA operation; these include 
such things as stopping a DMA operation temporarily, or interrogating a DMA operation to determine how far it has 
progressed. 

Indefinite DMA transfer may also be specified. In this case, no buffer length is given; rather, the DMA operation will 
proceed until stopped. 



2-53 




XFER REQ 

Vgg 
Vdd 

ADDR8 

ADDR9 

ADDR10 

ADDR11 

ADDR12 

ADDR13 

ADDR14 

ADDR15 

PI 

P2 

DB7 

DB6 

DBS 

DB4 



Pin Name 

DBO - DB7 

ADDR0-ADDR15 

*, WRITE 

LOAD REG/READ REG 

PI, P2 

MEMIDLE 

XFER REQ 

ENABLE, DIRECTION 

DWS, XFER 

STROBE 

VsS' VdD' Vgg 



Description 

Data Bus Lines 
Address Lines 
Clock Lines 

Registers Load/Read Line 
Port Address Select 
Memory Idle Line 
Transfer Request Line 
Control Status Lines 
DMA Write Slot, Transfer 
Output Strobe Line 
Power Lines 



Type 

Tristate, Bidirectional 

Tristate, Output 

Input 

Input 

Input 

Input 

Input 

Output 

Output 

Output 



Figure 2-14. 3854 DMA Signals and Pin Assignnnents 



THE 3853 STATIC MEMORY INTERFACE (SMI) 

The 3853 SMI provides interface logic for static read/write memory, that is, for memory which does not need to 
be refreshed. Logic implemented on this device is illustrated in Figure 2-1 5. and is a simple combination of func- 
tions which have already been described for the 3851 PSU and for the 3852 DMI. Figure 2-16 illustrates 3853 
SMI pins and signals. 

The description of memory interface logic which was given for the 3852 DMI applies also for the 3853 SMI. The 
3853 SMI, however, does not identify memory access periods, and cannot be used to implement direct memory 
access. 

Because the 3853 SMI does not have memory refresh or direct memory access support logic, there is unused real estate 
on the SMI chip. The real estate is used to implement a programmable timer and interrupt processing logic, as de- 
scribed for the 3851 PSU. There are, however, two small differences between interrupt logic as implemented on the 
PSU and the SMI devices; they are: 

1) The 3853 SMI interrupt address vector is not a permanent mask option as it is on the PSU; rather, it is programma- 
ble. 

2) The 3853 SMI has no priority output line, which means that in a daisy chain interrupt configuration it must have 
lowest priority; that is, it must come at the end of the daisy chain. 



2-54 



Clock Logic 



O 

03 
» 
O 

< 

Q 

< 

@ 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Interrupt Priority 
Arbitration 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Bus Interface 
Logic 



Accumulator 
Register<s) 



Data Counters) 



Stack Pointer 



Program Counter 



Systenr Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 

Interface Logic 



I 



I/O Ports 
Interface Logic 



Read Only 
Memory 



I 



I/O Ports 



Direct Memory 

Access Control 

Logic 



RAM Addressing 

and 
Interface Logic 



Read/Write 
Memory 



Figure 2-15. Logic of the F8 3853 Static Memory Interface (SMI) Device 



2-55 




EXT INT 

ADDR7 

ADDR6 

ADDR5 

ADDR4 

ADDR3 

ADDR2 

ADDR1 

ADDRO 

DBO 

DB1 

DB2 

DB3 

vss 



Pin Name 

DBO - DB7 
ADDRO -ADDR 15 
^, WRIT E 
INT RE Q 
PRIIN 

RAM WR ITE 
EXT INT 
REGDR 
CPU READ 
ROMCO - R0MC4 
VSS' VdD' Vqg 



Description 

Data Bus Lines 
Address Lines 
Clock Lines 
Interrupt Request 
Priority In Line 
Write Line 

External Interrupt Line 
Register Drive Line 
CPU Read Line 
Control Lines 
Power Supply Lines 



Type 

Bidirectional 

Output 

Input 

Output 

Input 

Output 

Input 

Input/Output 

Output 

Input 



Figure 2-16. 3853 SMI Signals and Pin Assignments 



2-56 



^- 



DATA SHEETS 

This section contains specific electrical and timing data for the following devices: 

• 3870 One-Chip Microcomputer 
. 3850 CPU 
. 3851 PSU 



< . 3852 DMI 

o . 3853 SMI 

g . 3854 DMA 

o . 3856 2K RSU 



3861 PIO 



o 
m 
(/) 
O 

< 
a 
< 

@ 



2-D1 



3870 

ELECTRICAL SPECIFICATIONS 
ABSOLUTE MAXIMUM RATINGS* 



Temperature Under Bias 

Storage Temperature . . . 

Voltage On Any Pin With Respect To Ground 
Power Dissipation . 



0°C to 70°C 

-6?Cto+150°C 
..-1.0V to + 7V 
LOW 



DC CHARACTERISTICS 

Ta = 0°C to 70°C, Vcc = 5V ± 1 0% 



SYMBOL 


PARAMETER 


MIN 


MAX 


UNIT 


TEST CONDITIONS 


'CO 


Power Supply Current 




TBD 


mA 


Outputs Open 


pd 


Power Dissipation 




TBD 


mW 


Outputs Open 


VlHEX 


External Clock 
Input High Level 


2.4 


5,8 


V 




ViLHEX 


External Clock 
Input Low Level 


-0.3 


0.6 


V 




IjHEX 


External Clock 
Input High Current 




100 


juA 


V|HEX=2.4V 


IlLEX 


External Clock 
Input Low Current 




-100 


JuA 


V|LEX=0.6V 


V|H 


Input High Level 


2.0 


5.8 


V 




V|L 


Input Low Level 


-0.3 


0.8 


V 




l|H 


Input High Current 
(except open drain and 
direct drive I/O ports) 




100 


mA 


V|H=2;4V 
internal pull-up 


l|L 


Input Low Current 
(except open drain and 
direct drive ports) 




-1.6 


mA 


V|L=0.4V 


ILOD 


Leakage Current 
(open drain ports) 




10 


mA 


Pull -down 
■ device off 


'OH 


Output High Current 
(except open drain and 
direct drive ports) 


-100 




mA 


VoH= 2.4V 


lOHDD 


Output Drive Current 
(direct drive ports) 


-1.5 


-8 


mA 


VOH=0.7V 
to 1.5V 


lOL 


Output Low Current 


1.8 




mA 


V0L= 0.4 V 


lOHS 


OutDut Hiqh Current 
(STROBE Output) 


-300 




/iA 


VoH= 2.4V 


lOLS 


OutDUt Low Current 
(STROBE Output) 


5.0 




mA 


VOL=0.4V 



'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is 
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 

Data sheets on pages 2-D2 through 2-D5 reprinted by permission of Mostel< Corporation. 



2-D2 



3870 

AC CHARACTERISTICS 

Ta = Ot to yOt, Vcc = +5V ± 10% 



o 
a 
tn 
o 

< 

Q 
< 



SIGNAL 


SYMBOL 


PARAMETER 


MIN 


MAX 


UNIT 


COMMENTS 




tO(XTL) 


Time Base Period, Crystal Mode 


250 


1000 


ns 


4MHz-1MHz 




tO(LC) 


Time Base Period, LC Mode 


250 


1000 


ns 


4MHZ-1MHZ 


XTL1 


tO(RC) 


Time Base Period, RC Mode 


250 


2000 


ns 


4MHz-500kHz 


XTL2 


tO(lNT) 


Time Base Period, Internal Mode 


250 


590 


ns 


4MHz-1.7MHz 




tO(EX) 


Time Base Period, External Mode 


250 


2500 


ns 


4MHz-400kHz 




tEX(H) 


External Clock Pulse Width, High 


90 


2000 


ns 






tEX(L) 


External Clock Pulse Width, Low 


90 


2000 


ns 




* 


t * 


Internal *C!ock Period 


2t0 typ. 


ns 


0.5 MS@4MHz 
ext. time base 




t|/0-S 




3t*-1000min. 
3t ^+250 max. 


ns 




STROBE 


Port Output to STROBE Delay 


Note 1 




tSL 




8ta>-250min, 
121* +250 max. 


ns 






STROBE Pulse Width, Low 






tRH 




6t4>+750min. 


ns 




RESET 


RESET Hold Time, Low 




EXT|NT 


tEH 


EXT INT Hold Time, Active 
State 


6t*+750min. 


ns 


Note 2 



1. Load is 50pF plus 1 standard TTL input. 

2. Specification is applicable when the timer is in the Interval Timer Mode. 

See "Timer Characteristics" for EXT INT requirements when in the Pulse Width ' 
Measurement Mode or the Event Counter Mode. 

3. The AC Ti'ming Diagrams are given in Figure 5. 



CAPACITANCE 
TA = 25t:, f=2MHz 



SYMBOL 


PARAMETER 


MIN 


MAX 


UNIT 


TEST CONDITION 








7 


pF 




C|N 


Input Capacitance: I/O Ports, RESET, EXT INT 


Unmeasured pins 
returned toGND 


CXTL 


Input Capacitance: XTL 1, XTL 2 


18 


23 


pF 





2-D3 



3870 

TIMER CHARACTERISTICS 

Definitions: 

Error = Indicated tinne value - actual time value 

tpsc = t4>x Prescale Value 

Interval Timer Mode: 

Single interval error, free running (Note 3) ±6t4> 

Cumulative interval error, free running (Note 3) 

Error between two Timer reads (Note 2) .;......;... ±(tpsc + t$) 

Start Timer to stop Timer error (Notes 1,4) . +t<i> to —(tpsc +t<t>) 

Start Timer to read Timer error (Notes 1,2) -5t* to -(tpsc + 7t$) 

Start Timer to interrupt request error (Notes 1,3). — 2t$ to — 8t$ 

Load Timer to stop Timer error (Note 1) +t$ to — (tpsc + 2t4>) 

Load Timer to read Timer error (Notes 1,2) .— Bt^J to — (tpsc + 8t4>) 

Load Timer to interrupt request error (Notes 1,3) — 2t4> to — 9t4> 

Pulse Width Measurement Mode: 

Measurement accuracy (Note 4) . . +t <I)to —(tpsc +2t 4>) 

Minimum pulse width of EXT INT pin . .2t<l» 

Event Counter Mode: 

Minimum active time of EXT INT pin. . .2Xfi> 

Minimum inactive time of EXT INT pin 2t4> 



Notes: 



1. All times which entail loading, starting, or stopping the Timer are referenced from the end 
of the last machine cycle of the OUT or OUTS instruction. 

2. All times which entail reading the Timer are referenced from the end of the last rriachine 
cycle of the IN or INS instruction. 

3. All times which entail the generation of an interrupt request are referenced from the start 
of the machine cycle in which the appropriate interrupt request latch is set. Additional 
tinrie may elapse if the interrupt request occurs during a privileged or multicycle instruction. 

4. Error may be cumulative if operation is repetitively performed. 



2-D4 



3870 



to(EX) 



tEX(H) 



External Clock 




Internal <t> Clock _/ \ / \ 7 \ / " 



o 
< 

Q 

< 



I/O Port Output 



STROBE 



Di 



\ 



. ti/o-S 



■* tsL 



/ 



RESET 



\ 



/ 



EXT INT 



r 



ICP BIT 2 



=^ 



ICP BIT 2^1 



7 



Note: All measurements are referenced to Vil max., V|H min., Vql max., or VqH min. 



FIGURES. AC TIMING DIAGRAMS 



2-D5 



3850 CPU 



2.2.2 Electrical Specifications 



Absolute maximum ratings (above which useful 
life may be impaired) 

Vqg +15Vto-0.3V 

Vqd +7V to -0.3V 

RC, XtL>< and XTLY +1 5V to -0.3V ( RC with 

5Kfi series resistor) 

All othe'i- inputs +7V to -0.3V 

Storage temperature -55°C to +150°C 

Operating temperature 0°C to +70°C 

Note: All voltages with respect to Vcg. 

DC Characteristics: Vgg = OV, Vqq = +5V ± 5%, 
Vgg = +12V±5%,Ta = 0°C 
to +70°C 

SUPPLY CURRENTS 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


TEST 
CONDITIONS 














f = 2MHz, 


"DD 


Vob fcurrent 




45 


75 


mA 


Outputs 
unloaded 
f -2MHz, 


>GG 


Vqg Current 




12 


30 


mA 


Outputs 
unloaded 



Data sheets on pages 2-D6 through 2-D33 reprinted by permission of Fairchild Camera and Instrument Corporation. 



2-D6 



3850 CPU 



Table 2-3. A Summary of 3850 CPU Signal DC Characteristics 



z 
ce 
o 
m 
w 
o 

S 

< 

Q 
< 

@ 



SIGNAL 


SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


*, WRITE 


VOH 


Output High Voltage 


4.4 


Vdd 


Volts 


Ioh = -50mA 




Vol 


Output Low Voltage 


vss 


0.4 


Volts 


l0L= 1.6 mA 




VOH 


Output High Voltage 


2.9 




Volts 


IqH = -100mA 


XTLY 


V|H 


Input High Voltage 


4.5 


Vgg 


Volts 






V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






l|H 


Input High Current 


5 


50 


)uA 


V|N = Vdd 




l|L 


Input Low Current 


-10 


-120 


mA 


V|N = Vss 


ROMCO 


VOH 


Output High Voltage 


3.9 


Vdd 


Volts 


IOH = -100juA 


: 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L= l-S mA 


R0MC4 














DBO 


V|H 


Input High Voltage 


2.9 


Vdd 


Volts 




; 


V|L 


Input Low Voltage 


Vss 


0.8 


Volts 




DB7 


VoH 


Output High Voltage 


3.9 


Vdd 


Volts 


Ioh = -ioomA 




Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L= 1-6 mA 




'IH 


Input High Current 




3 


/iA 


V||sj = 7V 3-State mode 




'IL 


Input Low Current 


' 


-3 


mA 


V|N = Vss, 3-State mode 


l/OO 


VOH 


Output High Voltage 


3.9 


Vdd 


Volts 


IOH = -30mA 


: 


VOH 


Output High Voltage 


2.9 


Vdd 


Volts 


Ioh = -150a'A 


I/O 17 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L= 1.6 mA 




V|H 


Input High Voltage (1) 


2.9 


Vdd 


Volts 


Internal pull-up to Vqq 




V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






l|L 


Input Low Current 




-1.6 


mA 


V|N = 0.4V(2) 




V|H 


Input High Voltage 


3.5 


Vdd 


Volts 


Internal pull-up to V^p 


EXT RES 




V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






l|L 


Input Low Current 


-0.1 


-1.0 


mA 


V|N = Vss 




VjH 


Input High Voltage 


3.5 


Vdd 


Volts 


Internal pull-up to Vqd 


INTREQ 




V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






l|L 


Input Low Current 


-0.1 


-1.0 


nnA 


V|N = Vss 




VoH 


Output High Voltage 


3.9 


Vdd 


Volts 


IOH = -10mA 


RJB 


VOH 


Output High Voltage 


2.9 


Vdd 


Volts 


IOH = -100)uA 




Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L= 100 /iA 



(1) Hysteresis input circuit provides additional 0.3V noise immunity while internal pull-up provides TTL 
compatability. 

(2) Measured while F8 port is outputting a high level. 
Note: 

Positive current is defined as conventional current flowing into the pin referenced. 

(3) Guaranteed but not tested. 



2-D7 



3850 CPU Table 2-4. A Summary of 3850 CPU Signal AC Characteristics 

AC Characteristics: Vgs = OV, V^q = +5V ± 5%, Vqq = +12V ±5%, T^ = 0°C to +70°e 
Symbols in this table are used by all figures in Section 2. 



SYMBOL 


PARAMETER 


MIIM. 


TYP. 


MAX. 


UNITS 


TEST CONDITIONS 


Px* 


External input Period 


0.5 




10 


/iS 




PW/ 


External Pulse Width 


200 




Px-200 


nS 


tp tf <30nS 


txi 


Ext. to <^ - to - Delay 






250 


nS 


CL=100pf 


tX2 


Ext. to<l' + to + Delay 






250 


nS 


CL=100pf 


pa> 


<!> t'eriod 


0.5 




10 


US 




PWi 


<^ Pulse Width 


180 




P'l'-180 


nS 


tf, tf = 50hS;CL= 100 pf 


tdi 


4j to WRITE + Delay 




150 


250 


nS 


Cl= 100 pf 


td2 


i|> to WRITE -Delay 




150 


250 


nS 


CL=100pf 


PW2 


WRITE Pulse Width 


P<1>-100 




P<I> , 


nS 


t^; tf = 50 nS typ; C|_ = 100 pf 


PWs 


WRITE Period; Short 




4P<1> 








PWl 


WRITE Period; Long 




6P<I> 








,td3 


WRITE to ROMC Delay 


80 


300 


550 


nS 


C|_= 100 pf 


td4* 

td5 

^sx' 


WRITE to ICB Delay 


1.0 




350 
430(2) 


nS 
nS 
MS 


C|_ = 50 pf 
Ci_= 100 pf 
Cl = 20 pf 


WRITE to INT REQ Delay 


EXT RES set-up time 


^su' 


I/O set-up tinne 


300 






nS 




th* 


I/O hold tinne 


50 






nS 




to* 


I/O Output Delay 


■ 




2.5 


juS 


Ci_ = 50 pf 


tdbi* 


WRITE to Data Bus Stable 




0.6 


1.3 


/js 


C|_=100pf 


tdb2 


WRITE to Data Bus Stable 


2P<1> 




2P<I'-i-1.0 


MS, 


Ci_=100pf 


tdb3* 


Data Bus Set-up 


200 






nS. 




tdb4* 


Data Bus Set-up 


500 






nS 




tdbg 


Data Bijs Set-up 


500 






nS 




tdbg* 


Data Bus Set-up 


500 






nS 





'The parameters which are starred in the table above represent those which are most frequently of 
importance when interfacing to an F8 system. These encompass 1/0 timing, external timing generation 
and possible external RAM timing. The remaining parameters are typically those that are only relevant 
between F8 chips and not normally of concern to the user. 

(1 ) Input and output capacitance is 3 to 5 pf typical on all pins except Vqq, Mqq, and V35. 



(2) If INTREQ isbeing supplied asynchronously, it can be pulled down at any time except 
during a fetch cycle that has been preceded by a non-priviledged instruction. In that 
case INTREQ must go down according to the requirements of td5. 



2-D8 



o 

CD 
0) 

o 

S 

< 

Q 
< 



3850 CPU 

PW 
XTLY 



WRITE 




U-PW2-J i^ 



zrmx_ ^rrrx. 



PARAMETERS ARE DESCRIBED IN TABLE 2-4 
Figure 2-8. Timing Signal Specifications 



WRITE 



ROMC 




SYMBOLS ARE DEFINED BY TABLE 2-4 
Figure 2-9. ROMC Signals Output by 3850 CPU 



2-D9 



3850 CPU 



XTLY 



WRITE 



ROMC 




DATA- 
BUS . 



^ TRUE ROMC STATeT 

V' OP CODE FOR NEXT INSTRUCTION" 



ONE CYCLE OF A SINGLE CYCLE | NEXT 

INSTRUCTION, OR LAST CYCLE OF A , INSTRUCTION 
MULTICYCLE INSTRUCTION ' 



Symbols are defined in Table 2-4 
Figure 2-10A. A Short Cycle Instruction Fetch 



XTLY 




^^_i_j i^j pw^h" 



Ly — K. 

L_PW2-^ U 



WRITE 



ROMC 



-PW, 



X 



X 



TRUE ROMC STATE 



l^e-tdg-^ 



V 



^*-tdb3-J 



ONE CYCLE OF THE SINGLE, LONG 

CYCLE DS INSTRUCTION 

(DECREMENT SCRATCHPAD) 



t 



OP CODE FOR NEXT 



INSTRUCTION 

I 

NEXT 
INSTRUCTION 



Symbols are defined in Table 2-4 
Figure 2-1 OB. A Long Cycle Instruction Fetch (During DS Only) 



2-D10 



3850 CPU 



.PWi 



o 

CQ 
W 
O 

< 

Q 

< 

@ 



(WRITE) 

DATA BUS (1) 
DATA BUS (1) 

DATA BUS 

DATA BUS 
DATA BUS 



-PWs- 



I 
I 



jr 



K 



X 



-tdbi 



-tdbo- 



S 



STABLE 



(HIGH IMPEDANCE) 



XE 



.tdb2- 



STABLE 



" X stable" 



- tdb4 
tdbg- 



" X DATA STABLE 



" X DATA STABLE 



tdbg 



:^ 



1 . Timing for CPU outputting data onto the data bus. 

Delay tdb-| is the delay when data is coming from the accumulator. 

Delay tdb2 is the delay when data is coming from the scratchpad (or from a memory device). 

Delay tdbg is the delay for the CPU to stop driving the data bus. 

2. There are four possible cases when inputting data to the CPU, via the data bus lines: they depend on the data path and the 
destination in the CPU, as follows: 

tdb3; Destination — IR (instruction Fetch) — See Figure 2-10 for details. 
tdb4; Destination — Accumulator (with ALU operation — AM) 
tdb5; Destination - Scratchpad (LR K,P etc.) 
tdbg; Destination — Accumulator (no ALU operation — LM) 

In each case a stable data hold time of 50 nS from the WRITE refrence point is required. 

Symbols are defined in Table 2-4 



Figure 2-11. Memory Reference Timing 



2-D11 



3850 CPU 



(WRITE) 



-/ ^ 



I/O (1) 



I/O (2) 



■PWs- 



DATA MAY CHANGE 



X 



DATA FROM OLD OUTS 



X 



y K. 



STABLE 



NEW DATA 



X 



.th 



DATA MAY CHANGE 



(1) This represents the timing for data at the I/O pin during the execution of the INS instruction, i.e., the 
CPU is inputting. 

(2) This represents the timing for data being output by the CPU at the I/O pin. 

Symbols are defined in Table 2-4 
Figure 2-13. Timing for Data Input or Output at I/O Port Pins 



WRITE 



-A k 

|-.-PW2-.^ 



ROMC 



ICB(I) 



INTREQ(2)- 



INTREQ(2)- 
EXT RES 



X 



td, 



^3— H 
.td4_^ 






.PW< 



y N 



-PW, 



TRUE 



X 



X 




(1) ICB will go from a 1 to a following the execution of the El instruction and will go from a to 1 
following either the execution of the D! instruction or the CPU's acknowledgement of an interrupt. 

(2) This is an input to the CPU chip and is generated by a PSU or 3853 iVll chip. The open drain outputs 
of these chips are all wire "ANDed" together on this line with the pull-up being located on the CPU 
chip. For a to 1 transition the delay is measured to 2.QM . 

Symbols are defined in Table 2-4 

Figure 2- 14. Interrupt Signals Timing 



2-012 



3851 PSU 



3.2.5 Electrical Specifications 



Absolute Maximum Ratings (Above which useful 
life may be impaired) 



o 
m 

o 

< 
< 



Vqg +15Vto-0.3V 

Vdd +7Vto-0.3V 

I/O Port Open Drain Option +15y..to -0.3V 

External Interrupt Input -60d'/iA to +225 /liA 

All other inputs & outputs +7V to -0.3\/ 

Storage Tern^erature -55°C to +150°C 

Operating Temperature 0°Cto+7b°C 

Note; All voltages with respect to Vgg. 

DC Characteristics: Vgs = OV, Vpo = +5V ± 5%, 
Vgg=.+12V±5%, 
TA = 0°Cto+70°C 

SUPPLY CURRENTS 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


TEST 
CONDITIONS 


'do 


VqD ^"^^«"' 




28 


60 


mA 


t = 2 MHz, 

Outputs 

Unloaded 


'gg 


V_Q Current 




10 


30 


mA 


f = 2 MHz, 

Outputs 

Unloaded 



2-D13 



3851 PSU Table 3-2. A Summary of 3851 PSU Signal Characteristics 




SIGNAL 


SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS TEST CONDITIONS 


DATA BUS (DB0-DB7) 


V|H 


Input High Voltage 


2.9 


Vdd 


Volts 






V|L 


Input Low Voltage 


Vrs 


0.8 


Volts 






VOH 


Output High Voltage 


3.9 


Vdd 


Volts 


Ioh = -iooma , 




Vol 


Output Low Voltage 


vss 


0.4 


Volts 


l0L= 1-6 mA 




'IH 


Input High Current 




1 


ma 


VjN "^ VqD' 3-State mode 




'OL 


Input Low Current 




-1 


ma 


V|N ^ Vss- 3-State mode 


CLOCK LINES!*, WRITE) 


V|H 


Input High Voltage 


4.0 


Vdd 


Volts 






V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'l 


Leakage Current 




3 


AiA 


V|N = Vdd . 


PRIORITY IN AND CONTROL 


V,H 


Input High Voltage 


3.5 


Vdd 


Volts 




LINES (PR! IN, ROMC0-ROMC4) 


V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






"l 


Leakage Current 




3 


^A 


V|N = Vdd 




VoH 


Output High Voltage 


3.9 


Vdd 


Volts 


IOH = -100/uA 


PRIORITY OUT (PRI OUT) 




Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


Iol=iooa/a 


INTERRUPT REQUEST 


VoH 


Output High Voltage 






Volts 


Open Drain Output (1] 


(INT REG) 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


'OL °^ ^ "^A 




'l 


Leakage Current 




3 


fiA 


V|N=Vdd' 




VoH 


Output High Voltage 








External Pull-up 


DATA BUS DRIVE (DBDR) 




Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L = 2 mA 




'l 


Leakage Current . 




3 


/ja 


ViN = VDD 


EXTERNAL INTERRUPT 


V|H 


Input High Voltage 


3.5 




Volts 




(EXT INT) 


V|L 


Input Low Voltage 




0.8 


Volts 






V|C 


Input Clamp Voltage 




15 


Volts 


l|H=185>A 




'IH 


Input High Current 




10 


liA 


ViN = Vdd 




'IL 


Input Low Current 




-225 


MA 


V,N = 2V 




'IL 


Input Low Current 


-150 


-500 


A/A 


V|N = VSS 


I/O PORT OPTION A 


VoH 


Output High Voltage 


3.9(5) 


Vdd 


Volts 


Ioh = -30mA 


(STANDARD PULL-UP) 


VoH 


Output High Voltage 


2.9 


Vdd 


Volts 


Ioh = -150mA 




Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


i0L=1-6mA 




V|H 


Input High Voltage 


2.9(3) 


Vdd 


Volts 


Internal Pull-up to Vqq [3] 




V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'L 


Leakage Current 




1 


UA 


V|N = Vdq 




>IL 


Input Low Current 




-1.6 


mA 


V|N = 0.4V[4] 


I/O PORT OPTION B 


VoH 


Output High Voltage 








External Pull-up 


(OPEN DRAIN) 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L = 2 mA 




V|H 


Input High Voltage 


2.9(3) 


Vdd 


Volts 


[3] 




V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'IL 

'■ 1 


Leakage Current 




2 


HA 


V|N = -f 12V 



2-D14 



3851 PSU Table 3-2. 


A Summary of 3851 PSU Signal Characteristics (Continued) 


SIGNAL 


SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


I/O IJORT OPTION C (DRIVER 
PULL-UP) 


Vol 


Output High Voltage 
output Low Voltage 


3.75 

vss 


Vdd 

0.4 


Volts 
Volts 


'oh = "1 t'A 
l0L = l-S mA 



Notes: 

1 . Pull-up resistor to Vqq on CPU. 

2. Positive current is defined as conventional current flowing into the pin referenced. 

3. Hysteresis input circuit provides additional 0.3V noise immunity while internal/external puil-up provides TTL compatibility. 

4. Measul^ed while I/O port is outputting a high level. 

5. Guaranteed but not tested. 



z 

EC 

o 

m 

o 

< 

Q 

< 

@ 



Table 3-3. A Summary of 3851 PSU Signal AC Characteristics 
AC Characteristics: Vgs = OV, Vqq = +5V ± 5%, Vqq = +12V ± 5%, T^ = O^C to +70°C 
Symbols in this table are used by all figures in Section 3. 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


TEST 
CONDITIONS 


P« 


4> Period 


0.5 




10 


pS 




PWi 


Pulse Width 


180 




P0-18O 


nS 


tr. tt = 50 nS typ. 


tdi 


<i> to WRITE + Delay 






250 


iiS 


Cl = 100 pf 


td2 


(l> to WRITE-Delay . 






250 


nS 


Cu = 100 pf 


td4 


WRITE to bB Input Delay 






2P0 + 1.0 


^iS 




PW2 


WRITE Pulse Width 


P0-1OO 




P* 


nS 


tr, tt = 50 nS typ. 


PWs 


WRITE Period; Short 




AP4, 








PWl 


WRITE Period; Long 




6P<* 








td3 


WRITE to ROMC Delay 






550 


nS 




td7 


WRITE to DB Output Delay 
WRITE to dbbft — Delay 


2P4> + 100-td2 


2P4> + 200 


2P<> + 850-td2 


nS 


Cl = 100 pf 


tds 


WRITE to DBDR+ Delay 




200 




nS 


Open Drain 


tn 


WRITE to INT REG -Delay 






430 


nS 


Cl = 100 pf [1] 


trz 


WF^ItE to INT REQ + Delay 






430 


nS 


Cl = 100 pf [3] 


tpn 


PRI IN to INT REQ -Delay 




200 




nS 


Cl = 100 pf [2] 


tpdi . 


PRI IN to PRI OUT- Delay 






300 


nS 


Cl = 50 pf 


tpd2 


PRI IN to PRI OUT + Delay 






300 


nS 


Cl = 50 pf 


tpd3 


WRITE to PRI OUT + Delay 






600 


nS 


Cl = 50 pf 


tpd4 


WRITE to PRI OUT — Delay 






600 


nS 


Cl = 50 pf 


tip 


WhiTE Iq Output Stable 






1.0(3} 


;xS 


Cl = $0 pf. Standard 
Pull-up 


tod 


WRITE to Outpiit StatJiQ 






1.0 <3> 


;jS 


Cl = 50 pf, 
RL=12.5Knt0VDD 

plus TTL load 


^p 


WRITE to Output Stable 




2QQ 


400 


nS 


Ct = 50 pf , Drhrer . 
Pull-up 


t$u 


l/d ^etupTime 


W!^i3MMmmM 






^S 




th 


I/O Hold TOT6 


w6MMMMy--y:'M 






nS 




tox 


EXT INT Setup Time 


wMiMimm 






nS 





Notes: 



1. Assume Priority In was enabled (PRI IN = 0) in previous F8 cycle before interrupt is detected in the PSU. 

2. PSU has interrupt pending before priority in is enabled. 



3. Assume pin tied to INT REQ input of the 3850 CPU. 

4. The parameters which are shaded in the table above represent those which are most frequently of importance when 
interfacing to an F8 system. Unshaded parameters are typically those that are relevant only between F8 chips and not 
normally of concern to the usei-. 

5. Input and output capacitance is 3 to 5 pf typical on all pins except Vqq, Vqq, and Vss- 



2-D15 



3851 PSU 




:^^.PW2_J^ 



DATA BUS OUTPUT 



DBDR 
(START OF DATA OUT) 



DBDR 

(END OF DATA 

OUT IN SUBSEQUENT 

CYCLE) 



DATA BUS INPUT 



X 



.td7. 



r 



STABLE 



:x: 



V 



-/In. 



SYMBOLS ARE DEFINED IN TABLE 3-3 
Figure 3-3. 3851 PSU Data Bus Timing 



LONG CYCLE 



STABLE 



STABLE 



WRITE 



_y 



INPUT (1) 



OUTPUT (2) 
(STANDAFtD PULLUP) 



OUTPUT (2) 
(OPEN DRAIN) 



OUTPUT (2) 
(DRIVER PULLUP) 



DATA MAY CHANGE 



X 



^ 



2.9V 



^^^ 



2.9V 



;^^ 



J~~\. 



DATA STABLE 



X 



DATA MAY CHANGE 



STABLE 



STABLE 



SYMBOLS ARE DEFINED IN TABLE 3-3 

1. The set-up and hold times specified are with respect to the end of the second long cycle during execution of the three 
cycle IN or INS instJ-uction. 

2. All delay times are specified with respect to the end of the second long cycle during execution of the three cycle OUT or 
OUTS instruction. 

Figure 3-7. Timing at PSU I/O Ports 



2-D16 



3851 PSU 



o 
u 




z 


ROMC 


(A 
Ul 

5 




8 

V) 

< 


INTREQ 




o3 




Ul 

Z 




o 
ffl 
« 
o 


PRIOUT 


< 

Q 
< 


PRI IN 



@ 




INTREQ 



PRIOUT 



EXT INT 



X 



tpr-j 



tpd-i 



X 



yf 



.tpr2: 



h*-tpd2 



■* h 



> 



NOTE: TIMING MEASUREMENTS ARE MADE AT VALID LOGIC LEVEL OF THE SIGNALS 
REFERENCED UNLESS OTHERWISE NOTED. 

SYMBOLS ARE DEFINED IN TABLE 3-3 



Figure 3-13. Interrupt Logic Signals' Timing 



2-D17 



3852 DMI 


Table 4-2. Summary of 3852 DMI Signal Characteristics 


SIGNAL 


SYMBOL 


PARAMETER 


MIIM. 


MAX. 


UNITS 


TEST CONDITIONS 


DATA BUS 


V|H 


Input High Voltage 


2.9 


vnn 


Volts 




(DB0-DB7) 


V|L 


Input Low Voltage 


VsR 


0.8 


Volts 






VOH 


Output High Voltage 


3.9 


Vdd 


Volts 


Ioh = -iooma 




Vol 


Output Ldw Voltage 


VsR 


0.4 


Volts 


l0L= 1-6nnA 




"IH 


Input High Current 




3 


mA 


V|N ~ VdD' 3-State mode 




'IL 


Input Low Current 




-3 


juA 


V|N "^ Vss, 3-State nnode 


ADDRESS LINES 


VoH 


Output High Voltage 


4.0 


Vdd 


Volts 


l0H = -1 mA 


(ADDR0-ADDR15) 


Vol 


Output Low Voltage 


vss 


0.4 


Volts 


IOL = 3.2rTiA 


AND 


'l 


Leakage Current 




3 


mA 


V|N = V[)D, 3-State mode 


RAM WRITE 


'l 


Leakage Current 




-3 


mA 


VjN = Vss, 3-State mode 


CLOCK 


V|H 


Input High Voltage 


4.0 


Vdd 


Volts 




(*, WRITE) 


V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'l 


Leakage Current 




3 


/iA 


V|N = Vdd 


MEMIDLE, 


VoH 


Output High Voltage 


3.9 


Vdd 


Volts 


IOH = -1mA 


CYCLE REQ, 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L = 2 mA 


CPU READ 














CONTROL LINES 


V|H 


Input High Voltage 


3.5 


Vnn 


Volts 




(ROMC0-ROMC4) 


V|L 


Input Ldw Voltage 


Vss 


0.8 


Volts 






'l 


Leakage Current 




3 


idA 


V|N = 6V 


REGDR, 


VoH 


Output High Voltage 


3.9 


Vnn 


Volts 


IOH = -300mA 


CPU SLOT 


Vol 


Output Low Voltage 


Vrs 


0.4 


Volts 


iOL = 2 mA 




V|H 


Input High VBltage 


3.5 


Vnn 


Vdlts 


Internal Pull-up 




VJL 


Input Low Voltage 


Vss 


0.8 


Volts 






IlL 


Input Low Current 
(REGDR) 


-3.5 


-14.0 


mA 


V|N =0.4V& Device 
outputting a logic "1" 


. ■■ •• 


"L 


Leakage Current 




3 


juA . 


V|N = 6V 



2-D18 



3852 DMI 



Table 4-3. 3852 DMI Output Signals Timing Summary 



z 
oc 
o 
m 

Vi 

o 

< 

< 
@ 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


NOTES 


P* - 


* clock period 


0.5 




10 


/iS 


Fig. 2-9 


td2 


•t to WRITE -Delay 






250 


nS 




tad-i 


Address delay If PCO 


50 


300 


500 


nS 


3 


tad2 


Address delay to high Z (short cycle with DMA on) 


tcS2+50 




tcs2+200 


nS 


3 


tad3 


Address delay to refresh (short cycle with REF on) 


tcs2+50 




tcs2+400 


nS 


3 


tad4 


Address delay if DC 


2P*+50-td2 




2P*+400-td2 


nS 


3 


tad5 


Address delay to high Z (long cycle with DMA on) 


tcS3+50 




tcs3+200 


hS 


3 


tadg 


Address delay to refresh (long cycle with REF on) 


tcs3+50 




tcs3+400 


nS 


3 


tcr^ 


CPU READ -Delay 


50 


250 


450 


nS 




tcr2 


CPU READ + Delay 


2P*+50-td2 




2P<I)+400-td2 


nS 




tcs^ 


CPU SLOT + Delay 


80-td2 




320-td2 


nS 




tcs2 


CPU SLOT - Delay (PCO access) 


2P*+60-td2 




2P4)+420-td2 


nS 




tcs3 


CPU SLOT - Delay (DC access) 


4PcI>+60-td2 




2P<t+420-td2 


nS 




tm^ 


MEMIDLE + Delay (PCO access) 


2P'I)+50-td2 




4P(I>+400-td2 


nS 




tm2 


MEMIDLE - Delay (PCO access) 


4PfI>+50-td2 




4P<I>+350-td2 


nS 




tm3 


MEMIDLE + Delay (DC access) 


4Pfi)+50-td2 




4P*+400-td2 


nS 




tm4 


MEMIDLE - Delay (DC access) 


6P*+50-td2 




6P*+350-td2 


nS 




tcvi 


WRITE to CYCLE REQ - Delay 


80-td2 




400-td2 


nS 


1,4 


tcy2 


WRITE to CYCLE REQ + Delay 


P<l>+80-td2 




P1)+400-td2 


nS 


1,4 


tcy3 


CYCLE REO + to + Edge Delay 




2Pcl. 






1,4 


tcy4 


CYCLE REQ -to -Edge Delay 




2P* 






1,4 


twri 


RAM WRITE- Delay 


4P4>+50-td2 




4P't+450-td2 


nS 


3 


twr2 


RAM WRITE + Delay 


5PfI>H50-td2 




5P<I>+300-td2 


nS 


3 


twr3 


RAM WRITE Pulse Width 


350 




P* 


nS 


3 


twr4 


RAM WRITE to High Z Delay 


tcs2+40 




tcs2+200 


nS 


3 


trgi 


REGDR- Delay 


70 


300 


500 


nS 


1 


trg2 


REGDR + Delay 


2P«I>+80-td2 




2P<{)+500-td2 


nS 


1 


td4 


WRITE to Data Bus Input Delay 






2P<I'+1000. 


nS 




tdy 


WRITE to Data Bus Output Delay 


2P<I>+100-td2 




2P<I>+850-td2 




2 



Notes: 

1. C|_ = 50pf. 

2. Cl= lOOpf. 

3. Cl = 500 pf. 

4. CYCLE REO is a divide-by-2 of «!> for all instructions except the STORE instruction. 

5. On a given chip, the timing for all signals will tend to track. For example, if CPU SLOT for a particular chip is fairly slow 
and its timing falls out near the MAX delay value specified, then the timing for all signals on that chip will tend to be out 
near the MAX delay values. Likewise for a fast chip whose signals fall near the MIN values. This is a result of the fact that 
processing parameters (which affect device speed) are quite uniform over small physical areas on the surface of a wafer. 

6. Input and output capacitance is 3 to 5 pf typical on all pins except Vqq, Vqq, and Vgs. 



2-D19 



3852 DMI 



■ tadi 



■*— — tadi 



yc 



-tad-; 



tad4 ■ 



xzkzze: 



tadc 



tadc 



X^ 



J_/p 



tcr2 
•tcs2 ■ 



O 

I" r\ 



ui 



■tcy2 



\ / 



tcy-i 



tcy4 



S 

< 
oc 



t 



tcs3 

• tm2 — 



tm3 



tcyg- 



Q 



- twr4 ■ 



tm4 



•trgi >- 



:i 



A 



•trg2- 



-td4- 



X 



\ 



/ ^ 



7 



-twr3- 



\ r 



)C 



Figure 4-4. Timing Characteristics for 3852 DMI Output Signals 



2-D20 



o 

CO 
(0 

o 

< 
Q 
< 



3852 DMI/3853 SMI 

4.2.2 DC Electrical Specifications 

Absolute Maximum Ratings (Above which useful 
life may be impaired). 



vgg 
Vdd 

All other inputs & outputs 
Storage Temperature 
Operating Temperature 



Note: All voltages with respect to Vgg. 



DC Characteristics: Vgg = OV, Vqd = +5V ± 5%, 
Vgg=+12V±5%, 
Ta = 0°C to +70°C 

SUPPL Y CURRENTS 



+ 15V to-0.3V 
+7V to -0.3V 
+7V to -0.3V 
-55°Cto+150°C 
0°C to +70°C 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


TEST 
CONDITIONS 


Idd 
Igg 


Vqd Current 
V(3(3 Current 




35 
13 


70 
30 


mA 
mA 


f = 2MHz, 

Outputs 

unloaded 

f = 2MHz, 

Outputs 

unloaded 



Table 52. 3853 SMI Output Signals Timing Summary 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


NOTES 


P* 


4> clock period 


0.5 




10 


mS 


Fig. 2-9 


td2 


* to WRITE -Delay 






250 


nS 


2 


tady 


Address delay if PCO 


50 


300 


500 


nS 


3 


tad4 


Address delay if DCO 


2P«I>+50-td2 




2P4>+400-td2 


nS 


3 


tcr^ 


CPU READ - Delay 


50 


250 


450 


nS 


1 


tcr2 


CPU READ + Delay 


2P*+50-td2 




2P<l>+400-td2 


nS 


1 


twri 


RAM WRITE - Delay 


4P<l>+50-td2 




4P*+450-td2 


nS 


3 


twr2 


RAM WRITE + Delay 


5P<I>+50-td2 




5P<I>+300-td2 


nS 


3 


twr3 


RAM WRITE Pulse 


350 




P* 


nS 


3 


fgi 


REGDR- Delay 


70 


300 


500 


nS 


1 


trg2 


REGDR + Delay 


2P*+80-td2 




2P<I'+500-td2 


nS 


1 


td4 


WRITE to Data Bus 
Input Delay 






2P*+1000 


nS 




tdy 


WRITE to Data Bus 


2P*+100-td2 




2P*+850-td2 


nS 


2 


tri 


Output Delay 






430 


nS 


2.6 


WRITE to INT REG -Delay 


tpri 


PRI IN to INT REQ- Delay 




200 


240 


nS 


2.7 


tex 


EXT INT Set-up Time 


400 






nS 





Notes: 

1. CL = 50pf. 

2. CL=100pf. 

3. Cl = 500 pf. 

4. On a given chip, the timing for all signals will tend to track. For example, if CPU SLOT for a particular chip is fairly slow 
and its timing falls out near the MAX delay value specified, then the timing for all signals on that chip will tend to be out 
near the MAX delay values. Likewise for a fast chip whose signals fall out near the MIN values. This is a result of the fact 
that processing parameters (which affect device speed) are quite uniform. 

5. Input and output capacitance is 3 to 5 pf typical on all pins except Vqq, Vqq, and Vgs- 



6. Assume Priority In was enabled (PRI IN = 0) in previous F8 cycle before interrupt is detected in the PSU. 

7. PSU has interrupt pending before priority in is enabled. 



2-D21 



3853 SMI 



nv 



§ = 



•tadi 



.-^ 



X 



>. 



tad/ 



JL 



X 



DC 



tcr2 



y 



twri 



"V 



twr3 



H 



/" 



■trg-i 



twr2 ■ 



X 



v: 



trg2 



< I- 



^-^n 



^ 



%. 



tr2 



V 



7" 



tpri 



V 



tpr2- 



2V 



Figure 5-4. 3853 Signal Timing 



2-D22 



3854 DMA 



Table 6-3. Summary of 3864 DMA Signal Characteristics 



o 

m 

O) 

O 

< 
o 
< 

@ 



EL EC TRICAL SPEC I PICA TIONS 
Absolute Maximum Ratings (Above which useful life may be impaired) 



Vgg 
Vdd 

All other Inputs & Outputs 
Storage Temperature 
Operating Temperature 



+15Vto-0.3V 
+7V to -0.3V 
+7V to -0.3V 
-55°Cto+150°C 
0°C to +70°C 



Note: All voltages with respect to Vss- 

DC CHARACTERISTICS: Vgs = OV, Vqd = +5V ± 5%, Vqg = +12V ± 5%, T^ = to +70°C 



SUPPLY CURRENTS 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


TEST CONDITIONS 


'dd 
'gg 


Vqq Current 
Vq(3 Current 




20 
15 


40 
28 


mA 
mA 


f = 2 MHz, Outputs Unloaded 
f = 2 MHz, Outputs Unloaded 



SIGNAL 


SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


DATA BUS (DB0-DB7) 


V|H 


Input High Voltage 


3.5 


Vdd 


Volts 






V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






VOH 


Output High Voltage 


3.9 


Vdd 


Volts 


Ioh = -iooaiA 




Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L= 1-6 mA 




l|H 


Input High Current 




1 


AiA 


V|N = 6V, 3-State mode 




'il 


Input Low Current 




-1 


iuA 


V||\| = Vss. 3-State mode 


ADDRESS LINES 


VoH 


Output High Voltage 


4.0 


Vdd 


Volts 


l0H = -'' mA 


;addro-addri5) 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L = 3.2 mA 




'l 


Leakage Current 




1 


/iA 


V|(^ = 6V, 3-State mode 


ENABLE, DIRECTION 


VoH 


Output High Voltage 


3.9 


Vdd 


Volts 


IOH = -100pA 


DWS (DMA WRITE 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L = 2 mA 


SLOT), XFER, 














STROBE 


'l 


Leakage Current 




1 


pA 


V|N = 6V 



SIGNAL 


SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 




V|H 


Input High Voltage 


3.5 


Vdd 


Volts 




MEM IDLE, XFER REQ 




V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'l 


Leakage Current 




1 


juA 


V|N = 6y 


LOAD REG, READ 


V|H 


Input High Voltage 


3.5 


Vdd 


Volts 




REG, P1,P2 


V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'l 


Leakage Current 





1 


pA 


V,N = 6V 


WRITE, 'P 


V|H 


Input High Voltage 


4.0 


Vdd 


Volts 






V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'l 


Leakage Current 





1 


AiA 


V,N = 6V 



Note: 



Positive current is defined as conventional current flowing into the pin referenced. 



2-D23 



3854 DMA Table 6-4. 3854 DMA Device Signals Summary 






SYMBOL 


PARAMETER 


MIIM. 


TYP. 


MAX. 


UNITS 


NOTES 


P4> 


* Clock Period 


0.5 




10 


mS 


Note 1 


PWi 


4> Pulse Width 


180 




Pc|)-180 


nS 


t^, tf = 50 nS typ. 


W 


* to WRITE + Delay 


60 




300 


nS 


Note 1 


td2 


* to WRITE -Delay 


60 




250 


nS 


Note 1 


PW2 


WRITE Pulse Width 


P*-100 




P* 


nS 


tr, tf = 50 nS typ. 


td3 


WRITE to READ/LOAD REG 
Delay 






600 


nS 




td4 


DB Input Set-up Time 






300 


nS 




tde 


XFER REQ to MEM IDLE Set-up 


200 






nS 




tdy 


MEM IDLE to ADDR True 


50 


200 


500 


nS 


Cl = 500 pf 


tdy' 


MEM IDLEtoADDR3-State 


30 




-250 


nS 


CL = 500pf 


tds 


READ REG to DB Output 


40 




300 


hS 


CL=100pf 


tdg 


WRITE to ENABLES 
DIRECTION -H Delay 






450 


nS 


CL = 50pf 


tdg' 


MEM IDLE to ENABLE - Delay 






400 


nS 


CL = 50pf 


tdio 


MEM IDLE to XFER & DWS 
-t- Delay 






300 


nS . 


CL = 50pf 


tdio 


MEM IDLE to XFER & DWS 
- Delay 






300 


nS 


CL = 50pf 


tdii 


* to STROBE -f Delay 


30 ■ 




200 


nS 


CL = 50pf 


tdii 


* to STROBE -Delay 


30 




200 


nS 


C|_ = 50 pf 



Notes: 

1. These specif ications are those of * and WRITE as supplied by the 3850 CPU. 

2. Input and output capacitance is 3 to 5 pf typical on all pins except Vqq, Vqq, and Vgg. 



2-D24 



3854 DMA 



< 

a3 
UJ 

Z 
oc 
o 
m 

CO 

O 

S 
< 
o 

< 

@ 




Q -J 

< 



3-STATE 



U— tdy —*' Ut- tdy' 

X ADDRTRUE | 3STATr 




Figure 6-5. 3854 DMA Device Signals and Timing 



2-D25 



3856 2K PSU 



ABSOLUTE MAXIMUM RATINGS (Note 1) 

Supply Voltage Vqg 

Supply Voltage Vdd 

I/O Port Open Drain Option 

Other I/O Port Options 

All Inputs and Outputs 

Storage Temperature 

Temperature (Ambient) Under Bias 

NOTE 1 . Above which useful life may be impaired. All voltages measured with respect to Vss- 



+ 15 to -0.3 V 

+ 7 to -0.3 V 

+ 15 to -0.3 V 

+7 to -0.3 V 

+7 to -0.3 V 

-55 to +150°C 

to +70°C 



SUPPLY CURRENTS 



SYMBOL 


PARAMETER 


TYP 


MAX 


UNITS 


TEST 
CONDITIONS 


Idd 


Vdd Current 


75 


125 


mA 


f = 2 MHz, 

Outputs 

unloaded 


Igg 


Vgg Current 


30 


45 


mA 


f = 2 MHz, 

Outputs 

unloaded 



TYPICAL THERMAL RESISTANCE VALUES 



PLASTIC: 
0JA (Junction to ambient) 
^jc (Junction to case) 



CERAMIC: 

0JA (Junction to ambient) 
djc (Junction to case) 



= 60°C/W (Still Air) 
= 42°C/W 



= 48°C/W (Still Air) 
= 33°C/W 



TABLE 1. 3856 PSU SIGNAL DC CHARACTERISTICS 
DC ELECTRICAL CHARACTERISTICS: Vss = V. Vdd = +5.0 V ±5%, Vqg = + 1 2 V ±5%, Ta = CO to +70''C unless othenwiso noted. 



SYMBOL 


PARAMETER 


SIGNAL 


MIN 


MAX 


UNITS 


TEST CONDITIONS 


V|H 


Input HIGH Voltage 


Data Bus (DB0-DB7) 


2.9 


Vdd 


V 




V|L 


Input LOW Voltage 




Vss 


0.8 


V 




Vqh 


Output HIGH Voltage 




3.9 


Vdd 


V 


Iqh = -100 /iA 


Vol 


Output LOW Voltage 




Vss 


0.4 


V 


Iql = 1.6 mA 


l|H 


Input HIGH Current 






3.0 


mA 


V|N = Vdd. 3-State Mode 


Iql 


Input LOW Current 






-3.0 


^A 


V|N = Vss. 3-State Mode 


V|H 


Input HIGH Voltage 


Clock Lines (*. Write) 


4.0 


Vdd 


V 




V|L 


Input LOW Voltage 




Vss 


0.8 


V 




"l 


Leakage Current 






3.0 


fiA 


ViN - Vdd 


V|H 


Input HIGH Voltage 


Priority In and Control 


3.5 


Vdd 


V 




V|L 


Input LOW Voltage 


Lines (PRI IN, ROM Cq-ROM C4) 


Vss 


O.B 


V 




"l 


Leakage Current 






3.0 


mA 


ViN = Vdd 


VOH 


Output HIGH Voltage 


Priority Out (PRI OUT) 


3.9 


Vdd 


V 


'oh = -100 jiA 


Vol 


Output LOW Voltage 




Vss 


0.4 


V 


Iol=100mA 


VoH 


Output HIGH Voltage 


Interrupt Request (INT REQ) 






y 


Open Drain Output (Note 1) 


Vol 


Output LOW Voltage 




Vss 


0.4 


V 


Iql = 1.0 mA 


II 


Leakage Current 






3.0 


mA 


V,N = Vdd 


VoH 


Output HIGH Voltage 


Data Bus Drive (DBDR) 








External Pull-up 


Vol 


Output LOW Voltage 




Vss 


0.4 


V 


Iql = 2.0 mA 


"l 


Leakage Current 






3.0 


'^^ 


ViN = Vdd 



2-D26 



3856 2K PSU 



TABLE 1. 3856 PSU SIGNAL DC CHARACTERISTICS 
DC ELECTRICAL CHARACTERISTICS: Vss = OV.Vdd = +5.0 V:!:5%.Vgg = +12 V=i=5%.TA = 0°C to ^-70°Cunle5sothefwlsenoted■ 



SYMBOL 


PARAMETER 


SIGNAL 


MIN 


MAX 


UNITS 


TEST CONDITIONS 


VOH 


Input HIGH Voltage 


Strobe 


3.9 


Vdd 


V 


'oh = 10 niA 


Vol 


Output LOW Voltage 




Vss 


0.4 


V 


Iql = 2.0 mA 


V|H 


Input HIGH Voltage 


External Interrupt (EXT INT) 


2.9 


Vdd 


V 


l|N = -130 /lA (Internal Pull-up) 


V|L 


Input LOW Voltage 




v.ss 


0.8 


V 




l|L 


Input LOW Current 






-1.6 


mA 


V,N = 0.4 V 


VoH 


Output HIGH Voltage 


I/O Port Option A 


3.9 


Vdd 


V 


loH = -30 /xA. Note 5 


VoH 


Output HIGH.Voltage 


(Standard Pull-Up) 


2.9 


Vdd 


V 


l0H = -150 /xA 


Vol 


Output LOW Voltage 




Vss 


0.4 


V 


Iql = 1.6 mA 


V|H 


Input HIGH Voltage 




2.9 


Vdd 


V 


Internal Pull-up to Vqq, Note 3 


V|L 


Input LOW Voltage 




Vss 


0.8 


V 




l|L 


Input LOW Current 






-1.6 


mA 


V|N = 0.4 V, Note 4 


VoH 


Output HIGH Voltage 


I/O Port Option B 








External Pull-up 


Vol 


Output LOW Voltage 


(Open Drain) 


Vss 


0.4 


V 


Iql = 2.0 mA, Note 3 


V|H 


Input HIGH Voltage 




2.9 


Vdd 


V 




V|L 


Input LOW Voltage 




Vss 


0.8 


V 




Vqh 


Output HIGH Voltage 


I/O Port Option C 


4.0 


Vdd 


V 


loH = -1.0 mA 


Vol 


Output LOW Voltage 


(Driver Pull-Up) 


Vss 


0.4 


V 


Iql = 2.0 mA 



NOTES: 

1. Pull-up resistor to Vqq on CPU. 

2. Positive current Is defined as conventional current flowing into tfie pin referenced. 

3. Hysteresis input circuit provides additional 0.3 V noise immunity while Internal/external pull-up provides TTL compatitxlity 

4. Measured while I/O port Is outputting a high level. 

5. Guaranteed, but not tested. 

TABLE 2. 3856 PSU SIGNAL AC CHARACTERISTICS 
AC ELECTRICAL CHARACTERISTICS: Vss = V, Vqd = +5.0 V ±5%, Vqg = + 1 2 V ±5%. Ta = O'C to +70°C unless otherwise noted. 



SYMBOL 


PARAMETER 


MIN 


TYP 


MAX 


UNITS 


TEST CONDITIONS 


P« 


<l> Period 


0.5 




10 


MS 




PWi 


4> Pulse Width 


180 




P0-18O 


ns 


tr, tf = 50 ns Typ 


tdi. td2 


4> to Write + Delay 






250 


ns 


Cl = 100 pF 


td4 


Write to DB Input Delay 






2P<^ + 1.0 


MS 




PW2 


Write Pulse Width 


P(^-100 




P4> 


ns 


tr, tf = 50 ns Typ 


PWs 


Write Period; Short 




4P« 








PWl 


Write Period; Long 








ns 




td3 


Write to ROMC Delay 






550 


ns 




td7 


Write to DB Output Delay 
Write to DBDR - Delay 


2P</)+100-td2 


2P</.+200 


2P«-i-850-td2 


ns 


Cl = 100 pF 


tdfl 


Write to DBDR -I- Delay 




200 




ns 


Open Drain 


tri 


Write to INT Req - Delay 






430 


ns 


Cl = 100 pF. Note 1 


tpr. 


PRI In to INT Req - Delay 




200 




ns 


Cl= 100 pF, Note 2 


tpdi. tpda 


PRI In to PRI Out Delay 




800 




ns 


Cl = 50 pF 


tpd3. tpd4 


Write to PRI Out Delay 




600 




ns 


Cl = 50 pF 


«SP 


Write to Output Stable 






1.0 


MS 


Cl = 50 pF, Standard Pull-up 
Note 3 


lod 


Write to Output Stable 






2.5 


MS 


Cl = 50 pF, Rl= 12.5 kn 
Open Drain, Note 5 


•dp 


Write to Output Stable 




200 


400 


ns 


Cl = 50 pF, Driver Pull-up 


tsu 


I/O Set-up Time 


1.3 






MS 




fh 


I/O Hold Time 









ns 




tax 


Ext Int Set-up,Time 


400 






ns 




tsBi 


Write to Strobe + Delay 






5P</.+300 


ns 


Cl = 50 pF 


tsB2 


Write to Strobe - Delay 






6P<A-I-410 


ns 


Cl = 50 pF 



NOTES: 

1. Assume Priority In was enabled (PR! IN = 0) in previous F8 cyde trafore interrupt is detected in the PSU. 

2. PSU has interrupt pending b efore priority In is enabled. 

3. Assume pin tied to INT REQ input of the 3850 CPU. 

4. The parameters which are shaded in the table above represent those which are most frequently of importance wfien interfacing to an F8 system. Unshaded 
parameters are typically those that are relevant only between F8 chips and not normally of concern to the user. 

5. Input and output capacitance is 3 to 5 of typical on all pins except Vqq, Vqq and Vcs- 



2-D27 



3856 2K PSU 



PWi ■«- 



DATA BUS OUTPUT 



DBOR 

(END OF DATA OUT ' 

IN SUBEOUENT CYCLE) . 



DATA BUS INPUT 



\ 



JnzI^ ^ 



LONG CYCLE 



X 



>:: 



J 



x: 



Fig. 2 DATA BUS TIMING 



^~ — N. 



r~~^ 



X 



^. 



Z> 



X 



X 



X 



^ 



LONG CYCLE 



^. 



A 



> 



y 



T^ 



Fig. 3 INTERRUPT LOGIC SIGNALS I/O STROBE 



NOTES: 1. Timing measurements are made at valid logic level to valid logic level 
of the signals referenced unleSs otherwise noted. 

2. Symbols are defined in Table 2. 



2-D28 



< 

Q 

< 

@ 



3856 2K PSU/3861 PIO 

I/O operations that use the two PSU I/O ports execute in three instruction cycles. During the first cycle, the port 
address is transmitted to the Data Bus. During the second cycle, data is either sent from the Accumulator to the 
I/O latch or enabled from the I/O pin to the Accumulator depending on whether the instruction is an output or 
an input. At the falling edge or Write ( marking the end of the second cycle and beginning of the third cycle) the 
data is strobed into either the Latch (OUTS) or the Accumulator (ins) respectively. The third cycle is then used 
by the CPU for its next instruction fetch. Figure 4 indicates I/O timing. 

Data Bus timing associated with execution of I/O instructions does not differ from Data Bus timing associated 
with any other data transfer to, or from the PSU. However, timing at the I/O port itself depends on which port 
option is being used. Figures 5a, 5b, and 5c illustrate the three ports options. Figure 4 illustrates timing for the 
three cases. 




OUTPUT "I 
(DRIVER PULLUP) 



Fig. 4 TIMING AT PSU I/O PORTS 



(l.) The set-up and hold times specified are with respect to the end of the second longcycleduringexecutionof the three cycle IN or INS 
instruction. 

(2.) All delay times are specified with respect to the end of the second long cycle during execution of the three cycle OUT or OUTS instruction. 



7.2.2 Electrical Specifications 

Absolute Maximum Ratings (Above w/iich useful 
life may be impaired) 



Vgg 
Vdd 

External Interrupt Input 
All other Inputs & Outputs 
Storage Tenriperature 
Operating Temperature 



+15Vto-0.3V 

+7Vto-0.3V 

-600 mA to +225 juA 

+7V to -0.3V 

-55°Cto+150°C 

0°Cto+70°C 



SUPPL Y CURRENTS 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNITS 


TEST 
CONDITIONS 


Iqd 
'gg 


Vqd Current 
Vqq Current 




30 
10 


70 
18 


mA 
mA 


f = 2MHz, 

Outputs 

Unloaded 

f = 2MHz, 

Outputs 

Unloaded 



Supply currents measured with Vqd = +5V ± 5%, 
Vqq = +12V ± 5%, Ta = 0°C to +70°C. All other 
electrical specifications are in Table 7-4. AM 
voltages rneasured with respect to Vss- 



2-D29 



3861 PIO 



Table 7-4. A Summary of 3861 PIO Signal Characteristics 



SIGNAL 


SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


DATA BUS 


V,H 


Input High Voltage 


3.5 


Vdd 


Volts 




(DB0-DB7) 


V|L 


Input Low Voltage 


vss 


0.8 


Volts 






VOH 


Output High Voltage 


3.9 


Vdd 


Volts 


Ioh = -iooma 




Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L= 1-6 mA 




'IH 


Input High Current 




1 


ma 


V|(\j = 6V, 3-State mode 




'OL 


Input Low Current 




-1 


AiA 


V|N ^ Vss, 3-State mode 


CLOCK LINES 


V|H 


Input High Voltage 


4.0 


Vdd 


Volts 




(*, WRITE) 


V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'l 


Leakage Current 




1 


ma 


V|N = 6V 


PRIORITY IN AND 


V|H 


Input High Voltage 


3.5 


Vdd 


Volts 




CONTROL LINES 


V|L 


Input Low Voltage 


Vss 


0.8 


Volts 




(PR! IN, ROMCO- 


'l 


Leakage Current 




1 


/^A 


V,N = 6V 


R0MC4) 














PRIORITY OUT 


VoH 


Output High Voltage 


3.9 


Vdd 


Volts 


Ioh = -iooma 


(PRIOUT) 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


l0L = 100 mA 


INTERRUPT 


VoH 


Output High Voltage 






Volts 


Open Drain Output [1] 


REQUEST 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


'OL ^ ^ "^A 


(INTREQ) 


'l 


Leakage Current 




1 


HA 


V,N=6V 


DATA BUS DRIVE 


VoH 


Output High Voltage 








External Pull-up 


(DBDR) 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


IOL = 2mA 




'l 


Leakage Current 




1 


/iA 


V,N = 6V 


EXTERNAL 


V|H 


Input High Voltage 


3.5 




Volts 




INTERRUPT 


V|L 


Input Low Voltage 




1.2 


Volts 




(EXT INT) 


V|C 


Input Clamp Voltage 




15 


Volts 


l,H = 185/;A 




l|H 


Input High Current 




10 


//A 


V|N = Vdd 




l|L 


input Low Current 




-225 


;UA 


V|N=2V 




'IL 


Input Lpyv Current 


-150 


-500 


/iA 


VjN^Vss 


I/O PORT 


VoH 


Output High Voltage 


3.9 


Vdd 


Volts 


IOH = -30/iA 


(STANDARD 


VoH 


OutpjJt High Voltage 


2.9 


Vdd 


Volts 


IOH = -100iuA 


PULL-UP) 


Vol 


Output Low Voltage 


Vss 


0.4 


Volts 


Iql = 2 mA 




V|H 


Input High Voltage 


2.9 


Vdd 


Volts 


Internal Pull-up to Vdd [3] 




V|L 


Input Low Voltage 


Vss 


0.8 


Volts 






'IL 


Leakage Current 




1 


MA 


V|N=6V 




'L 


Input Low Current 




-1.6 


mA 


V|N=0.4V [4] 



Notes: 

1. Pull-up resistor to Vdd o" CPU. 

2. Positive current is defined as conventional current flowing into the pin referenced. 

3. Hysteresis input circuit provides additional 0.3V noise immunity while internal/external pull-up provides TTL compatibility. 

4. Measured while I/O port is outputting a high level. 

5. Vss = OV, Vdd = +5V ± 5%, VoG = ■H2V + 5%, Ta = 0°C to +1Q°C. 

6. Output device off. 



2-D30 



3861 PIO Table 7-5. A Summary of 3861 PIO Signal AC Characteristics 

AC Characteristics: V5S = OV, Vqq = +5V ± 5%, T^^^ = C to +70°C 
Symbols in this table are used by all figures in Section 7. 



z 
oc 
o 

GO 
0} 
O 

< 

a 

< 



SYMBOL 


PARAMETER 


MIN, 


TYP. 


MAX. 


UNITS 


TEST 
CONDITIONS 


P<I) 


<T> Period 


0.5 




10 


ns 




PWi 


<!> Pulse Width 


180 




P<t>-180 


nS 


tp tf = 50 nS typ. 


tdi 


* to WRITE + Delay 


60 




250 


nS 


Cl= 100 pf 


td2 


1) to WRITE -Delay 


60 




225 


nS 


Cl= lOOpf 


td4 


WRITE to DB Input Delay 






2P*+1.0 


ns 




PW2 


WRITE Pulse Width 


P<J>-100 




P* 


nS 


tp tf = 50 nS typ. 


PWs 


WRITE Period; Short 




4P* 








PWl 


WRITE Period; Long 




6P* 








td3 


WRITE to ROMC Delay 






550 


nS 




td7 


WRITE to DB Output Delay 
WRITE to DBDR -Delay 


2P<I>+100-td2 


2P*+200 


2P4>-^850-td2 


nS 


Cl= 100 pf 


tdg 


WRITE to DBDR + Delay 




200 




nS 


Open Drain 


tri 


WRITE to INT REQ- Delay 






430 


nS 


Cl= 100 pf [1] 


tr2 


WRITE to INT REQ + Delay 






430 


nS 


Cl= 100 pf [3] 


tpri 


PR! IN to INT REQ -Delay 






240 


nS 


CL=100pf [2] 


tpr2 


PRI IN to INT REQ + Delay 






240 


nS 


Cl= 100 pf 


tpdi 


PRI IN to PRI OUT -Delay 






300 


nS 


Cl = 50 pf 


tpd2 


PRI IN to PRI OUT + Delay 






365 


nS 


Cl = 50 pf 


tpdg 


WRITE to PRI OUT + Delay 






700 


,nS 


Cl = 50 pf 


tpd4 


WRITE to PRI OUT -Delay 






640 


nS 


Cl = 50 pf 


'^sp 


WRITE to Output Stable 






2.5 


AiS 


Cl = 50 pf. 
Standard Pull-up 


•tsu 


I/O Set-up Time 


1.3 






ns 




'th 


I/O Hold Time 









nS 




*tex 


EXT INT Set-up Time 


400 






nS 





Notes: 



1. Assume Priority In was enabled (PRI IN = 0) in previous F8 cycle before interrupt is detected in the PIO. 

2. PSU has interrupt pending before priority in is enabled. 



3. Assume pin tied to INT REQ input of the 3850 CPU. 

*4. The parameters which are starred in the table above represent those which are most frequently of importance when 

interfacing to an F8 system. Other parameters are typically those that are relevant only between F8 chips and not normally 
of concern to the user. 

5. Input and output capacitance is 3 to 5 pf typical on all pins except Vqq, Vqq, and Vss- 



2-D31 



3861 PIO 




DBOR(ENDOF 

DATA OUT IN 

SUBSEQUENT CYCLE) 



h 



tdg. 



/ 



Figure 7-3. 3861 PIO Data Bus Timing 



WRITE 



INPUT (1) 



OUTPUT (2) 

(STANDARD 

PULL-UP) 



_y 



V 



■^J— 



U— ts 



th 



DATA lyiAY CHANGE X"~" DATA STABLE X^ DATA MAY CHANGE 



[.*— tsp— ► 



2.9V 



STABLE 



SYMBOLS USED ARE DEFINED IN TABLE 7-5 

Notes: 

1. Data from the I/O port is strobed into the accumulator of the CPU at the end of the second instruction cycle during 
execution of an IN or INS instruction. 

2. During an OUT or OUTS instruction, data is strobed into the port latch at the end of the second instruction cycle; thus 
the cycle shown is the second cycle within the execution of the instruction. 

3. Input and output capacitance of 3 to 5 pf typical on all pins except Vqq, Vqq, and Vg3. 

Figure 7-4. timing at PIO I/O Ports 



2-D32 



3861 PIO 



o 
a 
w 
o 

< 

< 




Note: 



SYMBOLS ARE DEFINED IN TABLE 7-5 



Timing measurements are made at valid logic level to valid logic level of the signals referenced unless otherwise noted. 

Figure 7-6. Interrupt Logic Signals's Timing 



2-D33 



Chapter 3 
THE NATIONAL SEMrCONDUCTOR 

SC/MP 



5 SC/MP is a low-cost microprocessor that has been designed to operate easily in multi-microprocessor con- 

o figurations. The most interesting characteristic of SC/MP is its bus interface logic. Most microprocessors are 

^ designed to always operate as bus master in any microcomputer system. SC/MP, in contrast, has the bus inter- 

^ face logic of a support device; it does not assume that it has any more right to a System Bus than any other 

lu device. Bus request/acknowledge logic coupled with bus access priority logic makes SC/MP the slave 

oc microprocessor of choice in any multi-microprocessor application. 

o 

So The very open bus interface logic of SC/MP results in it having no special support devices; it shares the support 

° devices of other National Semiconductor microprocessors. These support devices are described in Volume III. 



< The prime source is: 

< 



NATIONAL SEMICONDUCTOR INC. 



® 2900 Semiconductor Drive 

Santa Clara, CA 95050 

The authorized second source for SC/MP is: 

, SIGNETICS 
81 1 East Arques Avenue 
Sunnyvale, CA 94043 

Although Signetics is authorized as an SC/MP second source, they are not yet manufacturing SC/MP and are not likely 
to do so until late 1978. 

Figure 3-1 conceptually illustrates the logic functions which are implemented on the SC/MP chip. One of the 
weaknesses of Figure 3-1, and the equivalent figures for the other microcomputers, is that the way in which 
logic functions are implemented cannot be identified. SC/MP, for example, implements non-CPU logic at a very 
elementary level, well suited for simple applications only. 



Nonetheless, Figure 3-1 does reveal a few of the rather unusual capabilities provided by SC/MP 
SC/MP. Notice that Serial-to-Parallel Interface Logic is shown as implemented by the SERIAL I/O 
SC/MP chip. SC/MP has two serial I/O device pins, one for serial binary input data, the other for 
serial binary output data. The assembly and disassembly of serial-to-parallei data is accomplished by one SC/MP in- 
struction. 

Figure 3-1 also shows Programmable Timer logic as being implemented by the SC/MP chip. This is barely 
justifiable — the SC/MP instruction set includes a Delay instruction that is used to generate timed durations ranging 
from 1 3 to 1 31 ,593 microcycles. Note, however, that during this delay interval the CPU can be performing no other ac- 
tions: the CPU is, in effect, operating solely as a programmable timer. This is obviously quite different from having a 
separate logic device that performs this timer function within a system. Once again, this points out the weakness of a 
generalized representation such as Figure 3-1. 



SC/MP DMA 
AND 

MULTIPROCESSOR 
LOGIC 



One other area of non-CPU logic shown as being implemented by SC/MP further illustrates 
this point. A portion of the Direct Memory Access (DMA) logic is provided by SC/MP 
using a few signals to control bus access. A significant amount of external logic would still 
be required to obtain an operational DMA system. Therefore, Figure 3-1 can be misleading 
because it cannot indicate the way in which the CPU implements a particular function. In this 
particular case there is also a significant area of non-CPU logic provided by SC/MP that is nowhere indicated by Figure 
3-1: The signals that can be used for DMA are primarily intended to simplify the design of multiprocessor 
systems. This is a very unusual logic function for a CPU to provide and therefore is not even suggested in Figure 3-1. 
But for SC/MP, the inclusion of this multiprocessor-oriented logic makes a lot of sense: its low cost and modest perfor- 
mance make it a likely candidate for multiprocessor systems. 

3-1 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Interrupt Priority 
Arbitration 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Bus Interface 
Logic 



Accumulator 
Registers) 



Data Counter(s) 



Stack Pointer 



Program Counter 



Direct Memory 

Access Control 

Logic 



System Bus 



♦ 


1 


i 


t 


I/O Communication 
Serial to Parallel 
Interface Logic 




ROM Addressing 

and 

Interface Logic 






1 
1 


L 
1 


Programmable 
Timers 




Read Only 
Memory 



I 



I/O Ports 
Interface Logic 



I/O Ports 



RAM Addressing 

and 
Interface Logic 



Read/Write 
Memory 



Figure 3-1. Logic of the SC/MP Microcomputer 



■3-2 



o 

< 
o 

< 

@ 



There are two versions of the SC/MP CPU: the original version uses P-channel silicon-gate SC/MP 
MOS/LSI technology and its part number is ISP-8A/500; the new version (SC/MP-II) uses AND 
N-channel technology and its part number is ISP-8A/600. The two versions are functionally SC/MP-II 
equivalent and fully compatible In terms of object code and pin configuration. (A few minor ' 
signal level conversions are required for complete signal compatibility: see Figure 3-3.) The SC/MP-II provides some 
significant advantages over the original version — it is twice as fast and uses only one-fourth the power of the 
original P-channel version. Additionally, while SC/MP requires two power sources (a +5 volt and a -7 volt sup- 
ply), SC/MP-II needs only a single +5 volt supply. Throughout this chapter, we will simply refer to the CPU as 
SC/MP: all the descriptions apply to both versions of the CPU unless we specifically mention SC /MP-II. 

Both versions of the SC/MP CPU have an on-chip clock oscillator and can use a capacitor, 
crystal, or TTL clock input to drive the clock. The P-channel SC/MP can run at a maximum fre- 
quency of 1 megahertz, which results in instruction execution times in the range of 10 to 50 
microseconds. SC/MP-II can operate at frequencies up to 4 megahertz with resulting instruction 
execution times in the range of 5 to 25 microseconds. Notice that although the. input frequency 
for SC/MP-II can be four times that of SC/MP, the instruction execution time for SC/MP-II is twice as fast (not four times 
as fast): this is because of internal differences in the way the on-chip clock oscillator uses the tim ing inp uts. 

Both versions of SC/MP provide TTL-compatible input and output signals. 
SC/MP PROGRAMMABLE REGISTERS 



SC/MP 

INSTRUCTION 
EXECUTION 
SPEED 



SC/MP 
LOGIC LEVEL 



SC/MP has an 8-bit Accumulator, an 8-bit Extension register, a 16-bit Program Counter, three 16-bit Pointer 
registers, and an 8-bit Status register. These programmable registers are illustrated as follows: 



8 bits 



8 bits 



16 bits 



16 bits 



16 bits 



16 bits 



8 bits 



Accumulator (A) 

Extension register (E) 

Program Counter (PC) or Pointer Register (PO) 

Pointer Register 1 (PI) 

Pointer Register 2 (P2) 

Pointer Register 3 (P3) 

Status register 



The Accumulator is a single, primary Accumulator, as described for our hypothetical microcomputer. 

The Extension register is used to assemble or disassemble serial-to-parallel data for serial data input and output. 
This register is also used as a buffer for the Accumulator. 

The Program Counter is 16 bits wide; therefore up to 65,536 bytes of memory may be ad- 



SC/MP 

MEMORY 

PAGES 



dressed in the normal course of events. The four high-order bits of the Program Counter 
represent page select bits; therefore the memory of an SC/MP system is divided into 16 
pages of 4096 words each. ; r- 

Notice that the Program Counter is shown as Pointer Register 0; this is done because some instructions move data bet- 
ween Pointer registers including the Program Counter. There is one other unusual fact about the SC/MP Program 
Counter: the four most significant bits (the page select bits) of the Program Counter are never incremented dur- 
ing the instruction fetch sequence. Instead, when the last address of a page is reached, the Program Counter 
"wraps-around" to the first address of the current page. For example, if the Program Counter-contains 2FFFi6' 
when it is incremented the new contents of the Program Counter will be 2000] 5 instead of 3000iq. The page.select 
bits of the Program Counter can only be changed by executing an instruction that loads a new value into the rtiost sig- 
nificant bits of the Program Counter. 

Note that the four high-order address bits are not output on separate address pins; instead they are output on the data 
lines at the beginning of an input/output cycle and must be demultiplexed by external logic in order to generate page 
select signals. 

The three Pointer registers are also used as Index registers or Stack Pointers. Typically, you would assign a 
specific function to each register. For example, the following assignments might be used: 

PI - ROM Pointer 
■ P2 - Stack Pointer 
P3 - Subroutine Pointer 



3-3 



These arbitrary assignments also reveal several interesting facts about the architecture of SC/MP. First, the SC/MP CPU 
does not provide an on-chip stack; instead, a stack can be nnaintained in memory using one of the Pointer registers as a 
Stack Pointer. Secondly, the SC/MP instruction set does not include a Jump-to-Subroutine instruction: one of the 
Pointer registers must be used \o hold subroutine addresses which can then be swapped with the Program Counter. 
We will discuss this in detail when we describe the SC/MP instruction set. 

ADDRESSING MODES 

The SC/MP memory reference instructions use program-relative direct addressing, indexed addressing, and 
auto-indexed addressing. All memory reference instructions are two-byte instructions and have the following 
object code format: 



76543210- 

I I I I I I I I I 



1 


■T 



Bit No. 



00= PC 
01 =P1 
10=P2 
11 =P3 



displacement 



= PC-relative or indexed 

1 = Auto-indexed 

Opcode 



Program relative and indexed addressing are as described in Volume I, Chapter 6. We will just re-emphasize 
here that all addressing in SC/MP is paged and uses the wrap-around technique — that is, there is no carry from 
the low order 1 2 bits of an address into the most significant 4 bits of an address. We mentioned this earlier when we 
discussed the Program Counter, and it also applies to indexed addressing. Thus, if the sum of the Index register (that is, 
one of the Pointer registers) and the second object code byte contents (displacement) is more than FFF16. the Carry bit 
will be discarded. This may be illustrated as follows: 



Pointer register (Index register) 



B4 




displacement 
I 4D I 



Effective Address = 1FB4 + 4D 



1 F B 4 
+ 4 D 



Expected result = 
Discard Carry 






Actual Result is 1001. 



Remember, all arithmetic operations during address formation, regardless of the addressing mode, obey this 
wrap-around technique: there is never a carry from bit 11 into bit 12. 

The auto-indexing mode of addressing provided by SC/MP instructions is actually an auto-increment/auto- 
decrement operation. When auto-indexing is specified, the displacement, as a signed binary. nunnber, is added to the 
contents of a Pointer register in order to compute an effective address. If the displacement is less than zero, the Pointer 
register is decremented by the displacement before the memory access. If the displacement is equal to or greater than 
zero, then the contents of the Pointer register is the effective address and the Pointer register contents are incremented 
by the displacement after the memory access. This method of auto-increment and auto-decrement addressing is 
the same as that described in Volume I with one significant difference: SC/MP allows an address to be incre- 
mented or decremented by any value in the range 0-127 instead of just by a value of one. 



3-4 



SC/MP STATUS REGISTER 

SC/MP has a programmable 8-bit Status register which may be illustrated as follows: 



o 

GQ 
W 

o 

<' 

Q 
< 

© 



cy/l 


ov 


SB 


SA 


IE 


F2 


Fl 


FO 





;i8) HT) (22) (21) (19J 

Circled numbers represent device pin numbers to which bits of the Status register are connected. 

The Carry (CY), Link (L) and Overflow (OV) status bits are typical microcomputer status bits as were described 
in Volume I, Chapter 7. 

• The two sense bits, SB and SA, are tied to SC/MP device pins. These two bits directly reflect the state of the 
logic signals applied to the device pins and thus can be used to detect external events. Although there are no 
SC/MP instructions that allow you to directly jump or branch on the condition of one of these bits, a sequence of mask- 
ing and testing instructions can be used to accomplish the same effect, albeit more slowly. The SA and SB bits are 
read-only bits. Instructions may read the status of these two bits, but only incoming signals may change t[^eir 
condition. For example, an instruction that moves the contents of the Accumulator to the Status register may modify 
any of the other status bits, but bits 4 and 5 will not change. The SA bit serves a dual function. If the Interrupt Epa- 
ble (IE) bit is set to one, the SA input serves as the interrupt input. We will discuss interrupt processing later in this 
chapter. 

FO, Fl pnd F2 are control flags that are tied to SC/MP device pins. The state of these three flags may be 
changed under program control and may be used to control external devices. When the state of any of these flags 
is changed, it is immediately reflected by a change in the signal level at the associated device pin. 

SC/MR CPU SIGNALS AND PIN ASSIGNMENTS 

Figure 3-2 illustrates the SC/MP pins and signals. A description of these signals is useful as a guide to the way 
in which an SC/MP microcomputer system works. 

The 12 address lines ADOO - AD1 1 output memory and I/O device addresses. These are tristate lines, and may 
be floated, giving external logic control of the Address Bus. The four most significant address bits 
(AD12 - AD15) are time multiplexed on the data lines. 

The eight Data Bus lines DBO - DB7 are multiplexed, bidirectional data lines through which 8-bit data units are 
input and output, and on which statuses and address bits are output at the beginning of any input/output cycle. 
Statuses on Data Bus lines DB4 - DB7 identify the type or purpose of the input/output cycle. The address bits 
on Data Bus lines DBO - DBS are the four most significant address bits (AD12 - AD15) which must be bsed to 
generate page select signals for memory or peripheral devices. Table 3-1 'describes the status and address infor- 
mation that is output on the Data Bus. Like the address lines, the data jines are tristate. 

SENSEA, SENSEB, FLAGO, 1, aqd 2 are pin connections for the similarly named Status register bits described 
earlier. 

SIN and SOUT are used in combination with the SIO instruction for serial input of Qata to the Extension register 
and serial output of data from the Extension register. 

The remaining signals (excluding clock, power and ground) may be divided into bus access. Data Bus definition, and 
timing control signals. 



You will notice that some of the SC/MP pins in Figure 3-2 have two sets of signal SIGNAL 
names: the names enclosed in parentheses reflect the nomenclature used with SC/MP- DIFFERENCES 

II. Aside from the clock and power signals which we shall discuss separately, the only BETWEEN SC/MP 
difference between SC/MP and SC/MP-II is in the polarity of bus access signals: Bus Request (P-CHANNEL) 
(BREQ/NBREQ), Enable In (ENIN/NENIN), and Enable Out (ENOUT/NENOUT). The "N" prefix to AND SC/MP-II 
each of the SC/MP-II signals indicates that these signals are negative-true — as opposed to (N-CHANNEL) 

the positive- (or logic "1") true signals for the P-channel SC/MP. In the descriptions that ———————— 

follow, we will use P-channel SC/MP nomenclature. If you are using the N-channel SC/MP-II version, you must 
simply invert these signals. ;• 



3-5 



NWDS 

NRDS 

(NENIN) ENIN 

(NENOUT) ENOUT 

(NBREQ) BREQ 

NHOLD 

NRST 

CONT 

DB7 

DB6 

DB5 

DB4 

DB3 

DB2 

DB1 

DBO 

SENSEA 

SENSEB 

FLAGO 

(GND)Vss 



PIN NAMEt 

X1,X2 
•DB0-DB7 
•AD00-AD11 
•SENSEA.SENSEB 
•FLAG0,1,2 \ 
•NRST 
•CONT 

•BREQ (NBREQ) 
♦ENIN (NENIN) 
•ENOUT (NENOUT) 
•NADS 
•NRDS 
•NWDS 
•NHOLD 

SIN 

SOUT 

VggVss<VccGnd) 

•These signals connect 
t Signals in parenthesis 




DESCRIPTION 

Crystal/Capacitor Connections 

Data Bus 

Address Lines 

External Status Input 

Flags 

Reset 

Halt/Continue 

Bus Request/Busy 

Data Bus Enable 

CPU Bus Access Status 

Address on Data Bus 

Data Input Strobe 

Data Output Strobe 

Clock Delay 

Serial Data In 

Serial Data Out 

Power and Ground 

to the System Bus. 

are SC/MP-II signal names. 



TYPE 

Input 

Bidirectional, Tristate 

Output, Tristate 

Input 

Output 

Input 

Input 

Bidirectional . 

Input 

Output 

Output 

Output, Tristate 

Oi|tput, Tristate 

Input 

Input 

Output 



Figure 3-2. SG/MP CPU Signals and Pin Assignments 



Before the SC/MP CPU can begin any input/output operation, it must gain access to the SC/MP 

System Busses, This approach reflects the design philosophy behind SC/MP. It is a relatively BUS ACCESS 

low-cost, low-performance CPU and the designers anticipated that it would frequently be used in CONTROL 

multiprocessor systems or in systems utilizing Direct Memory Access. Accordingly, three signals SIGNALS 
are provided to control access to the System Busses. 

BREQ is used as a bus busy input indicating that some other device is using the System Busses: as an output, 
BREQ is a bus request which is output when the System Busses are free and SC/MP requires access to the 
busses. 

ENIN is a control signal which is input to the CPU by external logic. When ENIN is low, the CPU is denied access 
to the System Busses and the'SC/MP address and data lines are held in tristate mode. 



3-6 



ENOUT is the CPU's output response to ENIN. When output high, ENOUT indicates that ENIN is high; therefore, the 
CPU can gain access to the Systenn Busses, but it has not done so. If ENOUT is low, it indicates either that ENIN is low, 
therefore the CPU is being denied access to the System Busses or, if ENIN is high, then it indicates that the CPU is using 
the Systenn Busses. 



SC/MP DATA 
BUS DEFINITION 
SIGNALS 



When the CPU has gained access to the System Busses, three signals identify the way in 

Q which the CPU is using the Data Bus. 

< NADS is output to indicate that a valid address has been output on the address lines and 

o that the low-order four bits of the Data Bus contain the high-order four bits of a 16-bit 

c address. NADS also indicates that status information is being output on the high-order four bits of the Data Bus. 

o "■.'■"■■ , . , , . 

^ NRDS, when output by the CPU, indicates that the CPU wishes to receive data on the Data Bus. 

ui NWDS, when output by the CPU, indicates that data is being output by the CPU on the Data Bus. NWDS may be 

H used by external logic as a write Strobe. 

g There are three signals which control CPU timing. 

w NRST is a system reset signal. When input low, it aborts any in-process operations. When 
< 



returned high, all programmable registers are cleared, and program execution begins with the 
instruction fetched from memor/ location 0001 is- 



SC/MP TIMING 

CONTROL 

SIGNALS 



g CONT may be Input to stop the CPU between instructions. When CONT is input low, all CPU operations are halted 

g after the current instruction execution has been completed. The CPU remains halted until CONT goes high. 

o 

^ NHOLD is an input signal used during input/output operations to lengthen the allowed time interval for devices 

< to respond to CPU access requests. 

< 
@ 

SC/MP TIMING AND INSTRUCTION EXECUTION 

The SC/MP timing for instruction execution is very simple. Instruction execution times are expressed in terms 
of microcycles. A typical instruction is executed in 1 microcycles; one (the first) or more of these microcycles is an in- 
put/output cycle. The length of a microcycle depends on the frequency of the clock inputs to the CPU: with the P- 
channel SC/MP, the minimum microcycle length is 2 microseconds; for SC/MP-II, the N-channel version, mininnum 
microcycle length is 1 microsecond. Thus, typical instruction execution time is 20 microseconds for the P-channel 
SC/MP, and 10 microseconds for SC/MP-II. All microcycles, whether internal machine cycles or input/output cy- 
cles, are of the same length : the only variance occurs when the NHOLD signal is used to stretch an input or out- 
put cycle. 

There are basically only three types of SC/MP machine (or micro) cycles: data input (read) cycjes, data output 
(write) cycles, and internal microcycles. The execution of each instruction is merely a concatenation of these three 
types of microcycles. 

SC/MP does, however, output some status information at the beginning of every input or output 
cycle; this status information provides a more precise definition of the events that will occur dur- 
ing that microcycle. Table 3-1 lists the information whjch may be output on the Data Bus at the 
beginning of an I/O cycle (when NADS is low). Table 3-2 defines the status information for non-1/0 
cycles. 



SC/MP 
I/O CYCLE 
STATUS 
INFORMATION 



3-7 



Table 3-1. Status and Address Output via the Data Lines 
at the Beginning of an I/O Cycle 



SYMBOLS 


DATA BUS 
BIT 


DEFINITION 


H-Rag 


r 


Indicates that a Halt instruction has been executed. 


D-Flag 


6 


Indicates that a Delay Instruction has been executed and that a 
delay cycle Is starting. 


l-Flag 


5'.- 


Indicates that the CPU is in the fetch cycle for the first byte of an 
instruction. 


R-F|ag 


4 


When high, indicates that the I/O cycle is a read cycle and that input 
data should be placed on the Data Bus when NRDS is active. When low, 
indicates that the I/O cycle Is a write cycle and that the Data Bus 
will contain output data when NWDS is active. 


AD15 


3 
2 
1 



The four most significant bits of a 16-bit address. 
Can be used as page select signals. 


AD14 


AD13 


AD 12 



Table 3-2. Statuses Output on the Data Bus for 
Various Types of Machine Cycles 



Status 
Information 


Data Bus 
Bit 


TYPE OF MACHINE CYCLE 1 


Instruction 
Fetch 


Halt 
Instruction 


Delay 
Instruction 


Data Input 
(Read) 


Data Output 
(Write) 


H-Flag 


7 


p^ 


■ 1 











D-Flag 


6 








1 





P 


l-Flag 


5 


1 


1 











R-Flag 


4 


1 


1 


1 


1 






SC/MP BUS ACCESS LOGIC 

Since the SC/MP CPU must gain access to the System Busses before it can perform an input or output cycle, 
we will describe the bus access logic before discussing input/output cycles. 

Figure 3-3 illustrates the bus access logic processing sequence that occurs whenever the SC/MP CPU is going 
to perform an input/output cycle. '' 

First, the bidirectional BRED |ine is tested. If the BREQ input is high, it indicates that the System Bus is currently in 
use: the CPU holds the outputs of the address and data lines, and the NRDS and NWDS signals in th|e high-impedance 
(tristate) mode. 

When the BREQ input signal is low (or goes low) it indicates that the System Bus is free, and the CPU then outputs a 
logic "1" on the BREQ line. This informs external devices (for example, other SC/MP CPUs or a DMA controller) that a 
request for bus access has been initiated. 

The CPU next tests the state of the ENIN input line. ENIN is essentially the "bus grant" signal: if it is low, it indicates 
the Bus Request (BREQ) is denied and the CPU remains in an idle state with its output held in the high impedance 
mode. When the ENIN input is high (or goes high) it indicates that the CPU's bus request has been granted and the I/O 
cycle can now be initiated. ■ 

When the I/O cycle has been completed, the CPU sets the BREQ output low to indicate that it has finished using the 
System Bus and that its outputs are once again in the high impedance mode. 



3-8 



o 

ffi 

(0 

o 

< 

Q 

< 

® 













r START '^ 


Initiate an I/O cycle. 
(Instruction fetch, data 




f 


input, or data output) 




CHECK 
BREQ 
INPUT 














^^^<breqV^^ yes 


If BREQ input high, bus is busy. Address 
and data lines, and NRDS, NWDS held 
in tristate mode. 




^S^^IGHX"^ 
|N0 








BUS IS AVAILABLE. 

OUTPUT BREQ 

HIGH 


Request bus access. 












^ INPUT ^ 
^S^^IGhl^^ 

^Cyes 


NO 


If ENIN low, bus access is 
denied until ENIN goes high. 










BUS 
ACCESS 
GRANTED 






1 






PERFORM 
I/O CYCLE 






1 






SET BREQ OUTPUT 

LOW WHEN I/O 

COMPLETE 













Figure 3-3. SC/MP Bus Access Logic Processing Sequence 

There are a couple of aspects of the bus access sequence which are not revealed by Figure 
3-3. 



SUSPENSION 
OF AN SC/IVIP 
I/O CYCLE 



First, the SC/MP CPU has the rather unusual capability of suspending an I/O operation after 
it has already begun. If the ENIN input line goes low while the CPU has access to the bus, the 
SC/MP address and data lines will go to the high impedance state, thus relinquishing access to the System Busses. The 
BREQ output signal will remain high and, when the ENIN input line subsequently goes high once more, the in- 
put/output cycle which had been suspended will begin again. 

This ability to suspend an I/O cycle might be quite useful in a system where bus access is granted on a priority basis. In 
such a system, it is conceivable that one or more of the system devices (another CPU, for example) might have overrid- 
ing priorities and require immediate access to the System Busses. The SC/MP bus access logic we've just described 
allows this to be accomplished with no difficulty whatsoever. There is, however, one gray area in this l/0-suspend 



3-9 



function. If an SC/MP I/O cycle is nearly complete, it would seem to be more efficient to go ahead and complete the cy- 
cle rather than suspending it and then restarting the entire cycle later. This is precisely what SC/MP does. Unfor- 
tunately., the SC/MP literature does not tell us where this "point-of-no-return" lies within an I/O cycle. One would 
assume, or at least hope that this point is prior to the time when NRDS or NWDS is sent out. These signals are the read 
and write strobe signals; if they were repeated when an I/O cycle was restarted, the same data might be read or written 
twice — a potentially vexing situation. However, you are at least assured that if ENIN goes low while SC/MP is perform- 
ing an I/O cycle, the cycle will be performed — either by continuing to completion or by being restarted when the 
System Busses are again available. 

If you refer back to Figure 3-3 once again, you will notice that there is no mention of 

the third SC/MP bus access control signal — ENOUT. This is not an oversight: — it is 

simply due to the fact that the ENOUT signal performs a rather specialized function which 

is not necessary to an understanding of the SC/MP bus access logic. The primary function 

of the ENOUT output signal is as an enabling signal in systems where a "daisy chain" 

technique is used to establish priorities for bus access. We will defer a discussion of this use of ENOUT until later in 

this chapter when we discuss the use of SC/MP in multiprocessor and DMA systems. 

If the SC/MP CPU is used in a single-processor, non-DMA system then there is no need for the 
built-in bus access logic. In these cases, which may in fact be in the majority, the bus access 
signals should be connected so that the SC/MP CPU is always guaranteed immediate access 
to the System Busses. This is easily accomplished by making the following connections: 



SC/MP ENOUT 
SIGNAL USED 
TO ESTABLISH 
ACCESS PRIORITIES 



SC/MP I/O 
WITH BUS 
ACCESS LOGIC 
CONTINUOUSLY 
ENABLED 





SIGNAL 


CONNECT TO 


SC/MP 


BREQ- 

ENIN 

ENOUT 


■ VGG through a pull-down resistor. 

vss 

Leave unterminated . ■ 


SC/MP-II 


NBREQ 
NENIN 
NENOUT 


VCC via external resistor 

Ground 

Leave unterminated 



In the descriptions of SC/MP input/output operations that follow, we will always assume that the SC/MP CPU 
has already been granted access to the System Busses, and that this access is not interrupted (or suspended). 

SC/MP INPUT/OUTPUT OPERATIONS 

Once the SC/MP CPU has control of the System Busses, an actual input or output cycle can begin. As we men- 
tioned earlier in this chapter, the execution of any SC/MP instruction includes some combinations pf input/output cy-' 
cles and internal machine cycles. Figure 3-4 illustrates the bus utilization required for each of the SC/MP instruc- 
tions, and also reveals an interesting, non-obvious fact about SC/MP input/output operations. Observe that each 
bus utilization interval is shown as being two microcycles in duration. This is true because each input/output opera- 
tion effectively requires two microcycles. The CPU spends a portion of the first microcycle gaining access to the 
System Bus and placing address and status information on the address and data lines. The actual data transfer (read or, 
write) occurs during the second microcycle. This can be confusing if you are designing a DMA or multiprocessor 
system: the actual time that the bus is available is a great deal less than you would expect if you based your computa- 
tions solely on the number of read and write cycles required for each instruction. To make this more clear, refer to Table 
3-3, which lists the read cycles, write cycles, and total microcycles required for execution of each SC/MP instruction. If 
you total up each of the columns. from this table, you come up with the following figures: 

Total Read Cycles = 79 
.: • • ■•;..• Total Write Cycles .= 3_ . • 

Total Input/Output Cycles = 82 
Total Microcycles =466 . 

Based on these figures, it would appear'that bus utilization is less than 20% (82/466). However, since the CPU main- 
tains control of the bus for approxihnately two microcycles each time a read or write cycle is performed, the actual bus 
utilization is quite a bit greater than you would have expected. For precise timing parameters refer to the data sheets at 
the end of thischapter. Keep in mind that bus utilization computations should be based not only on these data sheets, 
but also on the actual program being-used, since bus utilization is directly related to the connposition of instructions 
which comprise your program — these calculations can differ significantly from any theoretical calculations based 
solely on a CPU's complete instruction set. 

Now, having discussed those areas of SC/MP bus access and utilization which might be confusing, let us proceed to 
examine the actual data input/output operations — we will find that these SC/MP operations are quite straightforward. 



3-10 



o 

CO 
CO 

o 

< 
o 

< 



INSTRUCTION 


TIME IN MICROCVaES | 


'hh 


hhh|7|8| 


9 1 10 1 It 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 1 20 1 21 1 22 1 23 1 24 1 2S 1 26 1 


Sa. Ca. CSA. RR. RRL. SR, SHL. and SIO 

LDE. ANE. ORE. XRE, CAS. lEN. and DINT 

XAE. XPPC, and ADE 

CAE. XPAH. and XPAL 

DAE 

HALT 

JP. JZ and JNZ (No jump) 

JMP. JP. JZ. and JNZ (Do jumpl 

ADI 

LDI, ANI. ORI. and XRI 

CAI 

DAI 

ST 

LO. AND. OR. XOR 

ADD 

CAD ... 

DAD 

DLD and ILD 

DLY (minimum) 










1 














LEGEND: 

^^^^Q BUS UTILIZATION INTERVAL 

tS»^:SSS>l READ CYCLE WITH H-FLAG OUTPUT 






1 






•::'rz:i 


1 








1 






(wx¥!¥!>l OPERAND STORE 


.y.'z:^ 1 ■ ■ 








;.".j.>.i^J 


i:^!;:^^:^^ 1 














^n^r^m 


Zl 












■..•..■•"■.a 


fT'^m 


1 












":s^^ 


t^'""::^^'i 


1 












:::::..r"'i 


t.ZLS^l 


1 












ill 


i: -i 


1 












■:":'?TJ 


iii^n 










1 


;:v:;;;::;;:.-i 


r:3sra 


i:;:::.:: \ i 












-7±- 


E:i^ra 


o;e 


1 




^i 




! 


itn 


i"3^r.n 


f«:j£rs 


1 










-JoLJ_ 


t:::::i^K::3 


i^<o 1 




tr'i^ri 


F'l^Pi 1 












:.■"". .;;i 


trtTTi 
















„;;;..;..,.] 


r^r-m 


1 





Figure 3-4. Bus Utilization of Each SC/MP Instruction 



Table 3-3. SC/MP Instruction Execution Times 



INSTRUCTION 


READ 
CYCLES 


WRITE 
CYCLES 


TOTAL 
MICROCYaES 


ADD 


3 





19 


ADE 


1 





7 


ADI 


2 





11 


AND 


3 





18 


ANE 


1 





6 


ANI 


2 





10 


CAD 


3 





20 


CAE 


1 





8 


CAI 


2 





12 


CAS 


1 


. 


6 . 


CCL 


1 





5 


CSA 


1 





5 


DAD 


3 





23 .. 


DAE 


1 





11 


DAI 


2 





15 


DINT 


1 





6 


DLD 


3 


1 


22 


DLY 


2 





13- 131593 


HALT 


2 





8 


lEN 


1 





6 


ILD 


3 


1 


22 


JMP 


2 





11 


JNZ 


2 





9, 1 1 for Jump 



INSTRUCTION 


BEAD 
CYaPS 


WRrre 

CYOFS 


TOTAL 
MICROCYCLES 


JP 


2 





9. 11 for Jump 


JZ 


2 





9, 1 1 for Jump 


LD 


3. 





18 


LDE 


1 





6 


LDI 


2 





10 


NOP 


1 





5 


OR 


3 





18 


ORE 


1 





6 


ORI 


2 





10 


RR 


1 





5 


RRL 


1 





5 


SCL 


1 





5 


sio 


1 





5 


SR 


1 





5 


SRL 


1 





5 


ST 


2 


1 


18 


XAE 


1 





7 


XOR 


3 





18 


XPAH 


1 





8 


XPAL 


1 





8 


XPPC 


1 





7 


XRE 


1 





6 


XRI 


2 





10 



Note: If slow memory is being used, the appropriate delay should be added for each read or write cycle. 



3-11 



Figure 3-5 illustrates the timing for a standard SC/MP data input cycle. This tinning applies SC/MP DATA 
regardless of whether the input cycle is to access data from memory or peripheral devices and INPUT CYCLE 
also applies to instruction fetch operations. ^____^.^___ 

Once the CPU has gained access to the System Busses, the input cycle begins by presenting address and statuses 

on the address and data lines. When the NADS signal is sent out, the least significant 1 2 bits of address data are valid 
on the SC/MP address lines, and the SC/MP data lines are outputting status information and the most significant 4 bits 
of address information. Table 3-1 defines the information that is output on the data lines while NADS is true. When 
these address bits and/or status bits need to be latched, either the leading or trailing edge of NADS can be used as a 
clock signal. 



BREQ 



EMN 



NADS 



AD 11 -ADOO 



DB7 - DBO 



NRDS 




^—T 



Floating 



■c 



Address Valid 



Floating 



AD12 - AD15 



■^And Status^ 



Floating 



Roating 



Roating 



Output 



Floating 



\ 



n- 



Floating 



Figure 3-5. SC/MP Data Input Cycle 

Shortly after the trailing edge of NADS, the Data Bus is floated and the Read Data Strobe (NRDS) signal is out- 
put. Valid input data is expected prior to the trailing edge of NRDS. 

The SC/MP data output cycle begins in the same way as the data input cycle. The only 
difference is that immediately after the status/address information is output on the data 
lines, the write or output data is placed on the data lines. As shown in Figure 3-6, the NWDS 
signal is sent out to indicate when valid output data is present. Either the leading or trailing edge 
of NWDS could be used to latch the output data into external data latches. 



SC/MP 
DATA 
OUTPUT 
CYCLE 



BREQ 



ENIN 



NADS 



AD11 -ADOO 



\ 



\ r 



Floating 



Address Valid 



Roating 



DB7 - DBO 



NWDS 



Floating 



AD12 - AD15 



[And Status Output] 



Output Data Valid 



Roating 



Roating 



^ n 



Roating 



Figure 3-6. SC/MP Data Output Cycle 



3-12 



o 

CO 
(0 

o 

< 

< 
@ 



The data input/output cycles just described allow approximately one microcycle for exter- SC/MP NHOLD 

nal logic to respond. If additional access time is required, the NHOLD input signal to the CPU SIGNAL FOR 

can be used to lengthen an input/output cycle. The NHOLD signal can be set low any time prior SLOW I/O 

to the trailing edge of NRDS or NWDS as shown in Figure 3-7; this causes the trailing edge of OPERATIONS 
NRDS or NWDS to be delayed until after NHOLD has been returned high. On data input cycles, the 
time until valid input data must be presented is simply delayed. On data output cycles, the valid output data is main- 
tained on the data lines by the CPU until the delayed trailing edge of NWDS. 



NADS 



NHOLD 



■i}- 



Normal strobe timing 



* 



NRDS/NWDS 



oiw liming Nw^ 



'Ddayed strobe 



Figure 3-7. NHOLD Signal Used to (.engthen SC/MP I/O Operation 

The NHOLD signal causes the I/O cycle to be lengthened in increments of 1/2 microcycle. There is no limit on 
the duration of the NHOLD signal. 

THE SC/MP HALT STATE 

The SC/MP Halt state differs from those described for other microprocessors in this book in one significant and 
unusual way — execution of the SC/MP Halt instruction does not cause the CPU to enter the Halt state. Instead, 
when SC/MP executes a Halt instruction, it simply outputs the H-Flag status on data line 7 (DB7) when NADS is true. 

In order to actually place the CPU in the Halt state the CONT input signal to the CPU must be forced low. 

You can use external logic to force CONT low either in response to the H-Flag or completely asynchronously: whenever 
a low is applied to the CONT input, the CPU enters the Halt state upon completion of the current instruction. Figure 3-8 
shows a circuit that can be used to force the CPU into the Halt state when a Halt instruction is executed. When DB7 is 
output high while NADS is true, it indicates the Halt instruction has been executed: this combination of events is used 
to generate a low-going pulse (NHALT) which is applied to the clear (CLR) input of a D flip-flop. The Q output of the flip- 
flop is applied to the CONT input signal to the CPU. Thus, whenever a Halt instruction is executed, the CPU will be 
forced into the Halt mode. CPU operation is resumed when the start switch SI is momentarily closed to the NO con- 
tacts. This causes a positive-going clock pulse that sets the D flip-flop and returns the CONT input to the CPU high. 



+ 5V 



SI 
START 



NC 




SWITCH 
DEBOUNCER 



NO 



J- 



1 



PRE 
D Q 



7474 



CLK 



CLR 

■TT 



CONT 



SC/MP 



DB7 



NADS 



NHALT 



<o 



<<F 



Figure 3-8. Circuit to Cause Programmed Halt for SC/MP CPU 



3-13 



While the SC/MP CPU is in the Halt state, the address and data lines are floated. The CPU remains in the Halt 
state until the CONT input is returned high. There is one exception to this rule: if an interrupt request is 
detected while in the Halt state, the CPU responds to the interrupt by executing a single instruction. Thus, you 
could use the first instruction of your interrupt service routine to reset the external CONT input signal, and thereby ter- 
minate the Halt state. 

SC/MP INTERRUPT PROCESSING 

The SENSEA input signal to the SC/MP CPU serves as the interrupt request line if bit 3 of the CPU's Status 
register is set to "1 ". Bit 3 of the Status register is the Interrupt Enable (IE) flag and can be set using the Inter- 
rupt Enable (lEN) instruction. 

When interrupts are enabled, the SENSEA input line is tested at the beginning of every instruction fetch opera- 
tion as shown in Figure 3-9. If SENSEA is high, the IE flag is reset, and the contents of the Program Counter are 
exchanged with the contents of Pointer Register 3. In other words, Pointer Register 3 nnust contain the beginning 
address of your interrupt service routine. The return address, that is, the address at which program execution must con- 
tinue after the interrupt request has been serviced, is now held in Pointer Register 3. Thus, the return-from-interrupt se- 
quence would be to set the IE flag high and then once again exchange the contents of the Program Counter and Pointer 
Register 3 to resume the main program. 

Let us examine some of the special requirements and limitations of this interrupt processing sequence. First, 
before enabling interrupts you must load Pointer Register 3 (P3) with the beginning address of your interrupt 
service routine. Notice that the contents of P3 should actually be one less than the beginning address of the 
first instruction since the new contents of the Program Counter will be incremented prior to fetching the in- 
struction. 



INTERRUPT 




RESET frfTERRUPT 

ENABLE RAG 
EXECLTTE XPPC 3 



INCREMEhiT PROGRAM 
COUNTER. FETCH AND 
EXECUTE INSTRUCnON 



Figure 3-9. SC/MP Interrupt Instruction Fetch Process 



3-14 



< 

o3 

UJ 

Z 
oc 
o 
m 

(0 

o 

< 
o 

< 

@ 



SC/MP RETURN- 

FROM-INTERRUPT 

TECHNIQUE 



Next, if you compare the interrupt response of SC/MP to those of most other microcomputers or to our hy- 
pothetical microcomputer described in Volume I, you will notice that the following two steps are missing: 

1) There is no interrupt acknowledge signal. 

2) None of the SC/MP register contents are saved. 

In an SC/MP system, both of these functions are left up to your interrupt service routine. For example, you might 
provide an interrupt acknowledge indication using one of the CPU Flag outputs or by outputting a specially defined ad- 
dress. If it is necessary to save the contents of the SC/MP registers, this must also be done by your program using a 
software stack or a predefined area of read/write memory. You must also provjde the instructions necessary to restore 
the contents of any "saved" registers since, as we shall discuss next, the return-from-interrupt sequence used by 
SC/MP is also quite primitive. 

The final unusual aspect of the SC/MP interrupt system is that there is no Return-From- 
Interrupt instruction. Instead, as we mentioned earlier, the last instruction of your inter- 
rupt service routine must be an XPPC P3 instruction which restores the original contents 
of the Program Counter by exchanging the contents of PC and P3. This might seem quite 
straightforward, but it will require some special programming considerations. 

The XPPC P3 instruction, which we just mentioned, restores the correct value to the Program Counter — but what 
about P3? Remember that P3 is always supposed to point to the beginning address (minus 1) of your interrupt service 
routine (if interrupts are enabled). Yet, the interrupt response sequence we just described loaded the contents of P3 
into the Program Counter (PC) and then incremented the PC. And, as our interrupt service routine is executed, the con- 
tents of PC will be incremented each time an instruction is executed. Thus, when we complete the interrupt service 
routine and again exchange the coritents of PC and P3, we will be loading P3 (our service routine pointer) with a value 
that has been altered. So, the problem is — how do we perform an interrupt service routine and ensure that P3 will con- 
tain the correct pointer value upon completion of the service routine? 

The solution to this quandary requires a closer examination of interrupt service routines. A typical interrupt service 
routine might consist of three primary segments. One segment would be the entry point to the routine and would in- 
clude such things as register save operations: let us call this segment "SI". The second segment would be the instruc- 
tion sequence which actually services the device vyhich requested the interrupt: we will call this segment "S2". The 
final segment would restore registers and other system ejements to their 'pre-interrupt' values, and then return control 
to the main (interrupted) program: we will call this segment "S3". Thus, the entire interrupt recogni- 
tion/response/return sequence might be represented as follows: 



(We will use arbitrary addresses to simplify our discussion.) 



0040 



P3 [ 



"onr 



After th« SC/MP responds 
to the interrupt: 



PC I 0540 h 

P3 I 6646 I - 



0040 



P3C 



Q36f 



MAIN PROGRAM 



INTERRUPT 
SERVICE ROUTINE 



003E 
003F 



««a- 



Interrupt request recognized at this point. 
SC/MP performs an XPPC P3 operation. 



Entry point and save 
routine 



Main body of service 
routine 



S3 

Restore routine and 

return to main 

program 



053F 
0540 

054F 
0550 

055F 
0560 



• Last instruction of your interrupt 
service routine is XPPC P3. 
After this instruction .^^^>— ^— 



1 



Control is returned to Main Program 
resuming at point of interruption. 



3-15 



This sequence causes a proper return to the interrupted program but, as we have discussed, does not leave us with our 
desired pointer value (053F in this example) .in P3. The solution requires us to rearrange the segments of our interrupt 
service routine as follows: 





: ^• 


MAIN PROGRAM 








003E 






003F 


pel 00 40 1 




0040 










P3 1 053F 1 » 


























INTERRUPT 
SERVICE ROUTINE 






S3 
Restore routine 

and return 
to main program 




After SC/MP responds 
to the interrupt: 


Last instruction of your service 

053F ^n routine is XPPC P3 

0540 ^ Rrst instruction of 

„^.^ interrupt service routine 
054F 

0550 






PC 1 0540 1 
P3 1 0040 1 


SI 

Entry point and 

save routine 




S2 

Main body of sen/ice 

routine 



to the beginning of S2 at address 0530 ' 



Now, our entry point for the interrupt service routine is still 0540, so we load P3 with a pointer of 053F as' before. 
However, by rearranging the segments and adding a Jump instruction at the end. of the second segment (S2), we can 
have the last instruction of our interrupt service routine located at 053F. When this instruction (XPPC P3) is executed 
the following operation occurs: 



Before 



PC r 053F 



P3 I 0040 



After 




We have now returned control to the main program and we have also restored/the contents of P3 to the required 
pointer value to allow servicing of subsequent interrupts. 

One final point: the CPU's interrupt processing sequence resets the Interrupt Enable (IE) flag to zero. To allow 
subsequent interrupts to be serviced, your service routine must set the IE flag to "1". This would typically be the 
next to last instruction of your interrupt service routine. So the sequence of instructions would be: 



lEN SET IE FLAG TO 1 

XPPC P3 RETURN TO MAIN PROGRAM 

FIRST INSTRUCTION OF SERVICE ROUTINE 



3-16 



< 

HI 

z 
oc 
o 
m 

(A 

o 

< 

< 
@ 



SC/MP DMA AND MULTIPROCESSOR OPERATIONS 

Because the SC/MP CPU is a low-cost, low-performance microprocessor, its designers anticipated that it would fre- 
quently be used in systems which include other devices of equal or greater intelligence and processing power. Accor- 
dingly, logic is provided on the CPU which provides a simple yet effective method of operating in systems 
where the System Busses are shared. The logic required to implement a shared-bus system is essentially the same 
regardless of whether the purpose is to allow another device (such as a high-speed peripheral) to perform a DMA opera- 
tion or if it is required because there is more than one CPU operating in the system. There are a few rather subtle 
differences between the techniques used, and we shall point these out as we proceed with our discussion. 



As we have already described, three SC/MP signals are dedicated to bus-sharing ac- SC/MP 

tivities: BREQ is an input/output signal which serves both as a bus-request and bus-busy BUS-SHARING 

signal, ENIN is effectively a bus-grant input signaj, and ENOUT is an output signal that CONTROL 

can be used to establish priorities in daisy chained configurations. Let us begin by seeing SIGNALS 

how SC/MP might operate in a system which includes a DMA controller. 

The DMA logic provided by the SC/MP CPU is nearly the inverse of that provided by other rnfcrocomputers in 
this book. Most CPUs assume that they always have control of the System Busses. If another system device requires 
access to the System Busses, it makes a request to a DMA controller which, in turn, inputs a signal to the CPU request- 
ing that the CPU yield control of the busses. When the CPU has no need for the bus, it outputs an acknowledgement 
signal to the DMA controller which then sends a bus-grant signal to the requesting device. The SC/MP CPU. 
however, competes for the System Busses just as any other system device: it never assumes that it has control 
of the busses. Thus, there are reaNy no special considerations that need be accounted for when designing DMA logic 
for systems that include the SC/MP CPU. The DMA controller can treat the CPU as simply another device (no different 
from a peripheral device, although the CPU might be assigned'to a higher priority) that requires access to the System 
Busses. Therefore, a typical DMA application would on|y require the use of the SC/MP BREQ and ENIN signals as 
shown in Figure 3-10. ' ' 



MEMORY 



C=^ 



DMA 
CONTROLLER 



DMACK2 



DMACKl 



DMACKO 



DMA REQ 2 



DMA REG 1 



C=> 



SC/MP 



BREQ 
(DMAREQO) 



ENIN 
(DMACKO) 



c=> 



DEVICE 
1 



DMAREQ1 



DMACKl 



c=:> 



DEVICE 
2 



DM/^PEQZ 



DMACK2 



Figure 3-10. Using SC/MP in a System with Direct Memory Access 



3-17 



SC/MP IN 

MULTIPROCESSOR 

SYSTEMS 



Now let us look at how the SC/MP bus-sharing logic might be used in a multiprocessor 
system. It Is in such a system that the CPU's bus-sharing logic can be most appreciated. 
First, let us restate the rules which govern the conditions of the SC/MP ENOUT output 
sjgnal. '■] 

1) ENOUT is always low while SC/MP is actually using the System Busses; that is, while the ENIN input and 
BREQ output are both high. 

2) When SC/MP is not using the System Busses (either BREQ output or ENIN input low), ENOUT is held in the 
same state as the ENIN input. 

The effect of these rules may not be immediately obvious. To see how they function to simplify bus-sharing, let 
us construct a simple multiprocessor system consisting of two SC/MP CPUs and some memory. 

Vgg(-7V) 



BREQ1 
ENIN1 - EN0UT1 



SC/MP 

#1 



c 



7S 



iZ 



BREQ2 



ENIN2 



SC/MP 

#2 



7^ 



\7 



1 



SYSTEM BUSSES 



MEMORY 



There are three possible situations that can exist with this configuration. 

1) If one of the CPUs is currently using the bus, it is outputting a high on the BREQ line. This automatically prevents 
the other CPU from vying for the bus until the BREQ'lipe goes low upon completion of the bus access by the first 
CPU. 

2) If neither CPU is currently using the bus. the BREQ line is low. If one of the CPUs requires bus access, it can now 
output a high on the BREQ lirjp. Once again, this will prevent the other CPU from subsequently vying for the bus. 

Thus far there would seem to be no need for any control signals except the bidirectional BREQ line. However, it 
is when the third possibly situation is encountered that the ENIN and ENOUT signals are needed. 



3-18 



3) If both CPUs require bus access at the same time, each will test the BREQ line and, finding it low, will output a high 
on BREQ. This simultaneous occurrence of requests for bus access is resolved by using the ENIN and ENOUT sig- 
nals. The operation of these bus access signals to resolve this situation can be illustrated as follows: 



o 

GQ 
CO 

o 

< 

Q 

< 



BREQ1 



BREQ2 



ENIN1 



enoUti 



ENIN2 




"?^ 



■^^ 



^i« 



SC/MP #1 BUS 
ACCESS COMPLETE 



SC/MP #2 BUS 
ACCESS COMPLETE 




—- f? 

SC/MP #2 

GRANTED BUS ACCESS 

ih- 



\ 



•th 



SC/MP #2 DENIED 
BUS ACCESS 



' SC/MP #2 GRANTED 
BUS ACCESS 



SC/MP CONTROL 
TECHNIQUES IN 
MULTIPROCESSOR 
APPLICATIONS 



When the BREQ line goes high it applies a high input to the ENIN1 input of SC/MP #1. Since BREQ1 is also high at this 
time, SC/MP #1 now has access to the bus and it outputs a low on ENOUTI. This is applied to the ENIN2 input to 
SC/MP #2 and thus denies busaccess by SC/MP #2. Notice that SC/MP #2 holds its BREQ2 output signal high even 
though its request has not yet been granted. When SC/MP #1 has finished its bus access, the BREQ1 output returns 
low. However, since the BREQ2 output is still high, ENIN1 remains high. This condition of BREQ1 low and ENIN1 high 
causes the ENOUTI signal to go high, thus enabling SC/MP, #2. 

This arrangement allows the fjrst CPU in a daisy-chain string to have the highest priority for bus access and also 
automatically allows any other CPU to gain immediate access to the busses whenever they become available. 

Now that we have described the way in which the bus-sharing logic of the SC/MP CPU can be 
used in a multiprocessor system, let us continue just a bit further and describe a few more 
common considerations that you must deal with if you are designing a multiprocessor system. 
We will limit this discussion primarily to hardware and control considerations since program- 
ming in a multiprocessor system can become quite complex and is beyond the scope of this 
book. However, the techniques we will describe here are the first step towards simplifying the programming for such a 
system. 

The first operation that you must deal with in any microcomputer system is initialization of the system. This 
operation requires some additional thought when designing a multiprocessor system. Typically, one CPU will be 
the primary or controlling CPU: how do you ensure that this CPU has control of the system when power is first ap- 
plied? 

Figure 3-11 illustrates an easy method of establishing system control upon initialization. The system reset signal 
(NRST), which is generated at power-up, is applied to SC/MP #1.TheFLAG1 output from SC/MP #1 is then applied to 
the NRST input of SC/MP #2. Since the FLAG1 line is connected to a bit in the CPU's Status register which is set to 
zero on power-up, SC/MP #2 will be held in a reset condition until SC/MP #1 executes an instruction which sets that 
bit (and thus, the FLAG1 output line) high. 

Of course, this method requires the FLAG1 output from SC/MP #1 to be dedicated to this initialization operation. If this 
is a problem, you coijid use two separate initialization circuits with, for example, the RC time constant for the SC/MP 
#2 circuitry being greater than that of the circuitry for SC/MP #1. This approach, however, does not provide the posi- 
tive control of the first method we described. 



3-19 



Initialization 
Circuit 





A 


NRST 










SC/MP 






#1 






FLAG1 


21 








.A 


NRST 

SC/MP 












#2 





Figure 3-1 1. One Method of Initializing an SC/MP Multiprocessor System 

Once the multiprocessor system has been initialized and is running, the bus-sharing logic that we've already described 
will resolve contentions between the CPUs as far as access to System Busses is concerned. However, there might be 
situations where we want to assure that one of the CPUs will be guaranteed immediate and extended access to 
the System Busses. This can also be accomplished quite easily with SC/MP as illustrated in Figure 3-12. 













SC/MP 






#1 






p->o-2 


CONT 






21 


FLAG! 

SC/MP 










#2 













Figure 3-12. Forcing the Halt State in an SC/MP Multiprocessor System 



3-20 



In this illustration the FLAG 1 output of SC/MP #2 is inverted and applied to the CONT input of SC/MP #1 . Now, if the 
F1 bit in the Status register of SC/MP #2 is set to "1", SC/MP #1 will be forced into the Halt state and is effectively 
removed from the system until the F1 bit is reset under program control. 

THE SC/MP RESET OPERATION 

An NRST low signal input to the SC/MP CPU initializes the microprocessor. While NRST is low, any in-process 
ui operations are automatically aborted and the CPU's strobes and address and data lines are floated. NRST must be held 

< low for a minimum of two microcycles. After NRST goes high again, this is what happens: 

EC 

2 1) All of the programmable registers are cleared. 

o 2) The first instruction is fetched from memory location 0001 16. 

S 3) The Bus Request (BREQ) for this first input/output operation occurs within 6-1/2 microcycles after NRST goes high. 

u The NRST signal can be used at any time to reset the CPU. and must be used following power-up since SC/MP 

< may power up in a random condition. After power has first been applied to the CPU, you should allow approximately 
5 100 milliseconds for the oscillator and internal clocks to stabilize before applying the NRST signal. 

« SC/MP SERIAL INPUT/OUTPUT OPERATIONS 

»3 The SC/MP CPU not only has two of its 40 pins designated primarily for serial input/output operations, it also 

z dedicates one instruction from its rather limited instruction set solely to serial I/O. Allocation of this amount of a 

o CPU's resources for this purpose would seem unwarranted with most microprocessors; however, keep in mind that 

" SC/MP is a very low-cost device and intended primarily for use in slow-speed applications. It is quite likely that SC/MP 

° will frequently be used to transfer data serially, so it is therefore not only reasonable but advantageous to provide 

^ straightforward methods of performing these operations. Let us look now at how this is done with SC/MP. 

< In our description of SC/MP's programmable registers, we described the Extension (E) register as an 8-bit register. 
(g) When the E register is used for serial I/O, it is actually a 9-bit register with connections to two of the device 

pins as shown in the figure below. 

Extension Output 

Register Latch 



SIN 



B^-~» H7[6|5|4|3|2| 1 |0| B^Q »-0^ 



SOUT 



When the SC/MP SIO (Serial Input/Output) instruction is executed, the contents of the Extension register are 
shifted right one bit position: the previous contents of bit are loaded into the output latch and output on the SOUT 
pin, and the level (1 or 0) present at the SIN pin is loaded into bit 7 of the Extension register. The Extension register can 
be loaded from, and its contents can be transferred to the Accumulator. A typical serial output operation would thus 
consist of: 

1) Loading the Accumulator with the data byte that is to be transmitted. 

2) Transferring the contents of the Accumulator into the Extension register. 

3) Performing eight SlOJnstructions to shift the contents of the Extension register into the output latch and out onto 
the SOUT pin. 

Of course, this sequence does not cover all the programming requirements for serial data transfers. For example, your 
program must provide some method of timing the bit transmission. This is easily accomplished with SC/MP by using 
the Delay (DLY) instruction, which can generate variable time delays ranging from 13 to 131,593 microcycles. For 
asynchronous operations, one of the SC/MP Flags which are connected to device pins can be pulsed each time a new 
bit is shifted out (or in) and one of the sense conditions inputs (SENSEA or SENSES) can be tested to detect bit 
received/ready. 



3-21 



THE SC/MP INSTRUCTION SET 

Table 3-4 lists the SC/MP instruction set. 

Memory reference instructions are shown as having either full or linnited addressing capability. Full addressing 
capability is identified in the operand as follows: 

: 't DISP (X) ■ 



1 



^ If present, X stands for P1, P2 or P3, and indexed 
addressing is specified 

^ Must always be present. Specifies a program 
relative displacement. • 

^ If present, specifies auto-increment or auto- 
decrement addressing. 

Thus, the real options associated with full addressing capability are: 

DISP Direct, program relative addressing 

DISP(X) Direct, indexed addressing 

@DISP(X) Auto-increment or auto-decrement addressing" 

Limited addressing capabilities do not include the auto-increment and auto-decrement feature. The operand field for 
instructions with limited addressing capability is shown as follows: 

DISP (X) 



I 



— If present, X stands for PI, P2 or P3 and Indexed 
addressing is specified 

— Must always be present. Specifies a program ' 
relative displacement. 

The serial I/O instruction inputs serial data via the high-order bit of the Extension register, and/or outputs serial data via 
the low-order bit of the Extension register. ■ ' 

The serial I/O instruction works as a one-bit right shift of the Extension register contents, with bit being shifted to the 
SOUT pin and the SIN pin being shifted into bit 7. This has been illustrated along with the logic description. 

It is worth noting that SC/MP has no Jump-to-Subroutine instruction; rather, the XPPC instruction is used to exchange 
the contents of the Program Counter with the contents of a Pointer register. In very simple applications (and those are 
the applications for which SC/MP is intended) this is a very effective scheme. Providing subroutines are not nested, a 
subroutine's beginning address may be stored in a Pointer register, then execution of XPPC moves the subroutine's 
starting address to the Program Counter, thereby executing the subroutine — but at the same time, the Program 
Counter contents are stored in the Pointer register, thus preserving the return address. At the conclusion of the 
subroutine, execution of another XPPC instruction is all that is needed to return from the subroutine. The only penalty 
paid is that one Pointer register is out of service while the subroutine is being executed. If all Pointer registers are 
needed by the subroutine, or if subroutines are nested, then the return address which is stored in the Pointer register 
must be saved iri memory. In these more complicated applications, one of the Pointer registers will probably be used as 
a Stack Pointer, and addresses will be saved on the Stack. 

This type of subroutine access, while it may appear primitive to a minicomputer programmer, is very effective in simple 
microcomputer applications. 

The following symbols are used in Table 3-4. 

AC Accumulator 

C Carry status 

DATA An 8-bit binary data unit 

DISP An 8-bit signed binary displacement 

E The Extension register 



3-22 



< 
u 
o 

(O 
CO 

< 

UJ 

z 
cc 
o 

GO 

o 

< 

Q 

< 

@ 



EA Effective address, determined by the instruction. Options are: 

DISP EA is [PCl + DISP 
DISP(X) EA is [Xl + DISP 
@DISP(X) EA is [X] if DISP 5=0, 

EA is [Xl + DISP if DISP <0; 

in both cases [X]^[X] + DISP after EA is calculated. 

E<i> The ith bit of the Extension register 

IE Interrupt Enable 

Overflow status 

PC Program Counter 

X One of the three Pointer registers 

SIN Serial Input pin 

SOUT Serial Output pin 

SR Status register 

Z Zero status 

@ Auto-increment flag 

X<y,z> Bits y through z of a Pointer register. For example, P3<7,0> represents the low-order byte of Pointer 
register P3. 

@DISP(X) This designates the available addressing modes for the SC/MP, as described above. In all three of the ad- 
dressing modes, if -128 is specified for DISP, the contents of the Extension register are used instead of 
DISP. 

[ ] Contents of location enclosed within brackets. If a register designation is enclosed within the brackets, 

then the designated register's contents are specified. If a memory address is enclosed within the 
brackets, then the contents of the addressed memory location are specified. 

[[ ]] Implied memory addressing; the contents of the memory location designated by the contents of a 

register. 

A Logical AND 

V Logical OR 

"V" Logical Exclusive-OR 

^— Data is transferred in the direction of the arrow. 

" ► Data is exchanged between the two locations designated on either side of the arrow. 

Under the heading of STATUSES in Table 3-4, an X indicates statuses which are modified in the course of the instruc- 
tion's execution. If there is no X, it means that the status maintains the value it had before the instruction was ex- 
ecuted. 



3-23 



Table 3-4. SC/MP Instruction Set Summary 



TYPE 


MNEMONIC 


OPERAND(SI 


BYTES 


STATUSES 


OPERATION PERFORMED 


C 


O 










O 


SIO 




1 














[E<i-1>]*-[E<i>] 

SOUT — [EO] 

[E7]— SIN 
Shift the Extension register right one bit. Shift bit of the Extension register to the output pin 
SOUT. Shift the data at input pin SIN intd bit 7 of the Extension register. 


u. 

lU 

> K « 

tit 


LD 
ST 


& DISP(X) 
@ DISP(X) 


2 
2 














[AC]-[EA] 

Load Accumulator from addressed memory location. 
[EA]-[AC] 

Store Accumulator contents in addressed memory location. 


Ul 

O 

z 

lU 

§° 

M 

o < 
o 

lU 


ADD 
DAD 
CAD 
AND 

OR 
XOR 

ILD 
OLD 


@ DISP(X) 
@ DISP(X) 
@ DISHX) 
@ DISP(X) 
@ DISP(X) 
@ DISP(X) 
@ DISP(X) 
@ DISP(X) 


2 
2 
2 
2 
2 
2 
2 
2 


X 
X 
X 


X 
X 










[AC]-[AC]+[EA]+[C] 

Add binary to Accumulator the addressed memory location's contents with Cany. 
[AC] — [AC]+ [EA]+ [C] 

Add decimal to Accumulator the addressed memory location's contents with Carry. 
(ACl— [AC]+ [EA1+ [C] 

Add complement of addressed memory location's contents with Carry to Accumulator. 
[AC]-[AC] A [EAl 

AND Accumulator with addressed memory location's contents. 
[ACl— [AClV [EA] 

OR Accumulator with addressed memory location's contents. 
[AC]— [AC]¥[EA1 

Exclusive-OR Accumulator with addressed memory location's contents. 
[EA]— [EA] + 1; [AC]— [EA] 

Increment addressed memory location's contents,then load Into Accumulator. 
[EA]— [EA]-1; [AC]— [EA] 

Decrement addressed memory location's contents, then load into Accumulator. 


Q 
lii 

s 
z 


LDI 


DATA 


2 














[AC]— DATA 
Load immediate into Accumulator. 


1 

lU 

Ol 
O 

s 

5 
III 

S 

s 


ADI 
DAI 
CAI 

AM 


DATA 
DATA 
DATA 

DATA 


2 
2 
2 

2 


X 
X 
X 


X 
X 










[AC]-[AC] + DATA+[C] 
Add binary immediate. Add Carry to result. 

[AC]— [AC] + DATA+[C] 
Decimal add immediate. Add Carry to result. 

[AC]-[AC] + DATA+ [C]' 
Add the contents of the Accumulator to the complement of the immediate data value. Add Car- 
ry to result. 

[AC]— [AC] A DATA 
AND immediate. 



ADAM OSBORNE & ASSOCIATES. INCORPORATED 



Table 3-4. SC/MP Instruction Set Sumnriary (Continued) 



TYPE 


MNEMONIC 


OPERANDISI 


BYTES 


STATUSES 


OPERATION PERFORMED 


C 













r 
Si 

si 


ORI 
XRI 


DATA 
DATA 


2 
2 














[AC]— [AC] V DATA 

OR immediate. 
[AC] — [AC] V DATA 

Exclusive-OR immediate. 


0. 

s 


J^JP 


DISPtX) 


2 














[PC]— EA 
Unconditional jump to effective address. 


n 

"8 


jp 

JZ 
JNZ 


DISP(X) 
DISP(X) 
DISP(X) 


2 
2 
2 














If [AC] 2=0; [PC]— EA 

If the Accumulator contents are greater than 0, jump to effective address. 
If [AC]=0; [PC]-EA 

If the Accumulator contents equal 0, jlJmp to effective address. 
If [AC]=0; [PC]-EA 

If the Accumulator contents are not 0. jump to effective address. 


> 

O 

s 

K 
Ul 

t- 
(0 

5 

UJ 
K 

tk 

UI 

h- 

co 
5 

UJ 


LDE 
XPAL 

XPAH 

XPPC 
XAE 


X 
X 
X 
















[AC]-[E] 

Load the contents of the Extension register into the Accumulator. 
[AC]— [X<7,0>] 

Exchange the contents of the Accumulator with the lovi^ order byte of the specified Pointer 

register. 
[AC]' •[X<:i5,8>] 

Exchange the contents of the Accumulator with the high order byte of the specified Pointer 

register. 
[PC]< -[X] 

Exchange the contents of the Program Counter with those of the specified Pointer register. 
[AC]" >[E] 

Exchange the contents of the Accumulator with those of the Extension register. 


oe 

0. 

o 

e 

lU 

1- 

M 

O 

UJ 

E 

CC 
Ul 
K 
U) 

5 

Ul 

E 


ADE 
DAE 
CAE 
ANE 




■ 


X 
X 
X 


X 
X 










[AC]-[AC]+[E]+[C] 
Add binary the contents; of the Accumulator and the contents of the Extension register. Add Ca- 
rry to this result. 

[AC]-[AC]+[E]+[C] 
Add decimal the contents of the Extension register to those of the Accumulator. Add Carry to 
this result. 

[AC]-[AC]+[E]+[C] 
Add binary the contents of the Accumulator and the complement of the Extension register con- 
tents. Add Carry to this result. 

[AC]— [AC] A [E] 
AND the contents of the Accumulator with those of the Extension register. . 



Table 3-4. SC/MP Instruction Set Summary (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUSES 


OPERATION PERFORMED 


C 


O 










REGISTER- 
REGISTER 
OPERATE 
(CONTINUED) 


ORE 
XRE 




1 
1 














[AC]— [AC] V [El 

OR the contents of the Accumulator with those of the Extension register. 
[AC]— [AC]¥[E] 

Excluslve-OR the contents of the Accumulator with those of the Extension register. 


lU 

i 

lU 

a. 
o 

oc 

lU 

2 


SR 
SRL 

RR 
RRL 




1 
1 

1 
1 


















^'U - »-0| »- 


Shift Accumulator contents right one bit. The high order bit becomes a 0. The low order bit is 
lost. . , , 




Shift Accumulator contents right one bit. The Carry bit Is shifted into the high order bit of the 
Accumulator. The low order bit is lost. 


1 _ 1 






Rotate Accumulator contents right one bit. Rotate the low order bit of the Accumulator into the 
high order bit. 


I ■ ..« 1 




Rotate Accumulator contents right through Carry. 


E 

ce 

UJ 

1- 
z 


DINT 
lEN 




1 
1 














[IE]-0 

Disable Intenupts. 
[IE]-r 

Enable interrupts. 


0» 

■ D - 

■1- 


CCL 
SOL 
CSA 
CAS 




1 

1 . 
1 

1 




. 1 












[Cl-0 

Dear Carry. 
[C]-1 

Set Carry. 
[AC]-[SR1 

Load the contents of the Status register into the Accumulator. 
[SR1-[AC] 

Load the contents of the Accumulator Into the Status register. 




HALT 
NOP 
DLY 


DATA 


1 
1 
1 














Pulse the H-Rag 

No Operation. 

Delays CPU for a number of cycles equal to: . 

13 + 2(AC) + 2DATA + 29dATA 



o 
m 
v> 
O 

< 
o 

< 



The following symbols are used in Table 3-5: 

aa Two binary digits designating the Pointer register: 

00 Program Counter 

01 Pointer Register 1 

10 Pointer Register 2 

1 1 Pointer Register 3 

m One binary digit specifying address mode: 

Program Relative or Indexed .. ; 

1 Immediate or Auto-increment or Auto-decrement 

PP Two hexadecimal digits representing an 8-bit, signed displacement 
QQ Two hexadecimal digits representing 8 bits of immediate data 

Where two numbers are given — for example, 9/1 1, the first is execution time when no jump is taken; the second is ex- 
ecution time when there is a jump. 

Table 3-5. SC/MP Instruction Set Object Codes and Execution Times 



INSTRUCTION 


OBJECT 
CODE 


BYTES 


MACHINE 
CYCLES 


ADD @DISP(X) 


nilOmaa 
PP 


2 


19 


ADE 


70 


1 


7 


ADI DATA 


F4 
QQ 






AND @DISP(X) 


llOIOmaa 
PP 


2 


18 


ANE 


50 


1 


6 


AN! DATA 


D4 
QQ 


2 


10, 


CAD DISP(X) 


linimaa 
PP 


2 


20 


CAE 


78 


1 


8 


CAI DATA 


FC 
QQ 


2 


12 


CAS 


07 


1 


6 


CCL 


02 


1 


5 


CSA 


06 


1 


5 r 


DAD @DISP(X) 


inOlmaa 


2 


23 


DAE 


68 


1 


11 


DAI DATA 


EC 
QQ 


2 


15 


DINT 


04 


1 


6 


DLY DATA 


lOmOaa 
PP 


2 


22 


DLY DISP 


4F 
PP 


2 


13-131, 593* 


HALT 


00 


1 


8 


lEN 


05 


1 


6 


ILD DISP(X) 


lOIOIOaa 
PP 


2 


22 


JMP DISP(X) 


lOOOOOaa 
PP 


2 


11 



INSTRUCTION 


OBJECT 
CODE 


BYTES 


MACHINE 
CYCLES 


JNZ DISP(X) 


10001 lea 
PP 


2 


9/11 


JP DISP(X) 


lOOOOIaa 
PP 


2 


9/11 


JZ DISP(X) 


lOOOIOaa 
PP 


2 


9/11 


LD ®piSP(X) 


llOOOmaa 
PP 


2 


18 


LDE 


40 


1. 


6 ,, 


LD! DATA 


C4 
QQ 


2 


10 . 


NOP 


08 


. 1 


5-10. 


OR @DISP(X) 


llOllmaa 
PP 


2 


18 


ORE 


58 


1 


6 


■ ORI DATA 


DC 
QQ 


2 


10 


RR ■ • ■ 


IE 


1 


5 


RRL 


IF 


1 


5 


SCL 


03 


1 


5 


SIO 


19 


1 


5 


SR- 


1C 


1 


5 


SRL 


ID 


1 


5 


ST @DISP(X) 


llOOImaa 
PP 


2 


18 


XAE , 


01 


1 


7 


XOR ©DISRX) 


1 1 lOOmaa 
PP 


2 


18 


XPAH X 


OOllOlaa 


1 


8 


XPAL X 


OOllOOaa 


1 


8 


XPPC X 


OOiniaa 


1 


7 


XRE 


60 


1 


6 


XRI DATA 


E4 
QQ 


2 


10 



•Delay time depends on the value of DATA. 



3-27 



LD 


TABLE(P3) 


XPAH 


PI 


LD 


TABLE+1(P3) 


XPAL. 


PI 


LDI 


lOHl 


XPAH 


P2 


LDI 


lOLO 


XPAL 


P2 


LD 


@0(P2) 


ST 


@0(P1) 


DLD 


I0CNT(P3) 


JNZ 


LOOP 


XPAL 


PI 


ST 


TABLE+1(P3) 



THE BENCHMARK PROGRAM 

For SC/MP, the benchmark program looks like this: 

LOAD HIGH BYTE OF FIRST FREE TABLE BYTE 
ADDRESS MOVE TO PR1 HIGH-ORDER BYTE 
REPEAT FOR LOW-ORDER BYTE 

LOAD HIGH BYTE OF I/O BUFFER BASE ADDRESS 
MOVE TO PR2 HIGH-ORDER BYTE 
REPEAT FOR LOW-ORDER BYTE 

LOOP LD @0(P2) LOAD NEXT BYTE FROM I/O BUFFER 

AUTO-INCREMENT 
STORE IN NEXT FREE TABLE BYTE 
DECREMENT I/O BUFFER COUNT AND LOAD 
RETURN TO LOOP IF NOT ZERO 
LOAD LOW-ORDER TABLE ADDRESS INTO A 
SAVE IN FIRST FREE TABLE BYTE ADDRESS 

The SC/MP benchmark program makes the following assumptions. 

The address of the first free table byte is not stored at the beginning of the table; rather, it is stored in two bytes of a 
data area, addressed by Pointer Register 3, plus a displacement. The addresses of these two bytes are given by the dis- 
placement TABLE and TABLE-fl. 

It is assumed that TABLE begins at a memory address with Os for the low order eight binary digits (as for the F8 
benchmark program); therefore, the contents of the data area byte with address TABLE-l-1 (PC3) becomes the displace- 
ment to the first free byte of TABLE. Assuming that TABLE has a maximum length of 256 bytes, it is only necessary at 
the end of the data move operation to store a new byte address into TABLE-l-1, in order to update the address of the 
first free table byte. This scheme is illustrated below. 

The I/O buffer beginning address is stored in two immediate instructions, which load the two halves of the I/O buffer 
beginning address into the Accumulator; each half is then exchanged into a Pointer register. 

The SC/MP benchmark program assumptions may be illustrated as follows: 

MEMORY 



P3- 



lOCNT- 

























Middle of 256-byte data area 






addressed by P3 


TABLE - 


yy 


yy 




















LDI 


Program 


aa 




Area 




XPAH 






LDI 




bb 








XPAL 








■ aabb 


































































yyvY 



















3-28 



SUPPORT DEVICES FOR THE SC/MP CPU 



3C/MP support devices are general-purpose and are therefore 'described in Volume III. You may also use stan- 
dard off-the-shelf buffers, bidirectional drivers, RAM and ROI\^ to implement any supporting functions needed. 
Figure 3-13 illustrates an SC/MP system and the type of supporting devices that might be needed. Notice that 
the buffers, latches and I/O ports are all indicated by dotted lines. We have done this because it is quite feasible that 
some SC/MP systems might consist only of the CPU and a small amount of memory. In such a system, there would not 
necessaMly be any need for buffering the SC/MP input/output lines, nor demultiplexing status and page-select bits 
from the Data Bus. Many systems, however, will require some of the supporting devices indicated by Figure 3-1 3. In the 
remainder of this chapter we will briefly describe how some of the commonly required support functions for SC/MP can 
be implemented using both standard off-the-shelf devices and devices from other microcomputer families. 



o 

< 

Q 

< 



CRYSTAL 

OH 
CAPACITOR 

rjgh 



|<^\\^\\\\^\\\\\^^^^^ 



4m.\v\vv\^\mm\^^^^^^ 



NADS 
NROS 
NWDS 



FLAG0,1,2 
SQUT 



.j: 



DATA BUS ' BIDIRECTIONAL BUFFER 



I 1 

I STATUS 



^^^^^^ 



LATCH 
AND 
PAGE 



J BITS LATCH 



■ H-FLAG 
. I-FLAG 
. R-FLAG 

■ D-FLAG AD12 - 15 



NADS 
NRDS 



ADDRESS 
BUS 



UNIDIRECTIONAL BUFFER 



^M "OM C 



^ 



::>{ 



CONTROL 
STROBES 



UNIDIRECTIONAL BUFFEft 



■yi 



g^':!fJB^^sdV^g^-.:V^>M^-^!':iHa;^""' ■^''^qm^-i'i'-^'^r'^ 



CONTROL FLAGS AND 



Y UNIOIRECTIOKlAL BUFFth , SERIAL OUTPUT 



:^i 



C 



. J SENSE AND 
SERIAL INPUT 



EXTERNAL 
DEVICES 
AND/OR 
I/O PORTS 
(MILE. 8212. 82551 



Figure 3-13. An SC/MP System Showing Typical Support Devices that may be Required 



As we mentioned earlier, the SC/MP output lines cari each drive one TTL load. Some systems, BUFFERING 
especially those which utilize low-power external devices, may not require any buffering. When SC/MP 
buffiaring is needed, it can be provided using standard logic devices. The only area that re- BUSSES 
quires any special attention is when you are buffering the data lines: since these lines are 
used both for input and output of ddta, you must provide bidirectional control of these buffering devices. Figure 
3-14 shows one easy method of implementing bidirectional buffers for the SC/MP data lines using 8216 bidirec- 
tional bus drivers. (The 8216 is a support device from the 8080 family and is described in Chapter 4.) The SC/MP 
NRDS signal is inverted and used to provide directional control of the buffers. When the SC/MP is performing a read 
operation, NRDS is output low: this causes the contents of the system Data Bus to be gated through the buffers and 
onto the SC/MP data lines. At all other times, NRDS is high and whatever is on the SC/MP data lines is passed onto the 
system Data Bus. 



3-29 



DEMULTIPLEXING 
THE SC/MP 
DATA BUS 



If you need toiisp tKe four most significant address bits (AD12-AD15) for page 

select functions or. if you are going to mal<e use of the I/O cycle status information 

that SC/MP outplits; ybij must demultiplex this information from the SC/MP data 

lines. The most straightforward way of doing this is to use D-type flip-flops or data 

registers with the SC/MP NADS signal as the clock pulse. Here are some standard 7400 family devices that might 

be used: , . 

- 7475 Double 2-Bit Gated Latches with Q and Q Outputs 

- 7477 Double 2-Bit Gated Latches with Q Output Only 

- 74100 Double 4-Bit Gated Latches 

- 74166 Dual 4-Bit Gated Latches with Clear 

- 74174 Hex D-Typife Fllp-Flops with Common Clock and Clear 

- 741 75 Quad D-Type Flip-Flops with Common Clock and Clear 

Some of these devices require that the NADS signal be inverted to provide the necessary clocking signal. Remember, 
though, that the SC/MP address and status information is valid during both the leading edge (high-to-low transition) 
and trailing edge (low-to-high transition) of NADS: this generally simplifies the demultiplexing operation. 

Another method of demultiplexing the address bits from the data lines is to use address decoding devices that 
are clocked by the NADS signal and provide latched outputs. These latched outputs can then be used as the 
page select signals (or device select signals) during I/O cycles. 



DBO 
DBl 
0B2 
DB3 



SC/MP 



DBA 
DBS 
DB6 
DB7 

NRDS 



-0- 



H 



^ 



8216 



DIEN 



hC 



-O 



-C5 



12 



8216 



CS 



ys 1 



F"^ 



10 



13 



10 



13 



DBO ^ 




DBl 




DB2 




DB3 






^ SYSTEM 


. 


f DATA BUS 


DB4 




DB5 




DB6 




DB7 





Figure 3-14. SC/MP Data Lines Buffered Using 8216 Devices 



3-30 



< 

111 

Z 
DC 

o 

ca 

CO 

o 

< 

Q 

< 



USING OTHER MICROCOMPUTER SUPPORT 
DEVICES WITH THE SC/MP CPU 

There is nothing to prevent SC/IVIP from using silpport devices from other microcomputer "families". We have 
alreac^y shown one simple example — the use of 8216 bidirectional bus drivers to buffer the SC/MP data liries. 
The SC/MP CPU provides numerous control signals which allow general-purpose microcomputer support 
devices to be included in an SC/MP system. We will now describe a couple of specific examples of how this can 
be done — these examples will serve as guidelines for interfacing SC/MP to other support devices. 

The Microprocessor Interface Latch Element (MILE) is a support, device from t^e PACE 
microcomputer family arid is described in detail in Volume III. The MILE can be used to pro- 
vide an 8-bit, bidirectional I/O port in an SC/MP system as shown in the figure below. 



Derive CS from • 
Address Bus 



Data to/from 
SC/MP 



THE PACE 
MILE USED 
IN AN SC/MP 
SYSTEM 



From 
SC/MP CPU 



NRDS 







DBO^ 


PO 














I MILE 
DB7 
DIN2 


P7 

PIN 






^ n 






-»-0 






D0UT2 






I 


DIN1 


POUT 






t 


D0UT1 







Datd to/from 
external logic 



External logic must 
generate these control signals 



The chip select (CS) signal must be derived from the Address Bus and could consist of a single address line, a page 
select signal, or the output of address decoding logic. Remember that the SC/MP CPU does not differentiate between 
memory and I/O devices: it treats the MILE simply as a memory location. 

Directional control of th e MILE is provided by the SC/MP read strobe (NRDS) and write strobe. (NWDS) signals. NRDS is 
connected to the MILE's D0UT2 input signal: when NRDS and CS are both low, the contents of the MILE's data latches 
are g ated out onto thejSC/MP data lines for input to the CPU. The SC/MP NWDS signal is connected to the MILE's 
DIN2 input: when NWDS and CS are both low, the data output on the SC/MP data lines is latched into the MiLE. 

In the figure above, the MILE's DIN1 and D0UT1 signals are continuously enabled by connecting them to +5V. 
An alternate method of using these two signals woUld be to connect them to addre^b lines in order to simplify 
the address decoding requirements of the SC/MP system as shown in the figure below. 

In this example, data transfers between the MILE and SC/MP are enabled when address bit 1 1 (AD1 1) is a zero 
and AD10 is a one. This figure also shows the two handshaking signals (STD and STP) provided by the MILE. 
These signals can be applied to the SENSEA or SENSES inputs to SC/MP to implement simple I/O handshaking 
schemes. 



From 

SC/MP 

CPU 




Data to/from 
external logic 



External logic must generate 
^ these control signals 



TO SC/MP 
SENSE INPUTS 



3-31 



The 8212 I/O port from the 8080A microcomputer family is a device sllnilar to the 
MILE: the only difference is that while the MILE can operate bidirectioridlly, the 8212 is 
unidirectional. The signal connections required to use the 8212 with SC/MP are quite sim- 
ple: 



THE 8212 
I/O PORT 
USED IN 
SC/MP 
SYSTEMS 




-External logic strobes 
data into latches 



Tie MD to Ground. Now STB clocks 
latches and'oSI, DS2 enable buffers 



The connections shown here use the 8212 as an input port with handshaking logic provided. When the external 
logic latches data into the 8212 using the STB signal, the INT signal goes low; this signal can be applied to the SC/MP 
SENSEA or SENSES input to inform the CPU that input data is ready. SC/MP would then execute.a service routine pro- 
gram that would include an instruction to read data from the input port. This instruction would send out the input 
port's address, thus generating the DS2 signal, and then gate the latched data onto the CPU data lines when the NRDS 
signal is generated. When the latched data is read out of the 821 2, the INT signal returns high to complete the transac- 
tion. This sequence is summarized by the following timing diagram: 



DIO - DI7 



STB 



DS2 

DS1 (NRDS) 
DOG - D07 




TU ,, ^, Data latched by external logic 



Sense input 
to SC/MP CPU 




Latched data gated onto 
SC/MP data lines 



3-32 



Using the 8212 as an output port in an SC/MP system requires a simple reversal of the 
connections we described in the preceding example. 



THE 8212 USED 
AS AN OUTPUT 
PORT IN AN 
SC/MP SYSTEM 



< 
o 
< 

@ 



Data from 

SC/MP 

CPU 



NWDS 
(from SC/MP) 



Derived 
from Address lines 



^. 


DIO 




DOO 





[ 




0^7 
DSi 


8212 


D07 








STB 
















DS2 




MD 


( 


•— 











Data to external 
logic 



Tie to Vqc. Now DSI and DS2 clock 
latches and buffers are always enabled 



With this arrangement, data from the CPU will be loaded into the 821 2 latches when the required address is generated 
to apply a high to DS2 and SC/MP outputs the NWDS strobe signal. Data that is latched into the 821 2 is immediately 
gated out onto DOO - D07 and presented to external logic. 

We will conclude our discussion of support devices that may be used with SC/MP with the following observa- 
tion. The MILE and 8212 devices, which we have used as examples, are both relatively simple support devices. 
However, more complex general-purpose support devices are usually no more difficult to interface to an SC/MP 
CPU. In fact, the interface is often simpler, from a hardware point of view, because such things as mode control 
are handled by software. 



3-33 



DATA SHEETS 

This section contains specific electrical and tinning data for both the SC/MP and SC/IViP II (INS8060). 



z 

EC 

o 

CO 
CO 

o 

< 

Q 
< 

® 



3-D1 



SC/MP 



applications absolute maximum ratings 

■ Test Systems and Instrumentation ■ Process Controllers Voltage at Any Pin Vss + 0.3 V to Vss - 20V 
- Machine Tool Control ■ Terminals Operating Temperature Range 0°C to +70°C 
. Small Business Machines - Traffic Controls Storage Temperature Range -65°C to +150°C 

■ Word Processing Systems ■ Laboratory Controllers , . -,- ,,- ■ . • ,« .1 or^/^o,.> 

. .^ „,...^ Lead Temperature (Soldermg, 10 seconds) 300 C 

■ Educational Systems ■ Sophisticated Games 

■ Multiprocessor Systems ■ Automotive 

electrical characteristics (Ta = o°c to +7o°c, vss = +5v ± 5%, vqg = -7v ± 5%) 


Parameter | Conditions { Min. | Typ.* | Max. | Units 


INPUT SPECIFICATIONS 


ENIN, NHOLD, NRST, SENSE A, 
• SENSE B, SIN, DB0-DB7 
(TTL Compatible) (Note 2) 

Logic "1" Input Voltage 




vss-1 




Vss + 0.3 


V 


Logic "0" Input Voltage 




Vss - 10 




0.8 


V 


Pullup Transistor "ON" Resistance 
(Note 2) 


V|N = (VSS-1)V 




7.5 


12 


kn 


Logic "0" Input Current 


V||M = 0V 






-1.6 


mA 


BREQ(Note3) 

Logic "1" Input Voltage 




Vss-1 




Vss + 0.3 


V 


Logic "0" Input Voltage 








0.8 


V 


XI, X2 (Note 4) 

Logic "1" Input Voltage 




3.0 




Vss + 0.3 


V 


Logic "0" Input Voltage 








0.4 


V 


Logic "^" Input Current 


V|N = 3.0V 






5.0 


mA 


Logic "0" Input Current 


V||M = 0.4V 


-5.5 






mA 


Input Capacitance 

(All pins except Vgg and Vss) 








10 


pF 


Supply Current 

IGG / See Typical Plot of \ 

Igg 1 Normalized Iqg [and \ 

\ ISSl Versus Ambient 1 

\Temperature on page 6. / 


Ta = 0°C, loads on all outputs: 

ISINK= 1-6mA 
/ See diagram, Simulated \ 
\Current Load, on page 6./ 




100 
90 


135 
125 


mA 
mA 


OUTPUT SPECIFICATIONS 


BREa{Note3) 

Logic "^" Output Current 


V0UT=(VSS-1)V 


-2.0 






mA 


Logic "0" Output Current 


vgg< VquT^Vss 






±10 


ma 


External Load Capacitance 








50 


pF 


All Other Outputs 

Logic "1" Output Voltage 


IQUT = -80/jA 
lOUT = -2OO11A 


Vss-1 

2.4 






V 
V 


Logic "0" Output Voltage 


'out = 1-6mA 






0.4 


V 


Logic "0" Output Current 


VOUT = -0.5V 






4.0 


mA 


Logic "0" Output Voltage 


'out = 0mA (unloaded) 


-3.0 


-0.7 




V 


TTyplcal parameters correspond to nominal supply voltage at 25°C. 



Data sheets on pages 3-D2 through 3-D1 1 reproduced by permission of National Semiconductor Corporation. 



3-D2 



SC/MP 

electrical characteristics 



(Ta = C to +70°C, Vss = +5V ± 5%, Vgg = -7V ± 5%) (continued) 



Parameter 



Conditions 



IVIin. 



Typ. 



IVIax. 



Units 



O 

DO 
CO 

O 

< 

Q 
< 

@ 



TIMING SPECIFICATIONS (Note 5) 












Tx (Notes 4 and 6) 




1.0 




10.0 


Ais 




820pF ± 10% across XI & X2 


1.0 




4.0 


MS 


^res 


crystal witii equivalent series 
resistance < 600 J2 


900 




1000 


kHz 


Address and Input/Output Status 
(See figures Band 6.) 

Tdi (ADS) 




(3Tx/2)-150 


3Tx/2 


(3Tx/2) + 200 


ns 


Tw (ADS) 




(Tx/2) - 250 






ns 


Ts(ADDR) 




(Tx/2) - 300 






ns 


Th (ADDR) 




30 


50 




ns 


Ts (STAT) 




(Tx/2) - 300 






ns 


Th (STAT) 




30 


50 




ns 


Data Input Cycle (See figure 5.) 
Td(RDS) 




-80 


-50 




ns 


Tw(RDS) 




(3Tx/2) - 400 






ns 


Ts(RD) 




300 






ns 


Th(RD) 











ns 


tacc (RD) 




2Tx - 400 






ns 


Data Output Cycle (See figure 6.) 
Td (WDS) 




Tx - 250 






ns 


Tw (WDS) 




Tx - 250 






ns 


Ts (WD) 




(Tx/2) - 300 






ns 


Th (WD) 




60 


100 




ns 


Input/Output Cycle Extend 
(See figure 7.) 

Ts(HOLD) 




300 






ns 


Tdi (HOLD) 








300 


ns 


Td2(H0LD) 








500 


ns 


Tw(HOLD) 








oo 


ns 


Bus Access (See figure 4.) 
Td (ENOUT) 








300 


ns 


Td2 (ADS) 




(Tx/2) - 350 




Tx + 500 


ns 



OUTPUT LOAD CAPACITANCE 



External Load Capacitance 



75 



pF 



Note 1 : Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and 

should be limited to those conditions specified under electrical characteristics. 

Note 2: Pullup transistors provided on chip for TTL compatibility. 

Note 3: BREQ is an input/output signal that requires an external resistor to Vqq or ground. 

Note 4: Xi and Xj are master timing inputs that are normally connected to a l-megahertz crystal or an external capacitor to control the frequency 

of the on-chip oscillator. 

A hermetically sealed quartz crystal is recommended. The crystal must be a series-resonant type and its equivalent series resistance must not exceed 

600 ohms. Suppression of third harmonic oscillations may be required depending on the characteristics of the crystal. Typically, a 500- picofarad 

capacitor across pin Xi or X2 and an AC ground minimizes third harmonic effects. 

If use of an external oscillator is desired, the circuit shown in figure 3 or an equivalent may be used. 

Note 5: All times measured from valid Logic "0" or Logic "1" level. 

Note 6: T^ is the time period for one clock cycle of the on-chip or external oscillator. Refer to paragraph titled Timing Control for detailed 

definition. 

•Typical parameters correspond to nominal supply voltage at 25° C. 



3-D3 



SC/MP 

DRIVERS AND RECEIVERS 

Equivalent circuits for SC/MP drivers and receivers are 
shown below. All inputs have static charge protection 
circuits consisting of an RC filter and voltage clamp. 
These devices still should be handled with care, as the 
protection circuits can be destroyed by excessive static 
, charge. 



NRST , 

CONT I ipJ 

r,. V> — I — Lj — ^L 

»SS V 




SC/MP Driver and Receiver Equivalent Circuits 



SUPPLY CURRENT DATA 

Below are the two diagrams referenced from the para- 
metric specification for the supply current, page 2. 




•INCLUDES JIG CAPACITANCE. 

Simulated Current Load 



i= 0.4- 
B 0.2 ■ 



-20 20 40 60 70 BO 100 

AMBIENT TEMPERATURE (°CI 

TYPICAL PLOT OF NORMALIZED IGG (AND Iss) 

VERSUS AMBIENT TEMPERATURE 

DC POWER -IGG-VCG* Iss -VSS 



B. BREQ, ENIN, and ENOUT Timing 



— ?? 



V^.^^ 



® 



A 



— J? li H h^ ' 

To (ENOUT)-*-| |-*- -»-| [-•-Td (ENOUT) j 



V 



\ 




Note 1: ENOUT goes high to indicate that SC/MP was granted access to bus (ENIN high) but is not using bus. 

Note 2: ENOUT goes low in response to low ENIN input. 

Note 3: SC/MP generates bus request; bus access not granted because ENIN low. 

Note 4: ENIN goes high. Bus access now granted and input/output cycle actually initiated. If ENIN is set low while SC/MP 

has access to the bus, the address and data ports will go to the high-impedance (TRI-STATE®) state, but BREQ will remain 

high. When ENIN is subsequently set high, the input/output cycle will begin again. 

Note 5: I/O cycle completed. ENOUT goes high to indicate thgt SC/MP granted access to bus but not using bus. If ENIN had 

been set low before completion of input/output cycle, ENOUT would have remained low. 

Note 6: ENOUT goes low to indicate that system busses are available for use by highest-priority requestor. 

FIGURE 4. Bus Access Control 



3-D4 



SC/MP 



< 

ui 
Z 
oc 
o 
m 

(0 

O 

< 
o 
< 

@ 



A 



-Tdi (ADS)- 



-H^|-<Tw (ADS)*^ 



r 



|-*-Ts( 



■^J^mx ! I 



ADDRESS VALID 



Ts'(STAT)- 



I ADDRESS 
I AND STATUS 



-<-Th (STAT) 

7777777/^ 



I-Th (AOOR) 



DATA 
VAIID 



y/////^AV7y 



'y/////////A 



|-«To (ROS) 



I -^1 

I I 



'M^ 



n-TH( 



'fW 



'HlGHZVyC- 

^//7/7//, 



-tacc(RO)- 



-•>j-*Ts (ROl^l 



-TwIRDSI- 



Note: Timing is valid when ENiN is wired high or is set high before BREQ is set high by SC/MP; see figure 4 for NADS 
timing when ENIN is set high after BREQ. 

FIGURE 5. SC/MP Data Input Timing 



^ 



-Toi (ADS)- 



— >.|-<Tw(ADS)»-| 
|-*Ts(ADDR) I 



ADtiAOOo'/Z/^moHZ^^^^ 



I I 
I I 



ADDRESS VALID 



2^ 



^Th (STAT) 



I ADDRESS 
/y\ I AND STATUS 



X 



hTH(ADOR) 



WRITE DATA VALID 



|-* Ts (WD) >\ —*-\ -*-Th (WD) 



V^ 



V77777, 
7/////y 



-[-Tn((WDS) 



FIGURES. SC/MP Data Output Timing 



3-D5 



SC/MP AND INS8060-SC/MP II 



/ 



\ 



-TD2(H0LD)- 



\ 



/ 



l-*-Tw(H0LO)*-I I 
I I 



> a — ' I -. 

. ^ |Ts(HOLD)| ^ i 



Note: Dashed trailing edge of NRDS/NWDS Indicates normal strobe timing when NHOLD is not active. 

FIGURE 7. Extended Input/Output Timing , 



Applications Absolute Maximum Ratings (Note d 


■ Machine Tool Control ■ Terminals ' ' '■' ^o« -,«o^ 
. Small Business Machines - Traffic Controls Operating Temperature Range C to +70 C 

. Word Processing Systems ■ Laboratory Controllers Storage Temperature Range. ,:. - -65°G to +150°C 


■ Educational Systems ■ Sophisticated Games 

■ Multiprocessor Systems ■ Automotive Lead Temperature (Soldering 

DC Electrical Characteristics(TA = o°c to +7o°c, vcc = +5v ± 5%) 




. 300°C 




Parameter 


Conditions 


Min. 


Max. 


Units 


INPUT SPECIFICATIONS 


All Input Pins Except Vqc and GND 
Logic "1" Input Voltage 




2.0 


Vcc 


V 


Logic "0" Input Voltage 




-0.5 


0.8 


V 


Input Capacitance 

(All pins except Vqc and GND) 






10 


pF 


Supply Current 

"cc 


Ta = 25°C 
outputs unloaded 




45 


mA 




Ta = 0°C 
outputs unloaded 




50 


mA 


OUTPUT SPECIFICATIONS j 


"TRI-STATE®" Pins (NWDS, NRDS, 
DB0-DB7,AD00-AD11) 
Logic "1" Output Voltage 


IOUT = -''00mA 


2.4 




V 


Logic "0" Output Voltage 


l0UT= 2.0mA 




0.4 


V 


NADS, FLAG - 2, SOUT, NENOUT 
Logic "1" Output Voltage 


iout = -iooma 


vcc-1 




V 


Logic "1" Output Voltage 


l0UT = -1mA 


1.5 




V 


Logic "0" Output Voltage 


l0UT = 2.0mA 




0.4. 


V 


NBREQ{Note2) 

Logic "0" Output Voltage 


IOUT = 2.0mA 




0.4 


V 


Logic "1" Output Current 


< VOUT < Vcc 




±10 


AiA 


XOUT 

Logic "1" Output Voltage 


IOUT = -100juA 


2.4 




V 


Logic "0" Output Voltage 


l0UT= 1.6mA 




0.4 


V 



3-D6 



INS8060-SC/MP II 



AC Electrical Characteristics [ta = o°c to +7o°c, vcc = +5v ± 5%, 1 ttl Load (Note 3)] 


Parameter 


Conditions 


Min. 


Max. 


Units 


fx 




0.1 


4.0 


MHz 


R = 240n ± 5% (figure 2B) 
C = 300pF±10% 


2.0 


4.0 


MHz 


Tc (Note 4) 




500 




ns 


Microcycle 




1 




Ais 


External Clock Input (see figure 2A) 
Two 




120 




ns 


Twi 




120 




ns 


XOUT/ADS Timing Relationship 
(see figure 3) 
Th (ADS) 




100 


225 


ns 


Address and Input/Output iStatus 
(see figures 5 and 6) . 
Tdi (ADS) 






3TC/2 


ns 


Tw(ADS) 




(Tc/2) - 50 




ns 


Ts (ADDR) 




(Tc/2) -165 




ns 


Th (ADDR) 




50 . . 




ns 


Ts (STAT) 




(Tc/2) -150 




ns 


Th (STAT) 




50 




ns 


Th(NBREQ) 









ns 


Data Input Cycle (see figure 5) 
Td(RDS) 









ns 


Tw(RDS) 




Tc + 50 




ns 


Ts(RD) 




175 




ns 


Th (RD) 









ns 


Tacc (RD) 




2Tc - 200 




ns 


Data Output Cycle (see figure 6) 
Td (WDS) 




Tc-50 




ns 


Tw (WDS) 




Tc 




ns 


Ts (WD) 




(Tc/2) -200 




ns 


Th (WD) 




100 




ns 


Input/Output Cycle Extend 
(see figure 7) 
Ts(HOLD) 




200 




ns 


Tdi (HOLD) 




130 


275 


ns 


Td2(H0LD) 






350 


ns 


Tw(HOLD) 






oo 


ns 


Th (HOLD) 









ns 


Bus Access (see figure 4) 
Td (NENOUT) 






150 


ns 


Td2(ADS) 




Tc/2 


3TC/2 


ns 


Th(NENIN) 









ns 


Output Load Capacitance 
XOUT 






30 


PF 


All Other Output Pins 






.75 


pF 


Note 1 : Maximum ratings indicate limits beyond which damage may occur. Continuous operation at these limits is not intended and should be 

limited to those conditions specified under electrical characteristics. 

Note 2: NBREQ is an input/output signal that requires an external resistor to V(^q. 

Note 3: All times measured from valid Logic "0" level = 0.8 V or valid Logic "1" level = 2.0 V. 

Note 4: Tc is the time period for two clock cycles of the on<hip or external oscillator (Tg = 2/fx). Refer to paragraph titled Timing Control 

for detailed definition. 

Note 5: All times measured with a 50% duty cycle on the external clock. 



3-D7 



INS8060-SC/MP II 



The time interval of a microcycle is four times the period of the oscillator; that is: 
period of one microcycle = 2Tc 

Tc = 2(-l-) = 2(-!-) = 2 (.-!—) 
fosc fres ^XIN 

where: 

Tc = time period for two cycles of on-chip or external oscillator 

fosc ~ frequency of on-chip oscillator 

fres - resonant frequency of crystal connected between XIN and XOUT pins 

fXiN = fi'spufincy of external clock applied to XIN pin 



A. External Clock Input 



>-\ 



OPTIONAL 
DRIVER 
OPTIONAL ,* 

SYSTEM- hJ I H XOUT 

CLOCK . M 



XIN 

SC/MP 



EXTERNAL CLOCK PARAMETERS 



Utwi^ 



-Two — -] 



B. Resistor-Capacitor Feedback Network 



■ r 



OPTIONAL 
SYSTEM 
CLOCK 



NOTE; 100 <R<2k 



Typical Oscillator Frequency 
vs RC Time Constant 




0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 
CLOCK PERIOD (l/fMHz) 



FIGURE 2. Frequency Control Networks for On-Chip Oscillator 



C. Crystal with Low-Pass Filter (Above IMHzl 



■ Rp . 

— AAAr— I OPTIONAL 
DRIVER 

HDI-Ll--:::-- 



OPTIONAL 

■ SYSTEM 

CLOCK 






Suggested values for Crystal with Low-Pass Filter Network. 

Crystal ;iRp Ci Ri 

2MHz lOOkn 56pF . 1 kn 

3.58IVIHZ lOOkn 27pF 1 kn 

4MHz lOOkn 27iDF 1 kfi 

XTAL is parallel resonant with maximum series resonance equal 
to 1 kn. 

D. Crystal with Low-Pass Filter (1MHz or Below) 




OPTIONAL 
DRIVER 
k,. OPTIONAL 

I 'j>. SYSTEM 

»' CLOCK 




FIGURE 3. XOUT/NADS Timing Relationship 



3-D8 



INS8060-SC/MP II 



< 

da 

m 
Z 
cc 
o 
m 

o 

< 
o 

< 

@ 




B. NBREQ.NENIN, and NENOUT Timing 

Note 1: NENOUT Is always high while SC/MP is actually using bus; that is, NENIN input and NBREQ output are low. 

Note 2: When SC/MP Is not using bus (NBREQ output or NENIN Input high), NENOUT is held in same state as NENIN input. 

Note 3: NENOUT goes {ow to indicate that SC/MP was granted access to bus (NENIN low) but is not using bus. 

Note 4: NENOUT goes high In response to high NENIN input. 

Note 5: SC/MP generates bus request; bus access not granted because NENIN high. 

Note @: NENIN goes |ow. Bus access now granted and input/output cycle actually initiated. If NENIN Is set high while SC/MP has access to 

the bus, the address and data ports will go to the high-impedance (Tri-State®) state, but NBREQ will remain low. When NENIN is subsequently 

set low, the input/oVjtput cycle will begin again. 

Note 7: Input/output cycle completed. NENOUT goes low to indicate that SC/MP granted access to bus but not using bus. If NENIN had been 

set high before completion of input/output cycle, NENOUT would have remained high. 

FIGURE 4. Bus Access Control 



3-D9 



INS8060-SC/MP II 



Th (NBREO)-p« ►{ 



- TDt(ADS) ^■♦Tw (ADSI*-| 



*on.«oo^^^ 



|-*TS( 



I I 
I I 



ADDRESS VALID 



4IRH 7 ^/j 



y/SL 



I ADDRESS 
I AND STATUS 



|-*-Th(ADOR) 



V777y 



^ }-*Td(RDSI I ».| (-J-THtRO) 



V///7/////. 



7777777 



\ 



V 



Ty^wKwz^/. 



//////// 



-taccIhdi- 



■j-*Ts (ROI»-| 



Note: Timing is valid when NENIN is low before NBREQ is set low by SC/MP; see figure 4 for NADS timing when NENIN is 
set low after NBREQ. 



FIGURE 5. SC/MP Data Input Timing 



-Tdi(ADS)- 



— »-|-*Tw(ADS)*-] 
|-*-Ts(ADDR) I 




I I 
I I 



ADDRESS VALID 



Ts (STAT)-*-| |-«— —*^ 



I ADDRESS 
/A I AND STATUS 



|-*Th (STATI 



WRITE DATA VALID 



Ts(WD)- 



■«^m^ 



^ f 



\*- 



-Td (WDS)- 




-Tw (WDS) 



FIGURE 6. Data Output Timing 



3-D10 



INS8060-SC/MP il 



NO EXTENSION OF INPUT/OUTPUT CYCLE 



/ 



7 



r 



NHOIO CAN CHANGE 



\ 



ThIHOLOI 
l-« Ts(HOLDI >-l U .-i 



/ 



NHOLD CAN CHANCE 



NHOID CAN CHANGE 



\ 



EXTENSION OF INPUT/OUTPUT CVCLE 



\ 



-TslHOlD) ►! ToilHOLD) 




o 

< 

o 

< 

@ 



Note 1: In order to extend the input/output cycle, NHOLD must remain low until the point where NRDS/NWDS would have made i 
low-to-high transition with NHOLD inactive. Dashed line indicates the trailing edge of NRDS/NWDS when NHOLD is not active. 

FIGURE?. NHOLD Timing 



3-D11 



Chapter 4 
THE 8080A 



u The 8080A is the most widely known of the microcomputers described in this book; as such, it becomes the 

H frame of reference in many peoples' minds as to what a microcornputer should be. 

u The 8080A CPU is the direct descendant of the 8008, which was developed to Datapoint's specification for a 

u) device that would provide intelligent terminal data processing logic. 

^ It should be borne in mind that the 8080A was designed as an enhancement of the 8008, at a time when no 

lu definable microcomputer user public had established itself: therefore, many of the design features in the 8080A 

§ can be looked upon as astute shots in the dark. The success of this microcomputer is due either to the farsighted genius 

g of its designers, or to the fact that the power of most microcomputers so overwhelms the needs of microcomputer ap- 

« plications, that CPU design becomes almost irrelevant when compared to product costs and product availability. 

S An enhanced version of the 8080A, the 8085, is now available. The 8085 is described along with its support 

Q devices in Chapter 5. Note that in many cases it will be possible to use 8080A support devices with the 8085 CPU. 

** You are unlikely to use 8085 support devices with the 8080A; if your design is new enough to be looking at the 8085 

@ support devices, then in all probability you would be using the 8085 CPU in preference to the 8080A. 

There is also a family of one-chip microcomputers currently available from Intel only — the 8048 family. Where 
the 8085 is an enhancement of the 8080 with many similarities, the 8048 is a somewhat different product. The 
8048 devices are described in Chapter 6. 

The 8080A has more support devices than any other microprocessor on the market today. A few of these support 
devices are specific to the 8080A; however, the majority of them are used just as easily with almost any 
microprocessor. Only devices specific to the 8080A are described in this chapter; devices that can be used with any 
microprocessor are described in Volume III. The following is a list of 8080A support devices; a • at the left margin 
identifies a device described in this chapter, while an * in the left margin identifies a device which is described 
in Volume III. 

• The 8080A/g080A CPU 

• The 8224 System Clock Generator and Driver. This device generates timing signals for the entire 8080A 
microcomputer system. 

• The 8228 System Controller (SC). This device demultiplexes the data lines of the 8080A CPU which are used 
for bidirectional data transfer and to output control and status signals. 

'The 8251 and 8251 A Serial I/O Communication Interface, which provides a variety of synchronous and 
asynchronous serial data communication options. 

• The 8273 SDLC Protocol Serial I/O Controller. 

'The /iPD379 and the /aPD369. These devices provide synchronous and asynchronous serial I/O interfaces, 
respectively. 

' The 8255 and 8255A Parallel I/O interfaces, which provide programmable parallel I/O communication with ex- 
ternal devices. 

' The 8212 Input/Output port, which can be used as an address buffer/decoder, a priority interrupt arbitrator, or 
an I/O peripheral interface. 

' The 8257 Direct Memory Access control device, which enables data to be transferred between memory and 
external logic, bypassing the CPU. 

' The 8253 Programmable Timer, which is accessed as an I/O device to create delays and timed pulses. 

• The 8259 Priority Interrupt Control Unit, which arbitrates priority among eight interrupts and creates appropri- 
ate CALL instructions in response to an interrupt acknowledge. 

' The 8214 priority interrupt device, which allows a number of interrupt requests to be received and processed 
under program control. 

• The TMS 5501 Multifunction I/O Controller, which provides a variety of support logic functions. 

4-1 



* The 8205, 8216 and 8226 address buffer decoders, which provide the logic needed to decode address spaces 
out of the 8080A address lines. 

* The 8271 Programmable Floppy Disk Controller. This device provides a good deal of the logic needed to inter- 
face a floppy disk to a microprocessor. 

* The 8275 Programmable CRT Controller. This device provides a great deal of the logic needed to interface in- 
dustry standard CRT terminals to a microprocessor. 

Table 4-1 lists the sources for each of the products described. Device numbers in each colunnn are the individual 
nnanufacturers' device numbers, which may differ for the same device. 

Table 4-1. Devices of the 8080A Microcomputer Family 



DEVICE 


AMD 


INTEL 


NEC 


Tl 


NS 


SIGNETICS*** 


8080A 


9080A" 


8080A 


8080A 


TMS 8080A 


8080A 


8080A 


8224 


8224 


8224 


8224 


SN74LS424 


8224 


8224 


8228 


8228/38 


8228/38 


8228/38 


SN74S428 


8228/38 


8228/38 


8251 


9551* 


8251 


8251 
MPD379 
/MPD369 








8255 


9555* 


8255 


8255 




8255 




8214 




8214 


8214 








8216/26 


8216/26 




8216 








8205 


25LS138* 


8205 










8212 


8212 


8212 


8212 


SN74S412 






8253 




8253 


8253 








8259 




8259 


8259 








8257 




8257 


8257 








TMS 5501 








TMS 5501 







* Some parameters vary, but pin-for-pin compatible 

** Five CPU options are available offering clock speeds as fast as 250 ns, and wide temperature ranges 
*** Signetics second sources National Semiconductor products 

Companies manufacturing these microcomputer devices are: 

INTEL CORPORATION 

3065 Bowers Avenue 

Santa Clara, CA 95051 

ADVANCED MICRO DEVICES 

901 Thompson Place 

Sunnyvale, CA 94086 

TEXAS INSTRUMENTS INC 

P.O. Box 1444 

Houston, TX 77001 

NEC MICROCOMPUTERS INC 

5 Militia Drive 

Lexington, MA 02173 

NATIONAL SEMICONDUCTOR CORP 

2900 Semiconductor Drive 

Santa Clara, CA 95050 

SIGNETICS 

81 1 East Arques Avenue 

Sunnyvale, CA 94043 

SIEMENS A.G. 

Components Group 

Balanstrasse 73, D8000 

Munich 80, West Germany 

Siemens is manufacturing the 8080A family of devices in Europe with the active support of Intel. AMD is an 
authorized second source; however, most of their products were developed prior to the second source agree- 
ment. All other 8080A manufacturers are unauthorized. In consequence, some differences exist between Intel 



4-2 



and second source parts; differences are in some cases designed by the second source manufacturer, while in 
other cases differences are accidents. Differences we know about are described. 

The 8080A uses three levels of power supply: +5V, +12V and -5V. 

Using a 500 ns clock, instruction execution times range from 2 to 9 /xsec. 

Q All 8080A devices have TTL compatible signals. 

lU 

I THE 8080A CPU 

oe 
o 
o 
z Of the 8080A devices available on the market, the NEC 8080A is the only one that differs significantly from the 

(fl Intel 8080A. The NEC 8080A is advertised as "an upward enhancement". Some of the NEC 8080A upward enhance- 
\fi ments result in programs written for Intel 8080A not executing correctly on the NEC 8080A; therefore you should 
^ check carefully for incompatibilities when using the NEC 8080A. NEC now manufactures an exact 8080A reproduc- 
es tion as well; be sure you select the correct product if you buy from NEC. 

< Most differences between Intel and second source 8080A devices pertain to maximum clock frequency, environmental 
«B constraints and electrical characteristics. For details see the data sheets at the end of this chapter. 

lU 

z Functions implemented on the 8080A CPU are illustrated in Figure 4-1 ; they represent "typical" CPU logic. The 

o 8080A has an Arithmetic and Logic Unit, Control Unit, Accumulator and registers. 

o N-Channel, silicon gate MOS technology is used by all 8080A manufacturers. 

< The two most noticeable features of the 8080A CPU are the exclusion of clock logic and bus interface logic 
^ from the CPU chip. 

© The need for a separate clock logic chip simply reflects the fact that the 8080A was a relatively early microprocessor. 

Other microprocessors developed at the same time also required external clock logic. 

Bus interface logic must also be provided externally since the 8080A outputs an inadequate set of control signals. 
These control signals are augmented by instruction status information output on the Data Bus. External bus interface 
logic must combine the control signals with the instruction status signals to create an adequate Control Bus. 

These characteristics of the 8080A CPU are described in detail on the following pages. 

The 8085 CPU incorporates clock logic and bus interface logic onto the CPU chip. 

8080A PROGRAMMABLE REGISTERS 

The 8080A has seven 8-bit programmable registers, a 16-bit Stack Pointer, and a 16-bit Program Counter. These may 
be illustrated as follows: 

Program Status Word ) These two sometimes 
Primary Accumulator ) treated as a 16-bit unit 
Secondary Accumulators/Data Counter 
Secondary Accumulators/Data Counter 
Secondary Accumulators/Data Counter 
Stack Pointer 
Program Counter 

The A register is an 8-bit priman/ Accumulator. The remaining six Accumulator registers may be treated as six in- 
dividual, 8-bit secondary Accumulators, or else they may be treated as three, 1 6-bit Data Counters, which we will refer 
to as BC, DE, and HL registers. The 1 6-bit HL register is the primary Data Counter, and provides the implied memory ad- 
dress for most memory reference instructions; a limited number of memory reference instructions use the BC and DE 
registers as Data Counters. 

The 8080A uses a memory Stack, addressed by the Stack Pointer. 





P^W 




A 


B 


C 


D 


E 


H 


L 


SP 


PC 



4-3 



1 Clock Logic I 











808OA 






^^B 


8224 






WM^/. 


8228 








Figure 4-1. The 8080A CPU, 8224 Clock and 8228 System Controller. 
Forming a Three-Device Microprocessor 



8080A ADDRESSING MODES 

The memory addressing used by the 8080A is very straightforward; direct addressing and implied addressing are pro- 
vided. 

The most frequently used memory addressing mode is implied addressing, via the HL register. 
This was the only memory addressing mode available on the predecessor microcomputer, the 
8008.. 



8080A 

IMPLIED 

ADDRESSING 



4-4 



< 

< 



Register-register Move, and Register-register Operate instructions allocate three bits to specify one of eight registers; 
since there are only seven registers, the eighth code beconnes a memory reference specification, using implied address- 
ing via the HL register, as follows: 



3 2 1 

n 



• Bit No: 



D 



t: 



000 B specified 

001 C specified 
010 p specified 
Oil E specified 

100 H specified 

101 L sp>ecified 

1 10 Memory reference via HL 

1 1 1 A specified 



With one exception, direct addressing is the only addressing mode provided for Jump and 8080A 
Branch instructions; the exception is the instruction with the mnemonic PCHL, which provides a DIRECT 
jump using implied addressing. Direct addressing is also available for a limited number of ADDRESSING 

memory reference instructions. All direct addressing instructions are three bytes long; a • ., 
two-byte (16-bit) direct address is always specified. 

8080A ST ATMS 

The 8080A has a Status register with the following status flags: 

Zero(Z) 

Sign (S) 

Parity (P) 

Carry (C) 

Auxiliary Carry (Aq) 

SUB. present in the NEC 8080A only 

These status flags may be accessed by some instructions as a single Program Status Word (PSW). PSW bits are 
assigned as follows: 



7 65432 1 0- 

Isizlxj^lxIPJxicI 

f i V 



I Bit No. 



• Unassigned 

'SUB (NEC 8080A only) 



Instructions that access register pairs treat PSW and the Accumulator as a register pair. 

The 8080A uses its Sign status as described for the hypothetical microcomputer in Volume I, Chapter 7. 

The Carry status is not completely standard. When an addition instruction is executed, any car- 
ry out of the high-order bit causes the Carry status to be set to 1, while no carry causes the Carry 
status to be reset to 0. This is standard Carry logic, also known as Add Carry logic. When a 
subtraction instruction is executed, however, the Carry logic is inverted. 



CARRY 
STATUS 
BORROW 
LOGIC 



4-5 



A subtraction is actually the twos complement addition of the subtrahend to the minuend. The use of the Carry status 
is different: if there is a carry out of the high-order bit. then the Carry status is reset to 0; if there is no carry out of the 
high-order bit, then the Carry status is set to 1 . This philosophy is known as Borrow Carry logic and is used only during 
subtraction operations. Here are illustrations of the two philosophies: 



24 ic 
16A7 



Binary Twos 

Add Carry Logic 

No carry. 



\jt/ 



Complement 

Borrow Carry Logic 

No carry . 



-any ^ 



00 100 100| 
,11101001 



,00011100 
0101100 1. 



11111111' 

00100100 00011100 
1110 10 10 010 1100 1, 




Ones 


Twos 


Twos complement 


complement 


complement 


individual 


of high- 


of low- . 


bytes without 


order 


order 


regard to byte 


byte. 


byte 


order 



In a CPU which uses Add Carry logic, the twos complement of the low-order subtrahend byte is added to the minuend 
low-order byte. However, the ones complements of higher order subtrahend bytes are added to minuend bytes when 
the CPU executes a "Subtract with Carry". This logic adds the unaltered Carry status. This is equivalent to initially 
assuming that there is no carry from the lower order byte: if there is a carry from the lower order byte, then the ones 
complement addition is incremented. 

In a CPU which uses Borrow Carry logic, the twos complement of every subtrahend byte is added to every minuend 
byte, irrespective of whether we are dealing with the low-order or any other subtrahend byte. This is equivalent to 
assuming that there will always be a carry from the lower order byte — hence the twos complement add. If there is no 
carry, the sum" must be decremented. When a lower order byte borrows from the next high-order byte, there will be no 
carry; therefore, no carry causes the Carry status to be set to 1. However, the "Subtract-with-Carry" instruction 
subtracts the 1 Carry status from the result rather than adding it. 



AMD 9080A 

STATUS 

DIFFERENCE 



The Auxiliary Carry status is set and reset by the NEC 8080A following execution of any 
subtract instruction to correctly indicate whether a borrow from bit 4 occurred during the 
subtraction. The Intel 8080A uses the Auxiliary Carry at all times to indicate a carry out of bit 3 
following addition. The AMD 9080A always clears the Auxiliary Carry status following ex- 
ecution of a Boolean instruction; the Intel 8080A sometimes does and sometimes does not. 

8080A CPU PINS AND SIGNALS 

8080A CP.U pins and signals are illustrated in Figure 4-2. 

The 16 address lines A0-A15 output memory and I/O device addresses. These are tristate lines, and may be 
floated, giving external logic control of the Address Bus. 

The eight Data Bus lines DO - D7 are multiplexed, bidirectional data lines via which 8-bit data units are input 
and output, and on which statuses are output during the first clock period of any machine cycle: statuses on the 
Data Bus identify events which are to occur during the balance of the machine cycle, as described in Table 4-2. Like 
the address lines, the data lines are tristate. 

Remaining signals (excluding power and ground) may be divided into timing control. Data Bus definition, and in- 
terrupt control signals. 

These are the timing control signals: 

A device which cannot respond to a CPU access request within the allowed time interval 
extends the time interval by pulling the READY input control low. In response to READY low, 
the 8080A enters a Wait state, during which the CPU inserts an integral number of clock periods: 
WAIT is output high, and all operations are suspended within the CPU, but the address re- 
mains stable on the Address Bus. 

CPU logic can be stopped between the end of one instruction's execution, and the beginning of the next, by in- 
putting a high level on HOLD. This causes the CPU to float the Data and Address Busses, allowing external logic to ac- 
cess these busses, usually to perform direct memory access operations. 



8080A 
TIMING 
CONTROL 
SIGNALS 



4-6 



z 
cc 
o 

GO 
(A 
O 

< 

Q 

< 



The CPU responds to a HOLD request by outputting a Hold Acknowledge, HLDA, high; this signal can be used by 
external logic to identify the beginning of the time when the CPU has actually floated external busses, and external 
logic can take control of the microcomputer system. 

RESET is a typical reset signal; if held high for a minimum of three clock periods, it will zero the contents of all 
registers (excluding the status flags which maintain previous values), thus causing program execution to start with the 
instruction stored at memory location 0000. 

Two signals identify the condition of the Data Bus: 

When DBIN is output high, data from an addressed memory location, or I/O port, must be 
placed on the Data Bus; DBIN may be used as a data input strobe. 

WR is output low when data on the Data Bus is stable; WR may be used as a write strobe. 

The two interrupt control lines are INT and INTE. An external device requests an interrupt by 
inputting INT high. The CPU uses INJE to indicate whether interrupts are enabled or disabled. 



8080A 
DATA BUS 
DEFINITION 
SIGNALS 



8080A 
INTERRUPT 
CONTROL 
SIGNALS 



8080A TIMING AND INSTRUCTION 
EXECUTION 

An 8080A instruction's execution is timed by a complex sequence of MACHINE CYCLES each of which is sub- 
divided into CLOCK PERIODS. 



An instruction's execution may require from 1 to 5 machine cycles. Machine cycles are labeled 
MCI, MC2, MC3, MC4and MC5. ■ ' 

A machine cycle is made up of 3, 4, or 5 clock periods; the first machine cycle of an instruction 
must have 4 or 5 clock JDeriods. Clock periods are labeled Ti. T2, T3, T4, T5: 



8080A 

MACHINE 

CYCLES 



8080A 
CLOCK 
PERIODS 



MCI , MC^ MC3 MC4 MC^, 

ir2|T3|T4|T5|Tihr3|l4iTsri|T2|T3far5|Tl|T2|T3|T4|Tj^^ 



Where MC is shaded, the entire machine cycle is optional. Where T is shaded, the clock period is optional within its 
machine cycle. 



4-7 




PIN NAME 

•A0-A15 

•D0-D7 
SYNC 
. •DB|[^ 

♦READY 
■♦WAIT 

♦WR 

♦HOLD 

♦HLDA 

♦|NT 

♦INTE 

♦RESET 

^SS'^DD'^CC'^BB 
♦These signals connect to the System Bus. 



DESCRIPTION 

Address Lines 

Data Bus Lines 

Machine Cycle Synchronizer 

Data Input Strobe 

Data Input Stable 

CPU In Wait State 

Data Output Strobe 

Enter Hold State 

Hold Acknowledge 

Interrupt Request 

Interrupt Enable 

Reset CPU 

Clock Signals 

Power and Ground 



TYPE 
Output, Tristate 
Bidirectional, Tristate 
Output 
Output 
Input 
Output 
Output 
Input 
Output 
Input 
Output 
Inpu} 
Input 



Figure 4-2. 8080A CPU Signals and Pin Assignments 

CLOCK SIGNALS 

Two cloci<s, $1 and 3>2, provide the CPU with its tinning. 

Figure 4-3 illustrates the way in which clock signals $1 and 02 are used to generate a machine cycle consisting 
of five clock periods. A SYNC pulse identifies the first clock period of every machine cycle. 




Figure 4-3. A Machine Cycle Consisting of Five Clock Periods- 



4-8 



A 9-segment clock is specified for the 8080A where the $1 and $2 signals are generated out of 9 segments as 
follows; 



o 
m 

V) 

O 
< 

Q 

< 

@ 



*1 



<t>2 



The following altemat 



*i 



J 



<X>2 



*1 



J 



<t>2 



*! 



Jf 



*2 



<t>l 



J 



<t)2 



*1 



*2 



1 I 2 I 3 I 4 
I ' 
I I 

^l L_ 



5 I 6 
I 

I- 
I 



I I 

ve segmentations will also work 
1 



5 I 



\. 



7 I 8 I 9 I 

I ! I 

I I I 

I ! 



k 



y 



r 



t 



Irrespective of the segnnentation used, note that the total clock period time must remain the same. For example.^up- 
pose you have a 500 nanosecond clock; individual segments must be timed as follows: 

Number of Segments 9 876 5 4 

Duration of one segment 55.55 62.5 71.43 83.33 100.00 125.00 
(nanoseconds) 



4-9 



In summary, therefore, a clock period will normally have 9 segrpents. but may have 4, 5, 6, 7 or 8 segments. 

Note that the only time you ever need to know about clock segmentation is when you are creating your own 
clock signals. If you use the 8224 Clock Signal Generator (described later in this chapter) you can ignore clock signal 
segmentation- 
Clock periods T-], T2 and T3 of each machine cycle are used (with one exception) for memory reference opera- 
tions. During periods T4 and T5 functions internal to the CPU are executed. These two clock periods can be 
used by external logic for a limited number of approved operations that do not involve the CPU: 



rii^2hiiiiii 




' Operations internal to CPU 
■ Mennory reference operations 



The first three clock periods of the first machine cycle are always used to fetch an instruction from memory, and 

load it into the Instruction register. The first machine cycle always has at least four clock periods, with the Program 
Counter being incremented during T4: 



MCI 



I^T^ 



^-•^tmyimi^ 



Increment Program Counter 

Operations internal to CPU 
1 Instruction Fetch 



The CPU identifies the operations that will occur during every machine cycle by outputting 8080A 
status information on the Data Bus during clock period 72- External logic uses SYNC and the INSTRUCTION 

Ol pulse at the start of T2 to read status off the Data Bus. Timing is illustrated in Figure 4-4. STATUS 

If you are using an 8228 System Controller, it will decode status output on the Data Bus 
during T2. By combining this status information with the three control signals: WR, DBIN and HLDA, the 8228 System 
Controller is able to generate a set of bus control signals which will interface Industry standard memory devices and ex- 
ternal logic. 

If you are not using an 8228 System Controller, then you must provide external logic that decodes the Data Bus 
during <I>1 of T2. Your external logic must generate control signals which will be active during subsequent clock 
periods, at which time the Data Bus no longer holds status information. " 



<l>i 



<t»2 



Ti T2 T3 




in 'A r\ 


n 



SYNC 



Status on 
Data Bus 



J~^ 



Status 




J-\ 



Strobe to read status off Data Bus 
when <t>1 and SYNC are both high 



Figure 4-4. Status Output During T2 of Every 
Machine Cycle 



4-10 



z 
oc 
o 

CD 
(A 
O 

< 
o 

< 

@ 



Table 4-2 defines the statuses which may be output during clock period T2- Table 4-3 defines the way in which 
statuses should be interpreted to identify the various possible types of machine cycles. 

Table 4-2. Statuses Output Via the Data Lines During the Second 
Clock Cycle of an 8080A Machine Cycle 



SYMBOLS 


DATA BUS 
BIT 


DEFINITION 


HLTA 


D3 


Acknowledge signal for Halt instruction 


INTA* 


DO 


Acknowledge signal for INTERRUPT request. Signal should be used to gate a 
Restart instruction onto the Data Bus when DBIN is active. 


INP* 


D6 


Indicates that the Address Bus contains the address of an input device and 
the input device should be placed on the Data Bus when DBIN is active. 


OUT 


D4 


Indicates that the Address Bus contains the address of an output device and 
the Data Bus will contain the output data when WR is active. 


MEMR* 


D7 


Designates that the Data Bus will be used for memory read data. 


Ml 


D5 


Provides a signal to indicate that the CPU is in the fetch cycle for the first 
byte of an instruction. 


STACK 


D2 


Indicates that the Address Bus holds the pushdown stack address from the 
, Stack Pointer. 


WO 


, D1 


Indicates that the operation in the current machine cycle will be a WRITE 
memory or OUTPUT function (WO = 0). Otherwise a READ memory, INPUT 
operation, or interrupt or Halt acknowledge will be executed. 



"These three'status bits can be used to control the flow of data onto the 8080A Data Bus. 



Table 4-3. Statuses Output on the Data Bus for 
Various Types of Machine Cycle 



s 

M 

3 

a 

< 

Q 


Z 

o 

S 

K 
O 
u. 

Z 

CO 

3 

B 


TYPE OF MACHINE CYCLE 1 


z 

Ul 

1^ 

Z 

o 

=> 

Z 


a 

2 

oc 
>- 

E 
O 

UJ 


UI 

£ 

> 
a 
o 


5 

U] 

E 

u 

(0 


UJ 

i 

OT 


Q 

■ < 

UI 

E 

y- 

3 
a. 

z 


UJ 

t 

H 

3 
a. 
1- 

3 

o 


UI 

a 

Q 

l_ UJ 

Is 

E O 

K Z 
UJ 5^ 

2^ 


UJ 

a 
o 

o 

< o 
I < 


UJ 

a 
a 

UI 

_i 
S 

o 

z 

o 
55 


DO 


INTA 























1* 





1 


01 


wo 


1 


1 





1 





1 





1 


1 


1 


D2 


STACK 











1 


1 

















D3 


HLTA 


























1 


1(0) 


D4 


OUT 




















1 ■ 











D5 


Ml 


1 


Q 

















1 





1 


D6 


INP 





6 











1 














D7 


MEMR 


1 


1 





r 














1(0) 






(0) Identifies status outputs of the NEC 8080A which differ from those of the Intel 8080A. 
• This status is output as by the NEC 8080A during a Call instruction being executed within 
the interrupt acknowledge process. 



4-11 



INSTRUCTION FETCH SEQUENCE 

Instruction fetch timing is illustrated in Figure 4-5; events occur as follows: 

Period T-j The leading edge of <1>2 triggers the SYNC high pulse, identifying period Ti. 
WAIT is low, since the CPU is not in the Wait state. 

WR remains high since this is an instruction fetch cycle; data is not being written to memory. 
The leading edge of ^2 is used to set selected Data Bus lines high, providing external logic with status 
information as follows: 
. RI/WO (D1) • The CPU is expecting data input. 
Ml (D5) This is an instruction fetch period. - 

MEMR (D7) Data input is expected from memory. 

The leading, edge of <I»2 is used to set the required memory address on the address lines AO to A15. 

Period T2 External logic uses the $1 pulse of time period T2 to read status off the Data Bus. The read status strobe 
may be created as follows: 



SYNC 



D 



•READ STATUS STROBE 



Remember, if "you are using an 8228 System Controller, it reads and decodes status for you. 
Immediately after status has been output on the Data Bus, the Data Bus is free to receive the instruction 
object code. The address for the instructionbbject code will be on the Address Bus; this address appears 
on the Address BusduringTi, beginning with the rising eclgeof<I>2. The fact that status has been output 
and the Data Bus is free to receive the instructionobject code is indicated by DBIN being pulsed high. 
The DBIN high pulse begins with the rising edge of $2 in T2 and lasts exactly one clock period. 

Period T3 While DBIN is high, external logic must place the addressed instruction code on the Data Bus. The CPU 
will store this data in the instruction register — ^whence the Control Unit interprets it as an instruction 
code. 

The Data Bus is floated at <E>2 during T3. This means that the Data Bus has beeri disconnected from the 
CPU and can be used in any way by logic external to the CPU. 

Period T4 The Address Bus is floated at 4>2 during T4. 

The 8080A uses 1, 2 and 3 byte instructions. Each byte of a multibyte instruction requires its own instruction 
fetch. Exact timing for multibyte instructions is given later in this chapter, after the 8080A instruction set has been de- 
scribed. 

A MEMORY READ OR WRITE OPERATION 

So far as external logic is concerned, there is no difference between "read from memory" timing and instruction fetch 
timing — except that the Ml status (D5 on the Data Bus) is high during an instruction fetch only. Figure 4-5 therefore 
applies to a memory read operation also. 

Since a memory read operation is executed during time periods Tf , T2 and T3 of a machine cycle, the presence 
of a memory read operation in an instruction's execution sequence will add one machine cycle to instruction ex- 
ecution time. 

Figure 4-6 shows timing and signal sequences for a memory write operation. The signal sequences are identical 
to the instruction fetch sequence with the exception that DBIN remains low during T2 and T3, and different 
status signals are output on the Data Bus during Ti . 

SEPARATE STACK MEMORY MODULES 

One 8080A CPU can access two memory modules with overlapping memory addresses: a stack memory 
module and a nonstack memory module. Overlapping memory addresses can be used by the two memory modules, 
since Stack status (D2 high at Ol in T2) can be used to select the stack memory, while lack of Stack status (D2 low at 
<I>1 in T2) can be used to select nonstack memory. Externallogic must decode the address as referericing stack or non- 
stack memory. 



4-12 



Note that the 8228 System Controller does not generate a STACK control signal. Nevertheless, if you wish, you may im- 
plement separate stack and nonstack memory, with overlapping addresses; this requires your own status decode logic 
to isolate the Stack status. Such logic is quite simple, and may be illustrated as follows: 



SYNC 



< 

111 

z 
cc 
o 
m 

CO 

o 

< 

Q 

< 

@ 




Stack memory select 



Nonstack memory select 



The only disadvantage associated with having a separate stack memory is that nonstack instructions cannot reference 
the stack memory. 



SYNC 



READY 



WAIT 




•The NEC 8080A maintains the address on the Address Bus during T4 and T5. 



Figure 4-5. 8080A Instruction Fetch Sequence 
THE WAIT STATE 

A Wait state may occur between clock periods T2 and T3. The Wait state frees external 
logic or memory from having to operate at CPU speed. Wait state timing is illustrated in Figure 
4-7 and Figure 4-8. 

If READY is low during <P2 of T2, the 8080A CPU will enter the Wait state following T2. The Wait 
state consists of any number of clock periods during which the CPU performs no operations and maintains the levels of 
all output signals. The Wait state ends when READY is input high. The CPU samples READY during every $2 pulse 
within the Wait state; the Wait state will therefore end with the <I>1 pulse which follows a 02 pulse during which 
READY is sensed high. 



8080A 
SLOW 
MEMORIES 



4-13 



Memory interface logic in any 8080A microcomputer system must be designed to anticipate tliat every memory 
access either will, or will not require a Wait state. 

If memory is as fast as the 8080A CPU, then READY will normally be held high, in anticipation of no Wait state. In 
Figures 4-7 and 4-8 a broken line is used to represent this "READY normally high" case. Memory interface logic will 
pull READY low in order to insert one or more Wait machine cycles only in special circumstances; memory interface 
logic has until 02 of T2 to pull READY low. 




n 



rLj 



Floating 



4 Floating 



Figure 4-6. 8080A Memory Write Timing 
If memory is slower than the 8080A CPU, then READY will normally be held low in anticipation of one or more Wait 
machine cycles occurring between T2 and T3. In the special circumstance where no Wait state is needed, memory in- 
terface logic has until $2 of T2 to set READY high. 

Note that WR, if active, will be held low for the entire duration of a Wait state. This is because if WR is to be set low, the 
transition occurs at 01 of T2 and lasts until ^^ of T4 — a period which completely encompasses the Wait state. 

Relatively simple logic can be used to add a Wait state to a machine cycle. Consider the 
following scheme: 



8080A WAIT 
STATE REQUEST 
LOGIC 



MEMR- 

(from 8228), 

*1- 



PR 
01 Q1 



>CK1 7474 



PR 
D2 02 

>CK2 7474 



4-14 



Our goal, using the logic above, is to create a low READY pulse, which is one clock period wide, whenever MEMR 
nnakes a high-to-low transition. 




READY 



Consider the sequence of signal transitions in the logic we have illustrated above. At each 4>1 clock pulse, transitions 
will occur as follows; 



o 
m 
v> 
o 

< 
o 

< 




Q1 - D2 



It requires Q1 and Q2 to be high simultaneously for READY to be low; and that condition exists for a single clock pulse. 
Observe that you can use READY to trigger a one-shot in order to create a low READY input of any duration. 



Ti T2 T3 .4 T5 



*1 



4)2 



SYNC 



READY 



WAIT r\ I 



wr\j 



' Status 




A 



AJ 



...i..........^ 



Represents alternate signal form for READY as described in text accompanying this figure. 



Figure 4-7. The 8080A CPU Operating With Fast Memory and No Wait State 



4-15 



SYNC 



READY 



WAIT 



WR 




Represents alternate signal form for READY as described in text accompanying this figure. 



READY is false at ft>2 in T2, so next <t>'\ pulse initiates a Wait state, with WAIT set high by the leading 
edge of the 01 pulse. When READY is high at a ^Pl pulse, clock period T3 will be initiated by the next 
•PI pulse and WAIT will be reset low. 



Figure 4-8. The 8080A CPU Operating With Slow Memory and a Normal Wait State 

THE WAIT, HOLD AND HALT STATES 

We have discussed the Wait state within an 8080A microcomputer system, now we have to lool< at two further 
states during which instructions are not executed: the Hold and the Halt states. 

The fact that there are three states within which instructions are not being executed is frequently a source of confusion 
to 8080A users. Let us, therefore, clearly identify the differences between these three states before continuing a dis- 
cussion of the Hold and Halt states. 

As we have already seen, the Wait state consists of one or more clock periods which are inserted within a machine cy- 
cle, giving external logic time to respond to a memory access: Thus, the Wait state consists of an indeterminate num- 
ber of clock periods which occur within a machine cycle and extend the duration of that machine cycle. 

The purpose of the Hold state is to float the System busses so that external logic can perform direct memory access 
operations. Conceptually, therefore, a Hold condition consists of any number of clock periods, occurring in between 
two machine cycles which define the termination of one instruction's execution and the initiation of the next instruc- 
tion's execution: 



* _ru"\_n.. 

Last macNne cycle 

of an instruction's 

execution 



.rLrLrLn_n_ 



HOLD state clock periods ■ 



First machine cycle 
of next instruction's 
execution 



The Hold state may be looked upon as a period of time during which the CPU goes into a state of suspended animation. 

The Halt state results from the execution of a Halt instruction. The System Bus is not floated during a Halt state. During 
the Halt state, the CPU simply marks time. The purpose of a Halt state is to define those time intervals when there is 
nothing for the CPU to do; now when the CPU has nothing to do, it is only logical to assume that the CPU cannot know 
how long it will be before it has something useful to do. Typically a Halt condition will end when some external logic 
demands the service of the CPU. One method that external logic uses to demand CPU service is the interrupt request. 
The 8080A therefore requires an interrupt request to terminate the Halt state. 



4-16 



Let us now look at the Hold and Halt states in more detail. 



o 

< 

Q 
< 

@ 



THE HOLD STATE 

The Hold state allows external logic to stop the CPU. 

The Hold state is similar to the Wait state. During both states, signals output by the CPU are held constant; but 
the Data and Address Busses are floated in the Hold state only, not in the Wait state. 

The Hold and Wait states are also initiated in different ways and they serve different functions. 

The Wait state is initiated if external operations will not be completed during T3. The purpose of the Wait state is to 
allow the CPU to operate with slow memories or external logic, therefore a Wait always occurs between clock periods 
T2 and T3. ■ 

A Hold state is initiated by the hold request input signal HOLD. The CPU acknowle dges the onset of the Hold state by 
outputting HLDA high. If a HOLD is requested during a read or input operation (RI/WO (D1) high in T2), then HLDA is 
set high by the leading edge of 01 in T3. If a HOLD is requested during a write or output operation, then HLDA is set 
high by the leading edge of 01 in the cycle following T3. 

Note that even though HOLD is acknowledged and the Hold state is initiated in T3 during a read memory or input data 
machine cycle, logic must still hold data steady on the Data Bus until the leading edge of $2 in T3. This is because 
operations internal to the CPU will be executed normally during a HOLD. Operations internal to the CPU will only cease 
if the Hold state lasts for more cycles than would normally be present before the onset of the next T] cycle. 

HOLD low will cause the end of the Hold state. HOLD low must coincide with the leading edge of <I>1 or 02, and will 
terminate the Hold state at the •SI pulse of the next. machine cycle's T-\ clock period. The 8080A CPU will signal the 
end of the Hold state with HLDA false. 

During the Hold state, the Data Bus and the Address Bus are floated. Floating begins at $2 in T3 for a read operation 
and at 02 in the clock period following T3 otherwise. 

Figures 4-9 and 4-10 illustrate some variations on the Hold state. 

The NEC 8080A and the Intel 8080A differ when a Hold is requested during a DAD instruc- 
tion's execution. The NEC 8080A initiates the Hold as though a read operation was occurring, 
while the Intel 8080A initiates the Hold operation as though a write operation was occurring. 



NEC 8080A 

HOLD 

DIFFERENCES 



Do to D7 
Ao 10 A, 5 



Machin* Cycl* N 




n_ 



::ren 



MachiiM Cycla N * 1 



n n n n n r\ 



TV 



_n_ 



s\. 



ji_ 



Tw T„ 



Jl- 



I\ 



r 



t 



'optional, dtpendir>g c 



Figure 4-9A. Floating of Data and Address Busses at 02 in T3, for READ Operation Being Completed Prior 

to Onset of Hold State 



4-17 



Machini Cycle N 




.f\ r\ r\ r\ r\ _rv 



ji. 



Machine Cycle N + t 



Jl_ 



/\ 



Jl_ 



■ HOLD STATE ■ 



J~L 



n_ 



Figure 4-9B. Floating of Data and Address Busse s at 02 in T4, for a WRITE, or Any 
Non-READ Operation (RI/WO=False) 



01 

<t>2 

SYNC 

HOLD 

HLDA 

WW 

Do to D7 
Ao to A, 5 



r\ rv 




T2 T3 






r^ 



n r\ _n r\ a 



V 






Machine Cycle N + 1 



J~\- 



JT 



il_ 



-HOLD STATE- 



Jl_ 



ru 



t 



Figure 4-1 OA. Floating of Data and Address Busses for READ Operation ina Three Clock 

Period Machine Cycle 




Machine Cycle N + 1 



r\ n f\ 



i\ 



-H floating 



I\ 



J\ 



-HOLD STATE 




/\_ 



Figure 4-10B. Floating of Data and Address Busses at 02 in Ti, for WRITE or Any Non-READ Operation Being 

Completed Prior to Onset of Hold State 



4-18 



THE HALT STATE AND INSTRUCTION 

The Halt state is similar to the Wait state, except that it is initiated by a Halt instruction. 

The Halt state is not initiated by READY low, although READY low is a necessary requirennent for the onset of the Halt 
state. This means that READY high cannot be used to terminate a Halt state. Instead, an interrupt request (INT high) 
must be used to terminate the Halt state. 

^ Note that if interrupts have been inhibited, the interrupt request (INT high) will never be acknowledged, and 

tc the only way to get out of a Halt state is to power down, then power up the CPU. 

o ■ i ■ 

cc An anomaly of the Halt state is that the Data and Address Busses may be floated by entering tfip Hold state after enter- 

8 ing the Halt state; that is, you can move into, and out of the Hold state while in the Halt state. 

z 

~ if the Hold state is entered after the Halt state, then the Hold state must be exited by setting HOLD low before exiting 

Lu the Halt state. 

During a HALT, a hold request signaled by HOLD will not be acknowledged if an interrupt has been requested (INT 

o high) but not acknowledged (INTE high); i.e., the CPU will not enter the Hold state in the time between an interrupt 

« being requested and acknowledged. Once the interrupt has been acknowledged (INTE low), the CPU may enter the 

^ Hold state. 

z Figure 4-30 illustrates signal sequences and timing for the Halt instruction (and state). 

g THE RESET OPERATION 

w 

o A RESET high signal input to the 8080A CPU will clear the Program Counter and disable interrupts. 

< To properly perform the reset operation, RESET should be held high for at least three clock periods. During these 

< three clock periods, reset operations are executed in the following sequence: 

® 1) The Program Counter is cleared. 

2) All interrupt requests are disabled. 

3) Internal interrupt acknowledge logic (associated with signal INTE) is cleared. 

4) Internal hold acknowledge logic (associated with signal HLDA) is cleared. 

For as long as RESET is high, all 8080A CPU operations will be suspended. 

When RESET is reset low, instruction execution will resume with a T-\ clock period at the next <I>1 pulse. Since the Pro- 
gram Counter contains 0000, the first instruction executed following RESET will be the instruction stored in memory 
location OOOOie- 

Interrupts remain disabled when program execution resumes. 

When you power up any 8080A system you must simultaneously reset it. Powering up does not reset or change 
anything within the 8080A. If you power up without resetting, then registers, including the Program Counter, will con- 
tain undefined data; thus program execution will immediately and erroneously begin at some random location of 
memory. . 

Here are two possible reset on power up logic implementations: 
First a simple logic sequence: 

+ 5V p 



:Q 



r 
1 



RESET 



RESIN 
8224 



4-19 



Next a more complex, and more reliable one: 



1.0' 



1 i 



1.0 ; 



= +0.47UF ± 0.1 UF 



+ 5V 



'cc 



TH 



TR 555 OUT 



pis GND 

CV 



:i 0.1UF 



1/6 74LS04 



RESET 



A 



02 

SYNC 

READY 

DBIN 

WAIT J V 
WR-/ V 
INT 

INTE 



Oq to D7 
AotpAi5 



N 


Machine Cycle N + 1 ' 


■ N + 2 




Ti 


T2 


T3 ' 


T4 


T5 


T, 


n 


r\ 


/A 


n 


A 


n 


n 


_n_ 


/^ 


^ 


— s^^ 


^^r\_ 


_r\_ 


^4n_ 




T^ 


-IJ\ 


\ 






V- 


h \ 


n^ \ 




r \ 














1 


J 


J 








-j^ 


^^ 


















J 














/ 














/ 


■"A 














W 


\ 


. 




' 






\l-.s-i : I^:^;r I 


j 


\-> 


' 




1 








i 




Exte 

Reac 

D, - 

■* 1 


rnal Logic 
i Status 
Status 
nterrupt Initiat 






1 



Figure 4-1 1. Interrupt Initiation Sequence 



4-20 



EXTERNAL INTERRUPTS 

External logic may request ah in^Sfrupt at any time by setting the INT input high. An interrupt request will only 
be acknowledg(9d if interrupts have been enabled. Normally the El (Enable Interrupts) and Dl (Disable Interrupts) in- 
structions are executed to enable and disable interruJDts; however, interrupts are automatically disabled by the CPU 
during the RESET condition, and following an interrupt ackhdwledge. 

2 The 8080A CPU outputs INTE high when interrupts have been enabled, and low when interrupts are disabled. If inter- 

5 rupts are enabled, theri the SOSOACPU will acknowledge an interrupt request during the next Ti clock period, on the 

o rising edge of S>2. At this time INTE is set low to reflect the fact that an interrupt acknowledge automatically disables 

^ interrupts. Timing is illustrated in Figure 4-11. 

o ••■,■,.'■ 

u The 8080A CPU informs external logic that an interrupt has been acknowledged by outputting this status on 

- the Data Bus: 

^ DO-INTA- 

< Dl - RI/WO 

Q D5-M1 . 

« ' ■ ' ■ 

< INTA is the principal interrupt acknowledge status; it is converted into a separate interrupt acknowledge con- 
oa trol signal by the 8228 System Controller. 

ui • ■ . 

z Once an interrupt has been acknowledged, the 8080A CPU enters an instruction fetch sequence — but with 

o two differences: 

EQ 

o 1) Program Counter increment logic is suppressed. 

2 2) Different statuses are output oh the Data Bus during T2. The statuses output on the Data Bus during various 

Q machine cycles are summarized in Table 4-3. 

< 

@ The different statuses output during T2 of a normal, or a post-interrupt acknowledge instruction fetch are very 

important. . 

Dui-ing a normal instruction fetch sequence, MEMR is output true on D7. 

During the instruction fetch sequence which follows an interrupt acknowledge, MEMR is not output true on D7, but 
INTA is output true on DO. ■ 

Thus, external logic can differentiate between a normal instruction fetch and the instruction fetch sequence which 
follows an interrupt acknowledge. 

It is very important that external logic be able to differentiate between a, normal instruction fetch and an interrupt 
acknowledge instruction fetch. When the interrupt is acknowledged, the Program Counter is addressing an instruction 
which will not get executed until the interrupt service routine has completed execution: 



- When Instruction (^ completes execution, PC 
is addressing Instmction ^object code byte 




' But Instnjction (^ is to be executed 
directly following Instruction @ 



4-21 



Therefore the first instruction executed following the interrupt acknowledge must save the Program Counter 
contents. The last instruction executed within the interrupt service routine restores the Program Counter con- 
tents.During the instruction fetch vyhich follows an interrupt acknowledge, the Program Counter increment 
logic is suppressed, because the 8080A CPU expects the object code for the first interrupt service routine in- 
struction to be supplied by the interrupting device instead of memory: 

PROGRAM 
MEMORY 



dS" 



Interrupting logic provides first object code byte 
following interrupt acknowledge 



n-1 



h+1 
n + 2 



n + 3 
n + 4 
n + 5 
n + 6 
n + 7 



I Interrupt acknowledged 
PC now addresses n + 3 



The object code provided by external logic during the Instruction fetch which follows the interrupt 
acknowledge must be the object code for an instruction which will save the Program Counter contents for sub- 
sequent retrieval. There is only one instruction which will do this and that is a subroutine CALL instruction. 

Recall from Volume I that the subroutine CALL instruction will save the current Prograni Counter contents on the 
Stack, then will load a new starting address into the Progrann Counter. Thus, a subroutine CALL instruction satisfies the 
logical requirements for interrupt service routine initiation. ■ 

The normal way of terminating a subroutine is via a Return instruction. This instruction loads the Program Counter 
from the top of the Stack. The Return instruction will, therefore, satisfy the logical requirements for interrupt service 
routine termination. 

There are two types of 8080A subroutine CALL instruction: the RESTART (RST) and the CALL. The RST instruction is 
a one-byte subroutine CALL with the following object code: 

RST N instruction code: 



1 1 1 XXXI 1 




000 


N =0 


001 


N =1 


10 


N =2 


1 1 


, N =3 


100 


N =4 


101 


N =5 



New Program 
Counter contents: 



1 10 
1 1 1 

T 



N =6 
N =7 



OOOOOOOOOOXXXOOO 



Therefore RST n instructions are equivalent to subroutine CALL instructions, with program execution branching as 
follows: 



RSTO 
RST 1 
RST 2 
RST 3 
RST 4 
RST 5 
RST 6 
RST 7 



branch to 0000 ^g 
branch to 0008 
branch 
branch 
branch 
branch 

branch to 0030 
branch to 0038 



16 
to OOlOie 

I to oois^e 
I to 0020ie 

I to 0028i6 
16 



16 



4-22 



The CALL instruction is a typical three-byte, direct memory addressing subroutine-call: 



nnnn + 3 to Stack 



O 

CQ 

O 

< 
o 

< 

@ 



1 



PC I nnnn +3 | 




PROGRAM 
MEMORY 


nnnn-1 
nnnn 
nnnn + 1 
nnnn + 2 
nnnn + 3 
nnnn + 4 








CD 




qq 


Subroutine execution address 


PP 


) IS ppqq 















ppqq to PC 



The address of the instruction following the subroutine call (nnnn-l-3) is saved on the Stack, to be retrieved subse- 
quently by a Return instruction. The second and third CALL instruction object code bytes provide the address of the 
subroutine's first instruction; this address (ppqq) therefore is loaded into the Program Counter. 

What is not clearly understood by many 8080A users is that external logic can respond to an interrupt 
acknowledge by inserting either an RST or a subroutine CALL instruction. 

Responding to an interrupt acknowledge by inserting an RST instruction is very straightforward. The INTA status 
output during T2 can be used to select external logic as the source of an object code, while the lack of an MEMR status 
can be used to suppress the normal instruction fetch which would occur from program memory. Thus, a simple 8-bit 
I/O buffer will generate a Restart instruction as follows: 



+ 5V O 



Tie to + 5V for 
Tie to GND for 



•{■ 



Any 
8- Bit 
Buffer 



DO (INTA) 
SYNC. 



o 



INTA Strobe 



Connect to Data Bus 



With a little more effort, external logic can be designed to provide a subroutine CALL instruction's object code 
following the interrupt acknowledge. Providing the INTA status is used to suppress normal program memory ac- 
cesses for the next three machine cycles, logic associated with the external interrupt request can supply the three con- 
secutive object code bytes of a normal subroutine CALL instruction. 

In a configuration that includes an 8228 System Controller, if the first object code byte received following INTA output 
is a CALL (CDi6). then the 8228 System Controller outputs two more INTA statuses for the next two machine cycles. 
Now external logic can use INTA as a signal which disables normal memory accesses, selecting external logic instead. 
For more details, see the 8228 System Controller description given later in this chapter. 

If your configuration does not include an 8228 System Controller, then external logic must be quite complex if it res- 
ponds to an interrupt acknowledge with a CALL instruction. These are the operations external logic must perform: 

1) In response to INTA true, suppress normal memory references and transmit the code CD15 to the CPU. This code 
must be transmitted at the proper time, as an instruction code on the Data Bus. 

2) Suppress normal memory accesses for the next two clock periods. Remember, there is no INTA true for these two 
periods. 

3) During the next two clock periods, transmit the low order half, then the high order half of the interrupt service 
routine starting address. These two address bytes must be provided out of external logic, and their timing on the 
Data Bus must conform exactly to the second and third bytes of a CALL instruction. 



4-23 



NEC 8080A 
INTERRUPT 
ACKNOWLEDGE 
DIFFERENCES 



If your configuration includes an 8259 Priority Interrupt Control Unit, then this device takes care of all logic associated 
with responding to an interrupt acknowledge with a CALL; the 8259 is described later in this chapter. 

This NEC 8080A does not handle the INTA signal in the same way as the Intel 8080A. In ' *""* «"«"« '' 

response to a Call instruction executed during an interrupt acknowledge, the NEC 8080A out- 
puts INTA true for three machine cycles; in an Intel 8080A system an 8228 System Controller 
must be present for this to occur. The NEC 8080A DO status output also differs at this time; 
see Table 4-3 for details. 

The NEC 8080A responds to Restart instructions following an interrupt acknowledge in the same way as the Intel 
8080A. 

EXTERNAL INTERRUPTS DURING THE HALT STATE 

With all 8080A devices except the NEC 8080A, interrupt acknowledge logic during a 



NEC 8080A 
EXTERNAL 
INTERRUPT 
DIFFERENCES 



Halt state is as illustrated in Figure 4-11. For the NEC 8080A, however, the interrupt 
acknowledge sequence differs slightly during the Halt state only. INTE is reset low by the 
NEC 8080A on the rising edge of 02 in clock period T2; this is one clock period later than il- 
lustrated in Figure 4-11. Note that this difference in NEC 8080A response applies only to the 
interrupt acknowledge process occurring within a Halt state. 

WAIT AND HOLD CONDITIONS FOLLOWING 
AN INTERRUPT 

An interrupt cannot be acknowledged during a WAIT or HOLD condition. However, either of these conditions may oc- 
cur following the interrupt acknowledge. For example, if there is insufficient time between $1 in T2 and 02 in T2 for 
external logic to fetch the required RST or CALL instruction, more time may be acquired by using the READY signal to 
generate a Wait state, as with any instruction's execution. 



THE 8080A INSTRUCTION SET 

Table 4-4 summarizes the 8080A instruction set; there is a significant departure in instruction set philosophy 
from the hypothetical microcomputer described in Volume I. 

The 8080A is most efficiently programmed by making extensive use of the Stack and of subroutines. By providing a 
variety of Jump-to-Subroutine on Condition, and Return-from-Subroutine on Condition instructions, the 8080A allows 
the execution of subroutines to become an integral part of programmed logic sequences. 

Observe that the 8080A has a number of 1 6-bit instructions; that is, instructions that operate on the 1 6-bit contents of 
the BC, DE or HL registers. These include 16-bit increment and decrement, 16-bit add, and 16-bit data moves. 

The 1 6-bit instruction XTHL is particularly useful, since by allowing the top two Stack bytes to be exchanged with the 
HL registers, an easy method is provided for switching addresses. 

The DAA instruction modifies the A register contents to generate a binary coded decimal equivalent of the original bin- 
ary value. If carries out of bit 3 or bit 7 result, these are reported in the Auxiliary Carry and Carry statuses, respectively. 
See Volume T for a discussion of the decimal adjust operation. ' • . , 

There are a few differences between NEC 8080A and Intel 8080A instruction execution. 



NEC 8080A 
INSTRUCTION 
SET , 
DIFFERENCES 



For binary subtraction and BCD arithmetic the NEC 8080A performs operations in what is 
theoretically the "correct" fashion — which diffe.rs from the actual implementation of the Intel 
8080A. Specifically, the NEC 8080A has a Subtraci status (SUB) which is set after any addition 
is performed., Only the NEC 8080A has a Subtract status. 

The NEC 8080A correctly sets and resets the Auxiliary Carry status (AC) during subtract operations, identifying any 
borrow by the low order digit as follows: 



r> 



Borrow here sets AC 



.76543210 

XXXXXXXX 

- Y y Y Y Y Y Y Y 

= ZZZZZZZZ 



4-24 



< 
ca 

Z 
oc 
o 
m 
u> 
o 

< 
< 

@ 



X, Y and Z represent any binary digits. 

Decinnal subtraction for the Intel 8080A and NEC 8080A may be illustrated as follows, assuming the contents of 
Register B are to be subtracted from the contents of Register C: 

INTEL 8080A NEC 8080A 

MVI A,99H MOV A,B 

SUB C SUB C 

ADD B DAA 
DAA 

In the instruction sequence illustrated above for the Intel 8080A, you cannot use the Subtract instruction directly since 
it works for binary arithmetic only. You must create the nine's complement of the subtrahend by subtracting it from 99. 
Then you add the minuend to the nine's complement of the subtrahend. Finally you decimal adjust the result. 

In the case of the NEC 8080A you may use the Subtract instruction for either binary or BCD data. 

For a complete discussion of decimal subtraction using the Intel 8080A, see 8080 Pro g rammin g for Lo g ic Desi gn, 
Chapter 7. 

The Carry and Auxiliary Carry statuses are also treated differently by the NEC and Intel 8080A. When Boolean 
instructions are executed by the Intel 8080A, the Carry status (C) is always reset; the Auxiliary Carry status 
(AC) is sometimes reset. The NEC 8080A leaves the Carry and Auxiliary Carry statuses alone when executing 
Boolean instructions. 

When the AMD 9080A executes Boolean instructions it always clears both the Carry and Auxiliary Carry 
statuses. 



THE BENCHMARK PROGRAM 

Our benchmark program is coded for the 8080A as follows: 



LHLD 
LXI 
LDA 
MOV 
LOOP LDAX 
INX 
MOV 
INX 
DCR 
JNZ 
SHLD 



TABLE 

D.IOBUF 

lOCNT 

B.A 

D 

D 

M.A 

H 

B 

LOOP 

TABLE 



LOAD ADDRESS OF FIRST FREE TABLE BYTE IN HL 

LOAD STARTING ADDRESS OF lOBUF IN DE 

LOAD I/O BUFFER LENGTH 

SAVE IN B 

LOAD NEXT I/O BYTE 

INCREMENT BUFFER ADDRESS 

STORE IN TABLE 

INCREMENT TABLE ADDRESS 

DECREMENT BYTE COUNT 

RETURN FOR MORE BYTES 

AT END, RESTORE ADDRESS OF FIRST FREE TABLE BYTE 



The 8080A makes very few assumptions regarding the benchmark program. 

The address of the first free byte in the data table is assumed to be stored in the first two bytes of the data table — ad- 
dressed by the label TABLE. The immediate addressing instruction LHLD loads the contents of the first two bytes of the 
data table into the H and L registers. At the end of the program, the incremented table address is restored with the 
direct addressing instruction SHLD. 

Since the I/O buffer starting address does not change, an Immediate instruction is used to load this address into the DE 
registers. 

Since the number of occupied bytes in the I/O buffer may change, a direct addressing instruction, LDA, is used to load 
this buffer length into the Accumulator. It is then moved to the B register, since the Accumulator is used to transfer 
data within the program loop. 

The 8080A program makes no assumptions regarding the location of either the I/O buffer, or the data table, but it does 
assume that the table is not more than 256 bytes long. 

These are the abbreviations used in Table 4-4: 

A The Accumulator 

B The B registe 

C The C register 

D The D registe 

E The E register 



3r i 



These are sometimes treated as a register pair 
These are sometimes treated as a register pair 



4-25 



H 
L 
C 

Ac 

Z 

s 
p 

SUB 

I 

12 

13 

PC 

SP 

PSW 






This register pair provides the implied memory address 



DATA 

DATA 16 

DEV 

REG 

s 

d 

M 

LABEL 

RP 

PORT 

ADDR 

[ 1 

[ ] 



A 

V 
¥- 



The H register 

The L register 

Carry status. In Table 4-4 C refers to Carry status, not to the C register. 

Auxiliary Carry status 

Zero status 

Sign status 

Parity status 

Subtract status (present in the NEC 8080A only) 

The instruction register 

Second object code byte 

Third object code byte 

The Program Counter 

The Stack Pointer 

The Program Status Word, which has bits assigned to status flags as follows: 



7 6 5 4 3 2 1 

siz|xmx|P|xFl 



■ Bit No. 



' Unassigned 

• SUB (NEC 8080A only) 



8-bit immediate data 

16-bit immediate data 

An I/O device 

Register A, B, C, D, E, H or L 

Source register 

Destination register 

Memory, address implied by HL 

A 16-bit address, specifying an instruction label 

A register pair: B for BC, D for DE, H for HL, SP for Stack Pointer 

An I/O port, identified by a number between and ffiQ 

A 16-bit address, specifying a data memory byte 

Contents of location identified within brackets 

Memory byte addressed by location identified within brackets 

Complement of the contents of 

Move data in direction of arrow 

Exchange contents of locations on either side of arrow 

Add 

Subtract 

AND 

OR 

XOR 



The letter C is used to identify Carry status. Although C also identifies one of the 8080A 
registers, registers are always referenced generically in Table 4-4. 



8080A 
CARRY 
STATUS 
NOMENCLATURE 



4-26 



© ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 4-4. A Summary of 8080A/9080A Microcomputer Instruction Set 



TYPE 


MNEMONIC 


OPERAND{S) 


BYTES 


STATUSES 


OPERATION PERFORMED 


C 


AC 


z 


S 


P 


SUB- 


O 


IN 
OUT 


DEV 
DEV 


2 
2 














[A]— [DEV] 

Input to A from device DEV (DEV = to 255) 
[DEV]-[A] 

Output from A to device DEV (DEV = to 255) 


111 
o 

z 

111 

^5 

ce u. 
< uj 

n 

111 

s 


ID AX 

STAX 

MOV 

MOV 

LDA 

STA 

LHLD 

SHLD 


RP 

RP 

REG.M 

M.REG 

ADDR 

ADDR 

ADDR 

ADDR 


1 
1 
1 
1 
3 
3 
3 
3 














[Al-([RP]] 

Load A using address implied by BC (RP = B) or DE (RP = D) 
([RP]I-[A] 

Store A using implied addressing as for LDAX 
[REG]-[[H,L]] 

Load any register using address implied by HL 
I[H,L]]-[REG1 

Store any register using address implied by HL 
[A]-[ADDR], i.e., [A]-[[I3. 12]] 

Load A, use direct addressing 
[ADDR] — [A], i.e., [[13, 12)] — [A] 

Store A, use direct addressing 
[L]-[ADDRl, [H]-[ADDR+1], i.e., [Li-[[I3, 12]], [H]-[[I3, 12] + 1] 

Load H and L registers, use direct addressing 
[ADDR] — [L], [ADDR+n — [H]l.e., [113. 12]] — [L], [[13, 12] + 1] — [H] 

Store H and L registers, use direct addressing 


111 
o 

z 
111 

K 
111 

Si IS 

cc < 
>- "= 

n 

s§ 
>: S 

OC UJ 

SI 

z 
o 
o 

lU 

W 


ADD 

ADC 

SUB 

SBB 

ANA 

XRA 

ORA 

CMP 

INR 

DCR 


M 
M 
M 
M 
M 
M 
M 
M 
M 
M 




X 

X 

X 

X 

0'« 

0" 

o»* 

X 


X 

X 

X 

X 

Xt" 

Of* 

Of 

X 

X" 

x»» 


X 
X 
X 
X 
X 
X 
X 
X 
X 
X 


X 
X 
X 
X 
X 
X 
X 
X 
X 
X 


X 
X 
X 
X 
X 
X 
X 
X 
X 
X 





1 
1 

1 



1 


[A]-[A]+[[H.L]] 

Add to A 
[A]-[A]+[IH,L]]+[C] 

Add with Carry to A 
[Al-[A]-[[H,L]] 

Subtract from A 
[A]-[A]-[[H,LJ]-[C] 

Subtract from A with borrow 
[A]-[A]A[H,L1] 

AND with A 
[A]-[A]V[[H,L]i 

Exclusive-OR with A 
[A1-[A]V[[H,L]] 

OR with A 
[A] - [[H.L]]. Discard result but set flags. 
Compare with A 
[[H,L]]-[(H,L]]+1 

Increment memory 
[[H,L)l-[[H,Ll]-1 

Decrement metriory 



Table 4-4. A Summary of 8080A/9080A Microcomputer Instruction Set (Continued) 







OPERAND(S) 


BYTES 


STATUSES 


OPERATION PERFORMED 


TYPE 


MNEMONIC 






















C 


AC 


Z 


s 


p 


SUB' 






LXI 


RP,DATA16 


3 














[RP]— DATA16 
Load 16-bit immediate data into BC (RP = B), DE (RP = D). 


UJ 

5 


MVl 


M.DATA 


2 














HL (RP = H) or SP (RP = SP) 


5 




















[[H.LII— DATA 


lU 

5 




















Load 8-bit immediate data into memory location with address 


S 


MVI 


REG.DATA 


2 














implied by HL 
t REG]— DATA 
Load 8-bit immediate data into any register 




JMP 


ADDR 


3 














t PC]*- ADDR 


Q. ~ 




















Jump to instruction with label ADDR 


-3 
■ -> 


PCHL 




1 














[PC]-[H,L] 
Jump to instruction at location implied by HL 




CALL 


ADDR 


3 














[[SPlI— [PC], [PC] — ADDR, [SP] — [SP)-2 
Jump to subroutine starting at ADDR 




cc 


ADDR 


3 














[[SP]]-[PC], [PC]-ADDR, [SP]-[SP]-2 
Jump to subroutine if C = 1 




CNC 


ADDR 


3 














[[SP]]-[PC], [PC]-ADDR, [SP]-[SP]-2 
Jump to subroutine if C = 




cz 


ADDR 


3 














[[SP]]-[PC], [PC]-ADDR, [SP]-[SP]-2 
Jump to subroutine if Z = 1 


Z 


CNZ 


ADDR 


3 














[[SP]1-[PC], [PCl-ADDR, [SP]-[SP]-2 


oe 

3 ^ 




















Jump to subroutine if Z:= 


UJ O 


CP 


ADDR 


3 














[[SP]]-[PC], [PC]-ADDR, [SP]-[SP]-2 


* 2 




















Jump to subroutine if S = 


CM 


ADDR 


3 














[[SP]]-[PC], [PC]-ADDR, [SP]-[SPl-2 


ji 




















Jump to subroutine if S = 1 


^2 


CPE 


ADDR 


3 














[[SP]] — [PC], [PC] — ADDR, [SP] — [SP]-2 


O H 




















Jump to subroutine if even parity 


i o 


CPO 


ADDR 


3 














[[SP]]-[PC], [PC]- ADDR, [SP]-[SP]-2 


^s 




















Jump to subroutine if odd parity 


si 


RET 




1 














[PC]-[[SP]],[SP]-[SP] + 2 


CO — 

3 




















Return from subroutine 


(/> 


RC 
RNC 
RZ 
, . RNZ 
RM 




1 
1 
1 

1 . 
1 














[PC] — [[SP]], [SP] — [SP] + 2 . , 

Return from subroutine if C = 1 
[PC]-[[SP]]. [SP]-[SP] + 2 

Return from subroutine if C = 
[PC]-[[SP]], [SP]-[SP] + 2 

Return from subroutine if Z = 1 
[PC]-[[SP]], [SP]-[SP] + 2 

Return from subroutine if Z = 
[PC] — [[SP]], [SP] — [SP] + 2 

Return from subroutine if S = 1 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 4-4. A Summary of 8080A/9080A Microcomputer Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUSES 


OPERATION^ERFORMED 





AC 


■z 


s 


p 


SUB* 


SUBI^OUTINE CALL AND 

RETURN (IMMEDIATE 

AND STACK) (CONTINUED) 


RP 

RPE 

RPO 




1 

1 

1 














[PC]-[[SP]]. [SP]-[SP) + 2 
Return from subroutine if S = 

[PC]-[[SPl]. [SP]-[SP] + 2 
Return from subroutine if even parity 

[PC]-[[SP]], [SP]-[SP] + 2 
Return from subroutine if odd parity 


ce 

UJ 

a. 
O 
111 

E 

m 

s 


AD! 
AC! 
SUI 
SB! 
AN! 

XRI 
OR! 
CPI 


DATA 
DATA 
DATA 
DATA 
DATA 

DATA 
DATA 
DATA 


2 
2 
2 
2 
2 

2 
2 
2 


X 
X 
X 
X 

0" 

O" 
O" 
X 


X 
X 
X 
X 

xt 

0" 
X 


X 
X 
X 
X 
X 

X 
X 
X . 


X 
X 
X 
X 
X 

X 
X 
X 


X 
X 
X 
X 
X 

X 
X 
X 





1 
1 


[A]— [A] + DATA 

Add immediate to A 
[A] — [A] + DATA+ [C] 

Add with carry immediate to A 
[A]-[A]-DATA 

Subtract immediate from A 
[A] — [A]-DATA-[C] .- ^ 

Subtract immediate with borrow from A 
[A]-[A] ADATA 

AND immediate with A 

[A] — [A]VDATA 

Exclusive-OR immediate with A 
[A]— [AlV.DATA 

OR immediate with A > 
Compare immediate with A 


' z 
o 

H 

O 

.z 
o 
o 
z 
o 

B. 

s 


JC 

JNC 

JZ 

JNZ 

JP 

JM 

JPE 

JPO 


ADDR 
ADDR 
ADDR 
ADDR 
ADDR 
ADDR 
ADDR 
ADDR 


3 
3 
3 
3 
3 
3 
3 
3 














[pel- ADDR 

Jump if C = 1 
[PC]— ADDR 

Jump if C = 
[PC]— ADDR 

Jump if Z = 1 
[PC] — ADDR 

Jump if Z = 
[PC] — ADDR 

Jump if S = 
[PC] — ADDR 

Jump if S = 1 . 
[PC]-ADDR 

Jump on even*parvty 
[PC] — ADDR 

Jump on odd parity 



Table 4-4. A Summary of 8080A/9080A Microcomputer Instruction Set (Continued) 





MNEMONIC 


OPERAND(S) 


BYTES 


STATUSES 


OPERATION PERFORMED 


TYPE 






















C 


AC 


z 


s 


p 


SUB- 




Ul 


MOV 


ds 
















[REG]— [REG] 


> 
O 




















Move any register (s) to any register (d) 


S 


XCHG 


















[D] [H], [E] [U 


(9 

lU 




















Exchange DE with HL 


6 


SPHL 


















[SP]-[HL] 


Ul 

cc 




















Transfer HL to SP 




ADD 


REG 




X 


X 


X 


X 


X 





[A]— [A] + [REG] 
Add any register to A 




ADC 


REG 




X 


X 


X 


X 


X 





[A]-[A]+[REG]+[C] 
Add with Carry any register to A 




SUB 


REG 




X 


X 


X 


X 


X 


1 


[A]-[A]-[REG] 






















Subtract any register from A 


\h 


SBB 


REG 




X 


X 


X 


X 


X 


1 


[A]-[A]-[REG]-[C] 


2S 




















Subtract any register with borrow from A 


iS 


ANA 


REG 




0** 


xt 


X 


X 


X 




[Al-[A]A[REG] 


H 




















AND any register with A 


w ° 


XRA 


REG 




0*» 


Of* 


X 


X 


X 




[A]>-[A]V[REG1 






















Exclusive-OR any register with A 


oe 


ORA 


REG - 




O" 


Of 


X 


X 


X 




[A]-[A]V[REG] 
OR any register with A 




CMP 


REG 




X- 


X 


X 


X 


X 


1 


[A] - [REG]. Discard result but set flags. 
Compare any register with A 




DAD 


RP 




X 













[H,L]-[H,L]+ [RP] 
Add to HL 




INR 


REG 






X" 


X 


X 


X 





[REG]— [REG] + 1 
Increment any register 




DCR 


REG 






X" 


X 


X 


X 


1 


[REG]-[REG]-1 
Decrement any register 




CMA 


















[A]-[A] 
Complement A 


2S 

ce O 


DAA 
RLC 
RRC 






X 
X 
X 


X" 


X 


X 


X 




Decimal adjust A 




'HUh 


1 


U-j~ 














H 


Rotate A left with 


* L 


branch carry 


TT^ 


1 


iJT 














H 


Rotate A right wi 


^^ 


th branch carry 



© ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 4-4. A Summary of 8080A/9080A Microcomputer Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUSES 


OPERATION PERFORMED 


C 


AC 


■ Z - 


s 


p 


SUB- 


Ul 

is-, 

Ul Ul 

9z => 

O 2 

lU z 


RAL 




1 


X 












Ti^ n 















□^ 


LJ L 


Rotate A left withxarry 


, , 1 


»n > r^ 














~H 


* LI • L 


o — 

lU 
E . 


RAR 
INX 

OCX 


RP 
RP 




X 












Rotate A right with carry 

[RP]— [RPl+1 

Increment RP. RP = BC. DE, HL or SP- 
[RP] — [RP]-1 

Decrement RP 




PUSH 


RP 
















[[SP]]-[RP]. [SP]-[SP]-2 \ 






















Push RP contents onto stack > RP = BC, DE. HL or PSW 


< 


POP 


RP 
















[RP]-[[SP]], [SP]-[SP] + 2 j 




















Pop stack Into RP 




XTHL 


















[H,L] [[SP]] 

Exchange HL with top of stack 


t 


El , " 


















Enable Interrupts 


ce. 


Dl 


















Disable interrupts 


H 


RST 


N 
















Restart at addresses 8*N. N = through 7. 


























STC 






1 












[C]-1 


3 


CMC 






X 












Set Canv 
[C]-[C] 


W 




















Complement Carry 




NOP 


















No operation 




HLT 


















Halt 



Statuses: 


C 


= 


Carry 




Ac 


= 


Carry out of bit 3 




Z 


= 


Zero 




s 


= 


Sign 




p 


= 


Parity 




X 


- 


Status set or reset 







= 


Status reset 




1 


= 


Status Set 




Blank 


= 


Status unchanged 



* . SUB status is present in NEC 8080A only 
*.* NEC 8080A does not modify these status flags 
t The AMD 9080A always resets A^; to for all Boolean instructions. The Intel 8085 sets Aq to 1 for all AND 
instructions, and resets Aq to for all other Boolean instructions. 



Table 4-5. A Summary of Instruction Object Codes 
and Execution Cycles 



'■r ' ■■ -■ 

INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK 
PERIODS 


FIGURE 


LXI 


RP,DATA16 

1 '^ t 


OOXXOOOI 
YYYY 


3 


10 


4-22 


MOV 


REG.REG 


Oldddsss 


1 


■ - 5(4)' 


4-13 


MOV 


MiREG 


OmOsss 


1 


7 


4-16 


MOV 


.REG.M 


OldddllO 


1 


7 


4-15 


MVI 


REG.DATA 


OOdddllO 
YY 


2 


7 


4-15 


MVI 


M.DATA 


36 , YY 


2 


10 


4-14 


NOP 




00 




4 


4-12 


ORA 


REG 


lolioxxx 




4 


4-12 


ORA 


M 


B6 




7 


4-15 


ORI • 


DATA 


F6 YY 




7 


4-15 


OUT 


PORT 


D3 YY 




10 


4-29 


PCHL 




E9 




5 


4-13 


POP 


RP 


11XX0001 




10 


4-19 


PUSH 


RP 


11XX0101 




11 


4-18 


RAL 




17 




4 


4-12 


RAR 




1F 




4 


4-12 


RC 




08 




5/11 


4-27 


RET 




C9 




io(iiy 


4-19 


RLC 




07 . ' 




4 


4-12 


RM 




F8 




5/11 


4-27 


RNC 




DO 




5/11 


4-27 


RNZ 




CO 




5/11 


4-27 


RP 




FO 




5/11 


4-27 


RPE 




E8 




5/11 


4-27 


RPO 




EO ' 




5/11 


4-27 


RRC 




OF 




4 


4-12 


RST 


N 


11XXX111 




11 


4-18 


RZ 




C8 




5/11 


4-27 


SBB 


REG 


10011 XXX 




4 


4-12 


SBB 


tvi 


9E 




7 


4-15 


SB! 


DATA 


DE YY 




7 


4-15 


SHLD 


ADDR 


22 ppqq 




16 


4-25 


SPHL 




F9 




•5(4)* 


4-13 


STA 


ADDR 


32 ppqq 




13 


4-23 


STAX 


RP 


000X0010 




7 


4-16 


STC 




37 ■ 




4 


4-12 


SUB 


REG 


10010XXX 




4 


4-12 


SUB 


M 


96 




7 


4-15 


SUI 


DATA 


D6 YY 




7 


4-15 


XCHG 




EB 




4 


4-12 


XRA 


REG 


10101XXX 




4 


4-12 


XRA 


M 


AE 




7 


4-15 


XRI , 


DATA 


EE YY 


2 


7 


4-15 


XTHL. 




E3 


1 ■ 


18(17)' 


4-21 



INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK 
PERIODS 


FIGURE 


ACi 


DATA 


CE YY 


2 


7 


4-15 


ADC 


REG 


10001XXX 


1 


4 


4-12 


ADC 


M 


8E 


1 


7 


4-15 


ADD 


REG 


10000XXX 


1 


4 


4-12 


ADD 


M 


86 


1 


7 


4-15 


ADI 


DATA 


C6 YY 


2 


7 


4-15 


ANA 


REG 


10100XXX 


1 


4 


4-12 


ANA 


M 


AS 


1 


7 


4-15 


ANI 


DATA 


E6 YY 


2 


7 


4-15 


CALL 

CC 

CM 


LABEL 
LABEL 
LABEL 


CD ppqq 
DC ppqq 
FC ppqq 


3 

■ 3 
3 


17 
11/17 
11/17 


4-26 
4-26 
4-26 


CMA 




2F 


1 


4 


4-12 


CMC 




3F 


1 


4 


4-12 


CMP 


REG 


10111XXX 


1 


4 


4-12 


CMP 


M 


BE 


1 


7 


4-15 


CNC 


LABEL 


D4 ppqq 


3 


11/17 


4-26 


CNZ 


LABEL 


C4 ppqq 


3 


11/17 


4-26 


CP 
CPE 


LABEL 
LABEL 


F4 ppqq 
EC ppqq 


3 
3 


11/17 
11/17 


4-26 
4-26 


CPI 


DATA 


FE YY 


2 


7 


4-15 


CPO 


LABEL 


E4 ppqq 


3 


11/17 


4-26 


CZ 


LABEL 


CC ppqq 


3 


11/17 


4-26 


DAA 




27 




4 


4-12 


DAD 


RP 


00XX1001 




10(11)' 


4-20 


DCR 


REG 


ooxxxioi 




5 


4-13 


OCR 


M 


35 




10 


4-14 


DCX 


RP 


00XX1011 




5 


4-13 


Dl 




F3 




4 


4-12 


El 




FB 




4 


4-12 


HLT 




76 




7 


4-30 


IN 


PORT 


DB YY 




10 


4-28 


INR 


REG 


OOXXX100 




5 


4-13 


INR 


M 


34 




10 


4-14 


INX 


RP 


0OXX001 1 




5 


4-13 


JC 


LABEL 


DA ppqq 


3 


10 


4-22 


JM 


LABEL 


FA ppqq 


3 


10 


4-22 


JMP 


LABEL 


C3 ppqq 


3 


10 


4-22 


JNC 


LABEL 


D2 ppqq 


3 


10 


4-22 


JNZ 


LABEL 


C2 ppqq 


3 


10 


4-22 


JP 


LABEL 


F2 ppqq 


3 


10 


4-22 


JPE 


LABEL 


EA ppqq 


3 . 


10 


4-22 


JPO 


LABEL 


E2 ppqq 


3 


10 


4-22 


JZ 


LABEL 


CA ppqq 


3 


10 


4-22 


LDA 


ADDR 


3A ppqq 


3 


13 


4-24 


LDAX 


RP 


000X1010 


1 


7 


4-15 


LHLD 


ADDR 


2A ppqq 


3 


16 


4-17 



ppqq represents four hexadecimal digit memorv address 
YY represents two hexadecimal data digits 

YYYY represents four hexadecimal data digits 
X represents an optional binary digit 

ddd represents optional binary digits Identifying a destination register 

sss , represents optional binary digits identifying a source register 

• The NEC 8080A has five instructions with unique execution times, defined above by 
:(N)* where N is the number of NEC 8080A instruction cycles. 



4-32 



INSTRUCTION EXECUTION TIMES AND CODES 

Table 4-5 lists instructions in alphabetic order, showing object codes and execution times, expressed as 
machine cycles. 

Where two instruction cycles are shown, the first is for "condition not met" whereas the second is for "condi- 
tion met". 

Detailed timing for instructions is provided by Figures 4-12 through 4-30. Table 4-5 identifies the timing diagram that 
applies to each instruction. 

Instruction object codes are represented as two hexadecimal digits for instructions without variations. 

Instruction object codes are represented as eight binary digits for instructions with variations; the binary digit 
representation of variations is then identifiable. 

The NEC 8080A has four instructions with execution times that differ from the Intel 
8080A. These four instructions are the Register Move (MOV), the Return (RET), the 1 6-bit Add 
(DAD), and the Exchange instructions XTHL and SPHL. 



NEC 8080A 

INSTRUCTION 

EXECUTION 

TIME 

DIFFERENCES 



O 

< 

< 



4>, 



*. 



SYNC 
READY J V. 

A 



WAIT 



DBIN 

A 



WR 



Ai 
Di 



• Instruction Fetch- 



Instruction 
Execute 



MCI 




V Status _ yDatainStablelT 



Rr/wo 

Ml 
MEiVIR 



f 



Instruction 
Code 



Figure 4-12. Signal Sequences and Timing for Instructions: 

STC, CMC. CMA. NOP, RLC, RRC, RAL, RAR, XCHG, El, 

DI, DAA, ADD R, ADC R, SUB R, SBB R, ANA R, XRA R, ORA R, CMP R 



4-33 



-Instruction Fetch - 



Instruction 
Execute 



MCI 




T2 



n ^rv 



T3 



f 



T4 



Instruction Address 



Instruction 
Code 



a 



T5 



n_ 



n 



Figure 4-13. Signal Sequences and Timing for Instructions: 
INR. DCR, MOV REG REG. SPHL. PCHL, DCX. INX 




n f\ 




Instruction Addr« s 



]f Sulul \ pminSlibnl 



Figure 4-14. Signal Sequences and Timing for Instructions: 
DCR. INR, MVI M 



4-34 



I . . r . u Instruction 

-Instruction Fetch ^ r 

Execute 



T2 




r\_ 



2 




T2 



a 



Instruction Address 



y Status I yPalainSlablfJ 



t 



Instruction 
Code 



sr—r: 



\ Status " ][DatamSlable][ 



Figure 4-15. Signal Sequences and Timing for Instructions: 

LDAX. MOV REG M, ADI, ACI, SUI, SBI, AN), XRI, ORL.CPI, MV! R, ADD M, 

ADC M, SUB M, SBB M, ANA M, XRA M, ORA M, CMP M 



, r- .- Instruction 

Instruction Fetch > c - i« 

Execute 




n 



a 



"^ 



Instruction Address 



J Status JDataiiiSlablfj] 



T? 




T3 



Figure 4-16. Signal Sequences and Timing for Instructions: 
STAX..MOV M REG . 



4-35 



WR •/ V 




T2 T3. 



Figure 4-17. Signal Sequences and Tinning for Instructions: 
LHLD 




Figure 4-18. Signal Sequences and Tinning for Instructions: 
PUSH. RST 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Tl 



-Instruction Fetch- 



Instruction 
Execute 




n r\ 



T4 



r\_ 



Instruction 
Code 



T5 



n 



T3 




^ r\ 



T2 



Figure 4-19. Signal Sequences and Timing for Instructions: 
POP. RET 



">1 

"'2 

SYNC 

READY J «- 

WAIT -' *■ 

DBIN 

wr" J »- 

Ai 
Di 








Instruction 


, 




In-r E •" 










Execute 














MCI 


MC2 


MC3 


Tl 


T2 


T3 


T4 


Tl 


T2 


T3 


Tl 


T2 


T3 


n 


'^ 


n 


n 


n 


n 


n 


n 


n 


n 


^.j'\— 




sH 


— sO— 


— iTV— 


__r\_ 


__n_ 


^_7'\_ 


_j~\_ 


__n_ 


— r\_ 


k 


t^ 


\ 


\ 














-p 


/ 


Y 








\ 














1 


/ 


i 




1 
















\ 




\. 


J 


















LV 


i 


\ 






/ 














W 


\ 




/ 
















\i ^ 


\ Instruction Address 


\ . 


^ ^ 1 


ion 


■ 


i S,3, 


us yDatainSlableJ 






Bl WO 
MEMR 


Instruct 
Code 







Figure 4-20. Signal Sequences and Timing for Instructions: 
DAD 




Figure 4-21. Signal Sequences and Tinning for Instructions: 
XTHL 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 




Figure 4-22. Signal Sequences and Timing for Instructions: 
LXI, JMP, JNZ. JZ. JNC. JC, JPO. JPE, JR. JM 




Figure 4-23. Signal Sequences and Timing for Instructions: 
STA 



-Instruction Fetch - 




-Instruction Fetch- 



n_ 



nr \ \ Data Addrt 

Status jpata in Stable 



figure 4-24. Signal Sequences and Timing for Instructions: 
LDA 







„s„„c„onF.,c 




E.ecuie 

























































MCI 


MC2 


MC3 


MC4 


MC5 






T, 


^2 


T3 


T4 


T,- 


T2 


T3 


T. 


T2 


T3 


T. 


^2 


'3 


" 


T2 


T3 






n 


'^ 


n 


n 


n 


^ 


r\ 


n 


? 


n 


1 


1^ 


k k 1^ 


h \ 






^ 


1^ 


_sn_ 


^ 


-ViH— 




—^X- 




._s5r\_ 


<r 


L_ 


-^^5^"^— 




\^ 


^ 


-.45~\_ 


-S5r\— 


\n 




r 
r 




Aa 


\ 


,Ar- 




\ 


H 


\ 


A^ 


H 




A^ 


R 


\ 




■ 


' 






'^ 








/ 






Y 




^ / 




\ 








EADY J V 


/ 


/ 












1 


,/ 


/ 


i 






1 










1 














/ 






\ 




J 


I 


A 


/ 










/ \ 








/ 






-U 


V 




i 


1-^ 


If 


/ 


D8IN 


\ 


T 




/ 


\ 






\ 






\ 




/ \ 


\ 






/ , 


/ 


wrW 


\ 


1 




/ 


^ 






\ 


\ 




\\ ■ 




\ 






















Ai 


\* 


V \ 1 


\k \ 


\ Oa.aAdd.eH 


\y ^ 




\i( 




\r 














\ 


s. s 1 


>> ■ 


\ \ 1 


y 


i i 


V 


i i 




Oi 


/ ... : i(o«.,,s,„»i 




I Soiu 


^ |(o^.s,„,.| 


_ji s,.,„ : K.„.;s,„,,j -■ 


J -■• y - s 


I -.. ■ J -■...- 




r 






R. ^ 


,nt,.c„on 




R./WO 






SeS 








:;■.. 












r.'.'.^ 











Figure 4-25. Signal Sequences and Timing for Instructions: 
SHLD 



© ADAM OSBORNE & ASSOCIATES. INCORPORATED 




Figure 4-26. Signal Sequences and Timing for Instructions: 
CALL. CNZ, CZ. CNC. CC. CPO. CPE. CP, CM 



-Instruction Fetch- 



T2 




r\_ 



T3 



rv 



If Condition Test Fails, 
Instruction Ends Here- 
Instruction 
Execute 



T4 



n 



/\ 



fA r\ 





T2 



.n. 



Instruction Address 



Data In stable! 



Instruction 
Code 



Data in Stable! 



Figure 4-27. Signal Sequences and Tinning for Instructions: 
RNZ, RZ. RNC, RC, RPO, RPE. RP. RM 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Tl 



-Instruction Fetch- 



Instruction 
Execute 




T2 



n 



T3 



s 



T4 



Instruction Address 



Instruction 
Code 




a 




Figure 4-28. Signal Sequences and Timing for Instructions: 
IN 



-Instruction Fetch- 



Instruction 
Execute 



T2 



T3 



T3 



T2 




r\ r\ 




Instruction Address- 



Instruction 
Code 



Figure 4-29. Signal Sequences and Timing for Instructions: 
OUT 



ADAM OSBORNE & ASSOCIATES. INCORPORATED 



-Instruction Fetch- 




n r\ 



Inslruction Addn 




LEiiZ, 



'^-. 



f^X 



TW 



Interrupt Terminates Halt - 




r\_ 



: nfn c 



Figure 4-30. Signal Sequences and Timing for Instructions: 
HLT 



SUPPORT DEVICES THAT MAY BE USED 
WITH THE 8080A 

Of the microprocessors described in this bool<, none have a wider variety of support devices than the 8080A. 
These support devices are described in the rest of Chapter 4 and in Volume III. Most of the devices described 
were originally developed by Intel, although a few were not. Note that the 8224 Clock Generator and the 8228 
System Controller devices are used so routinely with the 8080A that they frequently are looked upon as a three-chip 
CPU. An exception to this three-chip concept is the TMS 5501 made by Texas Instruments; it cannot be used with an 
8228 System Controller. , • 

A number of general-purpose support devices are described in Volume III. These are support devices that may be used 
with any microprocessor and are specific to none. 

One generalization that can be made regarding 8080A support devices is that the 8080A is so well endowed with sup- 
port logic that it will rarely make much sense to use another microprocessor's support part in preference. 

It is very difficult to use 6800 support devices with the 8080A because 6800 support devices require a synchronizing 
strobe signal which is difficult to generate within an 8080A system. 

THE 8224 CLOCK GENERATOR AND DRIVER 

The primary purpose of this device is to provide the 8080A CPU with its required 4>1 and 02 clock signals. Coin- 
cidentally, the 8080A READY and RESET inputs are created, with correct synchronization. Recall that these two 
signals must be synchronized with 4>2. 

Logic implemented on the 8224 Clock Generator corresponds generally to the block labeled "Clock Logic" in 
Figure 4-1 . To be completely accurate, however, a small portion of the Bus Interface Logic should also be illustr- 
ated as provided by the 8224 device. 

8224 CLOCK GENERATOR PINS AND SIGNALS 

8224 pins and signals pre illustrated in Figure 4-31. Figure 4-33 illustrates the 8224 connected to an 8080A 
CPU and an 8228 Systepi Controller. 

Signals may be divided between timing logic and control logic. 

Clock frequency is controlled by a crystal connected to the XTAL1 and XTAL2 pins. Crystal 
frequency must be exactly nine times the required clock frequency. The fastest clock period 
supported today is 250 nanoseconds, provided by the AMD 9080A. 500 nanosecond clock 
periods are standard. Since crystal frequency has to be nine times the clock frequency, the usual 
500 nanosecond clock will require an 18 MHz frequency crystal. 

If an overtone mode crystal is employed, then it must be supported by an external LC network, connected to 
the TANK input. This is standard clock logic practice; microprocessor clock logic represents no special case, therefore 
we will not discuss overtonemode crystals further. 



8224 

CLOCK 

SIGNALS 



4-46 



o 

CQ 
(/) 

o 

< 

Q 

< 

® 




PIN NAME DESCftlPTION TYPE 

RESET Control signal output to 8080A Output 

RESIN Reset logic input Input 

RDYIN Ready logic input Input 

READY Control signal output to 8080A Output 

SYNC Control signal input from 8080A Input 

<t>2 (TTL) TTL level duplicate of 4>2 Output 

STSTB Sync signal output to 8228 Output 

XTAL1,XTAL2 External crystal connections Input 

TANK Overtone crystal extra input Input 

OSC Crystal oscillator waveform Output 

<t>1, (t>2 Clock signals to 8080A Output 

Vqq.Vqq.GND Power and Ground 



Figure 4-31. 8224 Clock Generator Signals and Pin Assignments 

The principal clock signals output are <l>1 and 02, as required by the 8080A CPU. These two clock signals are 
derived from a divide-by-nine counter that defines <t>1 and <I>2 as follows: 



<P\ 



<t)2 



1 



/ 



I I I 

Two additional timing signals are output: 

The crystal oscillator frequency is output as OSC. 

A TTL level duplicate of 4>2 is also output for general use within the microcomputer system. 

The RESET input signal required by the 8080A CPU is usually generated by special external logic to provide 
sharp signal edges and synchronization w/ith the 02 clock pulse. Consider one common use of RESET — to detect 
power failure. A vague input may have to be converted into a crisp RESET as follows: 

Threshold 



Input (RESIN) 




4-47 



The 8224 Clock Generator will accept a sloppy input, as illustrated above by RESIN, and in response will create 
a sharp RESET output that conforms to the requirements of the 8080A CPU. A Schmitt trigger within the logic of 
the 8224 clock chip creates the appropriate reset logic level change when RESIN falls below a threshold level. 

RESET is also frequently connected to nnanually operated switches; this allo ws the microcomputer system to be reset 
by human intervention. The following simple circuit creates the appropriate RESIN input to the 8224 Clock Generator 
so that either power failure or an external switch may reset the CPU: 

Vqq (Power fail detect source) 



manual 
switch 



■ RESIN 



READY logic accepts an asynchronous RDYIN signal and creates a synchronous READY input to the 8080A 
CPU: 



<J>2 



RDYIN 



READY 



J~A 




One further signal created by the 8224 Clock Generator is the status strobe signal STSTB, which is required by 
the 8228 System Controller. This signal is of very little interest to a user since it simply accepts an 8080A SYNC out- 
put and converts it into the required 8228 STSTB input. 

When comparing the 8080A microcomputer system with other devices, it would be inaccurate to dismiss the 
8224 Clock Generator simply as an additional device — which must be added to an 8080A system, supplying 
logic which is commonly found on competing CPU chips. Do not forget the reset logic capability provided by the 
8224 Clock Generator. ' ' 

it can be argued that the 8080A CPU creates an artificial restriction — that RESET and READY inputs must.be syn- 
chronized with <&2; therefore the fact that the 8224 does this for you, simply eliminates a self imposed problem that 
should never have been there in the first place. This reasoning has merit, but the ability of the 8224 to receive a ragged 
RESIN input is a valuable feature that should not be overlooked. 

THE 8228 AND 8238 SYSTEM CONTROLLER AND BUS DRIVER 

The 8228 System Controller consi sts of a bidir ectional bus driver, plus control signal generation logic. The 8238 
System Controller advances l/OW and MEMW to give large memories more time to respond to a memory write. 

BUS DRIVER LOGIC 

A large nunriber of memory and I/O devices may be connected directly to the 8228 bidirectional Data Bus; such 
(Connections' to the 8080A Data Bus would not be feasible. Remember, memory devices leak current even when 
they are not selected; therefore, even the passive load of unselected memory devices connected directly to an 8080A 
CPU willleak more current than is available. 



4-48 



When comparing the 8080A microcomputer system with an alternate microcomputer system, you should look 
carefully at the fan out provided by the alternate CPU. 

If the alternate CPU busses need to be buffered, then the 8228 Systenn Controller becomes the equivalent 8080A 
system device; as such it does not represent an economic liability. 

If the alternate CPU busses do not need to be buffered, then the 8228 System Controller represents an additional 
device, peculiar to the 8080A system. 

CONTROL SIGNAL LOGIC 

The 8228 combines the three 8080A control signals: WR, DBIN and HLDA, with the statuses output on the 
Data Bus during T2 in order to generate bus control signals as follows: 

MEMR status on D7 true, with DBIN true generates MEMR true 
OUT status on D4 false, with WR true generates MEMW true 
INP status on D6 true, with DBIN true generates I/OR true 
OUT status on D4 true, with WR true generates l/OW true 
INTA status on DO true generates INTA true 



< 

Q 

< 




PIN NAME DESCRIPTION TYPE 

DO - D7 Data Bus connection to CPU Bidirectional 

DBO - DB7 Data Bus to external logic Bidirectional 

STSTB Status strobe input from 8224 Input 

HLDA Hold acknowledge input from CPU Input 

WR Data output strobe, input from CPU Input 

DBIN Data input strobe, input from CPU Input 

l/OW I/O write control output Output 

MEMW Memory write control output Output 

I /OR I/O read control output Output 

MEMR Memory read control output Output 

INTA Interrupt acknowledge control Output 

BUSEN DB Bus float/enable control input Input 

^CC' ^^^ Power and Ground 



Figure 4-32. 8228 System Controller Signals and Pin Assignments 

8228 SYSTEM CONTROLLER PINS AND SIGNALS 
8228 pins and signals are illustrated in Figure 4-32. 

DO through D7 represent the bidirectional Data Bus connection between the 8228 System Controller and the 8080A 
CPU; it is referred to as the "Processor Data Bus". 

DBO through DB7 represent the high fan out, bidirectional Data Bus accessed by external logic; it is referred to as the 
"System Data Bus". 



4-49 



WR, DBIN and HLDA represent the control signals of the same name that are output by the 8080A CPU 
All control bus signals use active low logic and may be defined as follows: 



MEMR — -a read from memory strobe 
MEMW — a write to memory strobe 
I/OR — a read from external I/O strobe 
l/OW — a write to external I/O strobe 
INTA — interrupt acknowledge 
Control signal timing is given in Figure 4-34. 

The interrupt acknowledge signal INTA has two special features which need to be explained. This signal may be 
tied to a +1 2 Volt power supply through a 1 K Ohm resistor, in which case 8228 logic assumes that there is only one 
possible interrupting source within the microcomputer system. Now the 8228 will automatically insert the object 
code for an RST 7 instruction in response to the interrupt acknowledge. This means that external logic does not 
need to supply the first post-interrupt instruction's object code. Of course, this means that all interrupt service routines 
effectively begin with the execution of an RST 7 instruction. 

If external logic responds to the INTA low pulse by supplying the first byte of a CALL i nstru ction's object code 
(11001101), then the 8228 System Controll er wi ll automatically generate two more INTA low pulses for the 
next t wo m achine cycles. See Figure 4-34 for INTA pulse timing within the machine cycle. Now external logic can 
use the INTA pulse as a memory deselect and an interrupt acknowledge logic select. Here is a very general illustration 
of external logic that responds to an interrupt acknowledge by supplying the CPU with a three-byte CALL instruction's 
object code: 



INTA' 

from 

8228 



T 



Any pulse 
count logic 



Select true on 
first INTA pulse 



i 



Select true 
on second 
INTA pulse 



Select true on third 
INTA pulse 



i 



Data Bus to CPU 



-^^ Program memory 
select (High true) 



8-bit port, 
holds 11001101 
(a CALL instruction) 



8-bit port, 
holds Call 
address, low 
order byte 



8-bit port, 
holds Call 
address, high 
order byte 



4-50 



o 

CO 

en 
O 

< 

< 
@ 



SYSTEM DMA REQ.- 
SYSTEM m. REQ.- 



TANK 

OSC 

*2(TU1 



>2(rai-«-4 — 

ROYIN i; V^ 
RESIN — 5*"^ 



eOi 



6224 

CLOCK 

GENERATOR 

DRIVER 



BUSBi ■ 




_ ADDRESS 
' BUS 



-A12 
-A13 
>A14 
>A1S 



STATUS STROBE 



^DATA 
BUS 



CONTROL 
BUS 



Figure 4-33. A Standard, Three Device 8080A IViicrocomputer System 



• Instruction Fetch ■ 



InstniCtion 
Execute 



MCI 



T2 



f 



n__yu_jn_^n__A 




Figure 4-34; Timing for Control Signals Output by 
the 8228 System Controller 



4-51 



Recall that the NEC 8080A generates three INTA low output pulses in response to a Call instruction object code being 
returned during the interrupt acknowledge process. But the NEC 8228 Systenn Controller does not assume that these 
three low INTA pulses will occur. Thus the NEC 8228 System C ontro ller may be used with an NEC 8080A or any 
other 8080A. In every case the NEC 8228 will generate three low INTA output pulses when external logic responds to 
an interrupt acknowledge by providing a Call instruction object code. 



The status s trobe STSTB which is output by the 8224 Clock Generator is a variation of the SYNC output from the 
8080A CPU. STSTB synchronizes the 8228 System Controller and is of no other concern to an 8080A user. 



BUSEN is an external input to the 8228 System Controller. This is a very useful signal because it allows external 
logic to float the Data Bus. When this signal is input low, the bidirectional bus driver logic of the 8228 System 
Controller presents a high impedance to the external Data Bus, thus allowing external logic to gain access to 
this bus. 

Figure 4-33 illustrates the way in which the 8080A CPU normally combines with the 8224 Clock Generator and the 
8228 System Controller. These three devices are frequently looked upon as a single entity. 

THE 8259 PRIORITY INTERRUPT CONTROL UNIT (PICU) 

This is a very flexible, programmable inter rupt handling device; it provides a CALL instruction's object code in 
response to three interrupt acl<nowledge (INTA) signals; the 8228 System Controller responds to an interrupt 
acknowledge in this fashion, as described earlier in this chapter. Therefore the 8259 PICU should be looked 
upon as a companion to the three-chip (8080A, 8224, 8228) microprocessor system. 

The 8259 PICU cannot be used with non-8080A systems. 

A single 8259 PICU with an 8080A microcomputer system will handle up to eight external interrupts, providing 
a variety of programmable interrupt priority arbitration schemes. 

Alternatively, an 8080A microcomputer system may have a single 8259 PICU designated as a master, controll- 
ing up to eight additional 8259 PICUs designated as slaves. This allows a maximum of 64 levels of interrupt 
priority. Priority arbitration schemes may be set independently for the master and for each slave, resulting in a 
bewildering profusion of priority arbitration possibilities. 

Use extreme caution before including master and slave PICUs within an 8080A microcomputer system. When 
an application is implemented around a microprocessor with the general speed and performance characteristics 
of an 8080A, then it is usually more efficient to handle numerous external request lines using multiple CPU con- 
figurations and/or programmed polling techniques, rather than interrupts. 

The 8259 PICU is fabricated using NMOS technology; it is packaged in a 28-pin plastic DIP. All outputs are TTL 
compatible. 

With reference to the standard logic functions' illustration used throughout this book, the box marked "Interrupt 
Priority Arbitration" represents the functions implemented by the 8259 PICU. But it is hard to equate the large number 
of options provided by the 8259 PICU with the interrupt logic provided by other microcomputer systems. An applica- 
tion that needs the 8259 PICU would certainly not be satisfied by Interrupt Priority control logic provided by almost any 
other device described in this book. 

8259 PICU PINS AND SIGNALS 

8259 PICU pins and signals are illustrated in Figure 4-35; we will summarize these signals, then discuss how 
the PICU is used. 

From the programmer's point of view, the 8259 PICU will be accessed either as two I/O ports, or as two memo- 
ry locations. CS is a typical chip select and AO identifies one of two I/O ports or memory locations. The way you, 
as a programmer, must interpret the function of each 8259 PICU I/O port or memory location depends on an intricate 
logical sequence. 

The two 8259 addressable locations are accessed via the Data Bus (DO - D7). 

lOR and lOW are standard read and writ e co ntrol signa ls. If the 8259 PICU is being accessed as two I/O ports, then 
these two signals will be connected to the I/OR and l/OW controls outp ut b y the 8228 System Controller; on th e other 
han d, if the 8 259 PICU is being accessed as two memory locations, then lOR and lOW must be connected to the MEMR 
and MEMW controls output by the 8228 System Controller. 

External devices requesting interrupt service have their request signals connected to IRO - IR7. A high level on 

any one of these signals will be interpreted as an interrupt request. An interrupt request is passed on to the CPU via 
the INT signal. This is illustrated in Figure 4-36. 

4-52 



o 

< 
< 



In a configuration that includes master and slave 8259 PICUs external logic will connect to the interrupt request 
signals (IRO - IR7) of the slave PICUs only. The INT outputs of the slave PICUs will be connected to the interrupt re- 
quests (IRO - IR7) of the master PICU. This is illustrated in Figure 4-37. 

When more than one 8259 PICU is present in a system, SP identifies the master and slave units. SP high defines the 
master, while SP low forces an 8259 PICU to operate as a slave. SP also determines the sense of the three cascade 
lines (CO, CI, C2); these are output lines from the master and input lines to a slave. 



The 8080A CPU provides the standard interrupt acknowledge via INTA. This interrupt acknowledge will be 
received by all 8259 PICUs in the system, master or slave. 

In a system that includes a master 8259 PIC U only , the three bytes of a CALL instruction's object code are out- 
put via the Data Bus in response to the three INTA control signals arriving from the 8228 System Controller. The 

second and third bytes of the CALL instruction's object code provide an address which is unique to the selected inter- 
rupt request. 

In a configuration that includes master and slave 8259 PICUs, the master PICU outputs the first byte of a CALL 
instruction's object code; the master also outputs a value between 000 and 111 via the three cascade lines 
(CO - C2). This three-bit binary value identifies the interrupt request level being acknowledged — and therefore 
the slave PICU being selected. The selected slave PICU p rovide s the second and third bytes of the CALL in- 
struction's object code in response to the second and third INTA pulses output by the 8228 System Controller. 
Thus the slave PICU identifies the interrupt request level it is acknowledging. 

The interrupt acknowledge logic of the 8259 PICU is referred to as "Vectoring". Let us examine 8259 vectoring 
in more detail. 




8259 

PRIORITY 

INTERRUPT 

. CONTROL 

UNIT 



PIN NAME 
CS 
AO 

D0-D7 
iOR 

low 

IRO - IR7 
INT 
INTA 
SP 

C0-C2 

Vcc. GND 



DESCRIPTION 

Device Select 

Identifies PICU as one of two 

I/O ports or memory locations 

Data Bus 

Read control signal 

Write control signal 

Interrupt request lines to PICU 

Interrupt request sent by PICU 

Interrupt acknowledge 

Identifies PICU as either master 

or slave 

Cascade lines select slave in 

multiple PICU systems 

Power and Ground 



- Vcc 

AO 

"-^ INTA 

IR7 

- — IR6 

IR5 

IR4 

IR3 

IR2 

IR1 

IRO 

-•*- INT 

SP 

^ C2 

TYPE 
Input 
Input 

Tristate, Bidirectional 
Input 
Input 
' Input 
Output 
Input 
Input 

Output on master 
Input on slave 



Figure 4-35. 8259 Priority Interrupt Control Unit Signals And Pin Assignments 



4-53 



8080A 
CPU 



■ ^ f * 



MEMR or l/QR 



A1& 



address: 
DECODING 



f DO 



8259 
PRIORITY 
INTERRUPT 
CONTROL 

UNIT 



rm 



DEVICE 




8228 

SYSTEM 

CONTROLLER 



. AO 
A1 
a'i5 
DO 
D*7 



DEVICE 
1 



DEVICE 



DEVICE 
7 



Figure 4-36. A System With One PICU 



THE 8259 PIGU INTERRUPT ACKNOWLEDGE VECTOR 

Vectoring is a general term used to identify an interrupt acknowledge sequence which results 
identification of the interrupting external source. With a non-vectored interrupt acknowledge, 
ecute sorrie instruction sequence whose sole purpose is to identify the source of the interrupt — 
nnore than one possible external interrupting source. 

Recall that when an interrupt request is 'acknowledged by a thr ee-dev ice 8080A nnicroprocessor 
system, the 8228 Syst em C ontroller outputs a low pulse on the INTA control line. External logic 
must interpret the low INTA pulse as a signal to bypass normal instruction fetch logic, and provide 
the object code for the first instruction to be executed following the interrupt acknowledge. (If this 
is new to you, refer to our discussion of the8080A and 8228 devices.) If a C ALL instruction's ob- 
ject code (CD-is) is returned to the 8228 System Controller, then low INTA pulses are output for 



in the immediate 

the CPU must ex- 
and that assumes 



8080A 
INTERRUPT 
RESPONSE 
USING CALL 
INSTRUCTION 



4-54 



the next two machine cycles — thus making it easy for external logic to fetch all three bytes of a CALL instruction's ob- 
ject code. The 8259 PICU uses this 8228 logic to supply a three-byte CALL instruction's object code as the first 
instruction executed following an interrupt acknowledge. But a CALL instruction's object code is interpreted 
thus: 



Byte 1 



Byte 2 



Byte 3 



O 
CD 
CO 

O 

< 
< 
@ 



CALL 



16-bit address of called subroutine's 
first executable instruction 



There are two ways in which the 8259 PICU can compute the address portion of the CALL instruction object 
code (bytes 2 and 3). These are the two options: 



Option 1 
XXXXXXXXXXXYYYOO 



Option 2 
XXXXXXXXXXYYYOOO 



X represents binary digits which are defined, under program control, to be a constant portion of the Call address. 

Y represents binary digits which identify the interrupt priority level (000 through 111). 

Since the CALL is the first instruction executed following an interrupt acknowledge, it causes program logic to branch 
to a memory location which is uniquely set aside for a single external interrupting source. Suppose you have selected 
CALL instruction Option 1, as illustrated above. You would then Set aside an area of memory for a jump table, as 
follows: 



XXXXXXXXXXXYYYOO 

001 1 100000000000 

1 

1 

1 1 

1 
etc 



PROGRAtyi 
MEMORY 




3800 


C3 














3804 


C3 














3808 


C3 














380C 


C3 














3810 


C3 



JMP 
'. ADDR 1 

Unused 
JMP 

I. ADDR2 

Unused 
JMP 

[ ADDR3 

Unused 
JMP 

tADDR4 

Unused 



Memory addresses have been selected arbitrarily in. the illustration above. 



4-55 



Program logic does not have to determine the source of an interrupt. You simply origin separate interrupt service 
routines at starting addresses specified by the Jump instructions in the jump table. This may be illustrated as follows: 



PROGRAM 
MEMORY 



3800 


C3 




80 




OF 






3804 


"C3 




00 




OF 






■^ 3e6r 


«iCC3 




• '00. 




OE'^ 






380C 


C3' 




80 




66 







MORE 
PROGRAM 
MEMORY 



JMP ADDR2 



OEOO 




0E01 




0E02 




0E03 




0E04 

















































ADDR2 



The illustration above arbitrarily assumes that the interrupt request arriving at IR2 has its service routine origined at 
OEOOis- 'n this example, the address vector provided by the 8259 is 380816^ 



XXXXXXXXXXXYYYOO 
001 1 100000001000 



80SOA 
CPU 



♦ ao . . ■ 



ADDRESS 
DECODING 



ICS 



I DO 



3Fr 



8259 

PICU 

(Master) 



To level 7 
Slave CS 



,. i, ,. 



To level 6 
Slave CS 



t 



I DO • 



JFT 



8259 
PICU 
(Slave) 



MEMR orTTOR 



* AO (from Address Bus) 

- C3 (from Address 
Decoding) 



5Pp— 



8259 
PICU 
(Save) 



iov7 



8228 

SYSTEM 

CONTROLLER 



■ AO (from Address Bus) 

■ ^ (from Address Decoding logic) 



DEVICES AT MASTER PICU LEVEL 7 



DEVICES AT MASTER PICU LEVEL 6 



Figure 4-37. A System With Three PICUs — One Master And Two S]aves 



4-56 



< 

lU 

z 
cc 
o 

CQ 
(O 
O 

< 
o 
< 

@ 



At memory location 380816- the object code for the instruction; 

JMP ADDR2 

takes us directly to the required interrupt service routine. 

8259 PICU PRIORITY ARBITRATION OPTIONS 

Priority arbitration logic is used to determine which interrupt request will be acknowledged when two or more 
interrupt requests exist simultaneously. The 8259 PICU allows interrupt priorities to be specified at two 
levels — which need to be clearly separated and identified. 

As discussed in Volume I — Basic Concepts, interrupt priority arbitration usually applies to simultaneous interrupt re- 
quests; at the instant an interrupt is acknowledged, if more than one external requesting source is requesting an in- 
terrupt, priority arbitration logic decides which single interrupt request will be acknowledged. Once an interrupt 
has been acknowledged, priority arbitration has nothing to do with whether the interrupt service routine can itself be 
interrupted, or by whom. 

The 8259 PICU extends interrupt priorities to the service routines themselves. Once an interrupt has been 
acknowledged, its service routine can only be interrupted by a higher priority interrupt. 

If you are unsure of the difference between interrupt priority arbitration at the point when interrupts are acknowledged, 
as against priority arbitration for the entire duration of an interrupt service routine, then refer to Volume I — Basic Con- 
cepts, where this subject is covered thoroughly. 

Let us now look at the various priority arbitration options provided by the 8259 PICU. 

The Fully Nested Mode is the default case. Interrupt priorities are set sequentially from (highest) to 7 (lowest). 

As we will describe shortly, the 8259 PICU must be initialized by an appropriate instruction sequence before it can 
be used in any way. Upon completing programmed initialization, Fujly Nested Mode is t\\e priority arbitration op- 
tion in force. It takes additional instructions to specify any other priority arbitration option.- 

In Fully Nested Mode, interrupt priorities will never change. An interrupt request arriving at an IR 
line will never be acknowledged if an interrupt request exists at a higher priority line, or if an inter- 
rupt service routine is being executed in response to a higher priority interrupt request. Conver- 
sely, once an interrupt has been acknowledged, the interrupt service routine which is subse- 
quently executed may be interrupted only by a higher priority interrupt. It makes no difference 
whether interrupts have, or have not been disabled, the 8259 PICU will ignore all interrupt re- 
quests at priority levels below that of an interrupt service routine currently being executed. For example, suppose inter- 
rupts are being requested simultaneously at levels 2 and 5. The level 2 interrupt will be acknowledged and its interrupt 
service routine will be executed. While the level 2 interrupt is being executed, the level 5 interrupt request will be 
denied by the 8259 PICU, whether or not interrupts have been disabled at the CPU. However, if an interrupt request ar- 
rives at priority level 1, the PICU will acknowledge this interrupt request, and will allow the level 2 interrupt service 
routine to be interrupted. This may be illustrated as follows; 

Interrupts are requested 
via lines IR2 and IR5- 



8259 PICU 

INTERRUPT 

SERVICE 

ROUJINE 

PRIORITIES 



,-^ 



Denied —IRS IR2 — acknov/ledged 



Program 
executing 



New interrupt 

request appears 

at IR1 

Interrupt is 

higher priority 

than IR2, so 

is acknov/ledged 




An Interrupt request at IR5, 
if still pending, can now 
be acknowledged 



IR2 request's 
service routine 
is executed 



!R1 request's 
service routine 
is executed 



4-57 



It is very important to understand that the 8259 PICU extends interrupt priority logic beyond the interrupt 
acknowledge, to the interrupt service routine itself. Standard priority arbitration logic does not extend to the interrupt 
service routine. Thus, in the standard case if interrupts were being requested at priorities 2 and 5, then the priority level 
2 request would be acknowledged, but the priority level 2 interrupt service routine could be interrupted by the level 5 
interrupt request, unless all interrupts were disabled at the CPU — in which case an interrupt request at level 1 would 
also be denied. 

If you do not want to extend interrupt priorities to the interrupt service routines, you can output a Special Mask Mode 
comrpand (vyhich we will describe shortly) to selectively enable interrupt requests of lower priority than the currently 
executing interrupt service routine. 

Rotating Priority, IVIode A is the next option. This differs from the Fully Nested Priority Mode, 
which we just described, in that after being serviced, a request is immediately relegated to lowest 
priority. This may be illustrated as follows: 



8259 PICU 

ROTATING 

INTERRUPT 

PRIORITIES 



Priorities assigned to IR lines 



Lowest 














Highest 


7 


6 


5 


4 


3 


2 


1 





IR7 


IR6 


IRS* 


IR4 


IR3 


IR2» 


IR1 


IRO 


IR2 


IR1 


IRO 


IR7 


IR6 


, IR5» 


IR4 


IR3 


IR5 


IR4 


IR3 


IR2 


IR1 


IRO 


IR7 


IR6 



Before first acknov/ledge 
After first acknowledge 
After second acknov/ledge 

* idqptifies active interrupt requests. 

In a microcomputer system that makes heavy use of interrupts. Rotating Run in Priority Mode A may be a necessary 
replacement for the default Fully Nested Priority Mode. In the default case, the lowest priority levels may get little or no 
service if there is heavy interrupt traffic. In an application that does not have a well defined hierarchy of interrupt 
priorities, a rotation of priorities, as illustrated above, is superior — because it has the effect of giving every priority 
level equal service. • 

Rotating Priority Mode A is implemented as a sequence of single programmed events. The microprocessor outputs an 
appropriate Control code to the 8259 PICU upon completingevery interrupt service routine. Thus Rotating Priority 
Mode A is not a permanently specified PICU condition; each rotation represents a single response to a single Control 
code — unconnected to previous or future priority selections'. For the moment, however, it is not necessary that you un- 
derstand the programnriing techniques employed when selecting 8259 interrupt priority rriodes; that is a subject we 
will cover after completing the description of all available priority options. 

Rotating Priority Mode B gives you some flexibility in determining future priorities. Now under program control 
you can fix the next division between top and bottom priorities at any time. This may be illustrated as follows: 

Priority assigned to IR lines 



Before first ackpov^ledge 
After first acknowledge 

IR5 is defined as . 

lowest priority 
After next acknowledge 

IRS is defined as 

lov/est priority 





Lovyes 


■ 






Highest 




7 


6 


5 


,4 


3 


2 1 





IR7 


IR6 


IRS 


IR4 


IRS 


IR2 IR1 


IRO 


IRS 


IR4 


IRS 


IR2 


IR1 


IRO IR7 


IR6 



IRS 



IR2 



IR1 



IRS 



IR4 



4-58 



o 

CD 
(/> 

o 

< 
< 



Rotating Priority Mode B allows program logic to determine subsequent interrupt priorities based upon transient 
system conditions. Rotating Priority Mode B rotates priorities any number of positions to the right, much as you might 
rotate the bits of an Accumulator. 

Like Rotating Priority Mode A, Rotating Priority Mode B depends on the microprocessor outputting an appropriate Con- 
trol code to the 8259 PICU. However, in Rotating Priority Mode A, rotation can be done only at the conclusion of an in- 
terrupt service routine, whereas in Rotating Priority Mode B, priorities can be changed at any time. 

Two mask modes allow individual priorities to be selectively disabled. A Simple Mask Mode 
allows the microprocessor to output an 8-bit mask, where 1 bits will cause corresponding 
interrupt request lines to be disabled. For example, the mask value CA-|g will disable interrupt 
lines IR7, IR6, 1R3 and IR1: 



8259 PICU 

INTERRUPT 

MASKING 



7 6 5 4 3 2 10 

|i|i|oio|i|oii|7] 






•Bit No. 

• Interrupt Mask 

■ These IR lines are selectively disabled. 



A Special Mask Mode is also provided; it allows you to enable interrupts at a lower priority level than that of the 
currently executing interrupt service routine. By writing a 1 to the appropriate bit of the Mask register, an interrupt 
level can be disabled while its interrupt service routine is executing. Even though the level is masked, all lower level in- 
terrupts will remain disabled until the conclusion of the service routine. Once the current level is masked, however, en- 
tering Special Mask Mode will enable all unmasked lower priority interrupt levels. Thus a request can interrupt a service 
routine operating on a higher priority level. 

Masks may be superimposed on Rotating Priority Mode A or Mode B without restriction. This allows you to selectively 
enable and disable individual interrupt request lines, then rotate priorities for the enabled lines. Special Mask Mode 
also allows you to selectively enable interrupts of lower priority than a currently executing interrupt service routine. 

Polled Mode bypasses priority arbitration altogether. If you select Polled Mode, then you 
must poll the 8259 PICU. You will interpret the polled data as follows: 



8259 PICU 
POLLING 




Bit No. 
Polled Status 



Highest priority level requesting 
an interrupt (000 through 111) 

Unassigned 

1 Interrupt request pending 

No interrupt requests pending 



In a configuration that includes master and slave 8259 PICUs, you will first read status from the master PICU. Upon 
detecting a 1 bit in bit 7, you will poll the slave PICU which is identified by bits 2, 1 and of the master's polled data. 
The slave poll identifies the highest priority interrupt request. This may be illustrated as follows: 



■ Bit No. 



Master. 



7 6 5.4 3 2 1 0-^ 




76543210 76543210 7 6 5 4 3 2 10-^ Bit No 

- 1 1 1 1 1 II II III 1 1 1 1 II cEnmrH— 



4-59 



Suppose the * represents interrupt requests. The master poll would return: 



7 6 5 4 3 2 10 



•Bit No. 



J 



nr 



The polling progrann must now poll slave 1; it will read: 

7 6 5 4 3 2 1 0-^- 



~ Priority 1 slave device 
- Requesting an interrupt 

' Bit No. 







m 



' Priority 3 interrupt request 
■ Requesting an interrupt 



In Polled Mode, the 8259 PICU is not being used as an interrupt processing device at all. In effect, interrupt requests are 
reduced to status flags, which will be processed by the CPU when it is ready to do so. External logic is no longer able to 
force the CPU to suspend current program execution: thus the key concept of an interrupt is missing. 

While it may not immediately appear obvious, using the 8259 PICU in Polled Mode is possibly one of the most 
effective ways of utilizing this device. A point we have frequently made, both in Volume I and in Volume II, is that 
the average microprocessor is simply too slow to efficiently handle random, nested interrupts in a traditional minicom- 
puter fashion. It is faster and more efficient to poll status on a round-robin basis, branching to appropriate subroutines 
upon detecting a status flag via which external logic has requested service. A detailed discussion of this point may be 
found in the book 8080 Pro g rammin g ForLo g ic Desig n. 

HOW INTERRUPT REQUESTS AND PRIORITY STATUS ARE RECORDED 

Internal to the 8259 PICU there are two registers', an Interrupt Request (IR) register and an interrupt Status (IS) 
register. 

The Interrupt Request and Interrupt Status registers may be looked upon as receiving external interrupt request 
status. in a cascaded fashion as follows: 



7 6 5 4 3 2 10 



Interrupt Status 
register (IS) 



I I II 11 lit 



Interrupt Request f 
register (IR) I 



,11 a ;,-,| II 11 

III II I IK 



Bit No. 

■INTA latches highest 
FHiority IR bit into IS 



IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR 



-IRN inputs set IR bits 
imnnediately INTA clears IR register 



IR6 IR5 IR4 IR3 IR2 IR1 IRO 

Any active interrupt request appearing on the interrupt request lines IRO - IR7 will set corresponding bits of the Inter- 
rupt Request register. When any interrupt is acknowledged, the acknowledged interrupts bit in the Interrupt Status 
register is set; simultaneously, all bits of the Interrupt Request register are reset. This may be illustrated as follows: 



IR(n) 



i 



Interrupt request signal 
IR register bit 



r 



ISin) 



(n) is the highest priority 

(i.e., acknowledged) interrupt request 



4-60 



In order to reset any bit of the Interrupt Status register you must issue a specific "End-Of-lnterrupt" instruction which 
we will describe shortly. 

You may therefore look upon the Interrupt Request register as identifying active, but unacknowledged interrupt re- 
quests. Notice that Interrupt Request status is not preserved across an acknowledge. This means external logic must 
hold its Interrupt Request true until it has been selected and acknowledged. 

You may look upon the Interrupt Status register as identifying the interrupt requests which are currently being ser- 
viced. If you do not nest interrupts, then only one bit of the Interrupt Status register will be set at any time. If you do 
nest interrupts, then more than one bit of the Interrupt Status register may be set — for the interrupt request being ser- 
viced currently and for any interrupt requests which were being serviced, but were themselves interrupted. But remem- 
ber you can misuse the Interrupt Status register. If you do not end interrupt service routines by outputting an "End-Of- 
lnterrupt" command to the 8259 PICU, then bits of the Interrupt Status register will remain set after the appropriate in- 
terrupt has been serviced. 

If you use a mask to inhibit interrupt levels, then the inhibit logic will prevent bits of the Interrupt Request and Interrupt 
Status register from being set for the inhibited interrupt levels. 

The Interrupt Request (IR) register stores a 1 bit at every requesting level; it may be visualized as a simple reflection of 
IR input signals: 



o 

CD 
CO 
O 

< 
o 

< 



7 6 5 4 3 2 1 0^ ^ 

IR7 IR6 IRS IR4 IR3 IR2 IR1 IRO 



' IR Register 



• represents active interrupt requests 

The Interrupt Status (IS) register reflects the status of current interrupt priority arbitration logic. Whenever an interrupt 
is acknowledged, the IS bit corresponding to the interrupt level is set. This bit is reset by the End-Of-lnterrupt (EOl) in- 
struction at the end of the interrupt service routine. We will tell you how to issue an EOl instruction shortly. 

Suppose the 8259 PICU is operating in the default mode: fully nested interrupts, no mask bits set. An interrupt request 
is made at level 4. When this interrupt is acknowledged, bit 4 of the IS register is set: 

7 6 5 4 3 2 10 



|o|o|o|i|o|o|o|o 



and interrupts at levels 5, 6 and 7 are disabled, since they are of lower priority than level 4. While the level 4 request is 
being serviced, a request is made at level 1. Since level 1 has higher priority, it will be acknowledged, interrupting the 
level 4 service routine. IS will look like this: 



7 6 5 4 


3 2 




|o| o|o|i 


olo 





Now interrupt levels 2 through 7 are disabled. At the conclusion of the level 1 service routine, EOl will reset bit 1: 



765432 1 

|o|o|o|i|o|o|oio 




thus enabling interrupt levels 2 and 3 — and level 4, whose service routine can now continue. On the next EOl, assum- 
ing no further interruptions, bit 4 of IS will be reset, at which time levels 5, 6 and 7 will again be enabled. 

In priority modes other than the Fully Nested Mode (Rotating Priorities A and B and Special Mask Mode) the 8259 PICU 
cannot be depended on to reset the correct IS bit when it receives the usual EOl. Therefore, it is sent a special EOl 
which specifies which level's service routine is ending — and therefore which IS bit is to be reset. 



4-61 



PROGRAMMING THE 8259 PICU 

As we have already stated, the 8259 PICU appears to the programmer as two I/O ports, or memory locations. 
However, there are a number of ways in which data written to, or read from either location may be interpreted. 
Let us begin by defining these interpretations; then we will explain the sequence in which Control codes should 
be written, and statuses read, in order to access the many capabilities of the 8259 PICU. 

Control codes output to the lower I/O port or memory address (AO = 0) may be interpreted in one of three ways, labeled 
Initialization Control Word 1 (ICW1) and Operation Control Words 2 and 3 (0CW2 and 0CW3): 

7 6 5 4 3 2 10 



I I I I'M I Ix 



Y*^i 


♦ 


t 















7 6 5 4 3 2 1 

i I I lolol I I \ 



Don't care 

1 One 8259 in a system only 

Master and slave 8259s in system 

1 4 bytes betVi^een address vectors 
8 bytes betv/een address vectors 

Must be 1 

Bits 7, 6 and 5 of interrupt address vector 




000 Select priority level as lovi/est 

001 Select priority level 1 as lovi/est 

010 Select priority level 2 as lowest 

01 1 Select priority level 3 as lowest 

100 Select priority level 4 as lowest 

101 Select priority level 5 as lov^est 

1 10 Select priority level 6 as lov/est 

1 1 1 Select priority level 7 as lowest 

Must be 00 

000 No Operation 

01 1 Simpile end of interrupt, ignore bits 2. 1, 

010 No Operation 

Oil Special end of interrupt, and reset IS bit specified by bits 2, 1, 

100 No Operation 

101 End of interrupt and execute Rotate Priority Mode A 

1 10 Execute Rotate Priority Mode B. Level set by bits 2. 1, is lovi/est level 

1 1 1 Er>d of interrupt and execute Rotate Priority Mode B. Level set by 
bits 2, 1. is lov/est level. 



7 6 5 4 3 2 1 



X 



•00 Not allovyed 
01 Not allov^ed 

10 Select IR register on status read 

1 1 Select IS register on status read 

• Normally 0. If 1, Polled Mode in force 

■Must be 01 

' 1 1 Select special mask mode 

10 Deselect sfiecial mask mode 
■ Don't care 



4-62 



< 

eS 
UJ 

Z 
c 
o 

CO 

v> 
o 

<' 

a 

< 

© 



When reading from the lower address (AO = 0), the condition of the nnost recently issued 0CW3 bits and 1 determine 
what will be read. If these two bits were 01 , the Interrupt Request register (IR) is read: if these two bits are 1 1 , the Inter- 
rupt Status register (IS) is read. 

Control codes output to the higher I/O port or memory address (AO = 1) may also be interpreted in one of three 
ways. After an ICW1 control has been output to the lower address (AO = 0), either one, or two Control codes must be 
output to the higher address (AO = 1). If ICW1, bit 1 is 1, a second Control code (ICW2) must be output to the higher 
address (AO = 1) of the master 8259 PICU, and to every slave 8259 PICU, that may be present. This is the format of 
ICW2: 

7 6 5 4 3 2 1 

nTTTTTT 




Bits 15 - 8 of the interrupt address vector 



If ICW1, bit 1 is 0, ICW2, as illustrated above, must be output — and it must be followed by a second Control code 
(ICW3), output to the higher address (AO = 1) of the master 8259 PICU, and then to each slave 8259 PICU. The master 
8259 will interpret ICW3 as follows: 

—Bit No. 



76 54 3 2 10- ^ 
I I I I I I I I I ^ iCW3 to master 




Any 1 bit identifies a request level to 
which a slave 8259 has been attached 



A slave 8259 will interpret ICW3 as follows: 

7 6 5 4 3 2 1 

cn 




Bit No. 

ICW3 to slave 



These three bits identify the 
request level at the nnaster 8259 
to v/hich this slave 8259 
has been connected 

Don't care 



A system with a single 8259, therefore, has ICW1, then ICW2 output to it. 

A system with master and slave 8259 devices must have ICW1, ICW2 and ICW3 output to the master, then ICW1, 
ICW2 and ICW3 output to each slave. 

After the initiation sequence has been completed, when reading or writing to the higher I/O 
port address (AO = 1), the Interrupt Mask register is accessed. Writing a 1 into any bit posi- 
tion will disable corresponding IR line requests. bits enable interrupt requests at corres- 
ponding IR lines. When you return to the initiation sequence, the higher I/O port address 
again accesses ICW2 or iCW3. 



8259 PICU 

INTERRUPT 

MASK 



4-63 



We will now examine the normal sequence in which the 8259 PICU will be programmed. Programming logic may be 
defined as follows: 




Write any initializing 
codes to master and 
slaves (H present) 



Modify interrupt enable/ 
disable if desired 



Execute interrupt service 
routine 



Interrupt 

Service 

Routine 



Write end of interrupt 
code 



4-64 



o 

m 

(0 

O 

< 

< 



Using arbitrary data, the initiation sequence for a single 8259 PICU systenn may be illustrated as follows: 

MVI PICUL,12H ;WRITE OUT ICW1 

MVI PICUH,40H iWRITE OUT ICW2 

The labels PICUL and PICUH address the lower and higher 8259 P|CU addressable locations, respectively. 

The two instructions above assume that the 8259 PICU is being addressed as memory. The two immediate data bytes 
specify an interrupt address vector beginning at location 4000i6. incrementing eight bytes with each priority level. 

Now consider a configuration where there is a master PICU and three slave PICUs connected to IRO, IR1 and IR2. Here is 
the initiating instruction sequence required: 

ilNITIAUZE MASTER PICU 

MVI PICUL14H 

MVI PICUH,40H 

MVI PICUH.07H 

;INITIALiZE FIRST SL-$<VE PICU 
' MVI SPCL1,10H 

MVI SPCH1,48H 

MVI SPCHI.O 

ilNITIALIZE SECOND SLAVE PICU 

MVI SPCL2,30H 

MVI SPCH2,48H 

MVI SPCH2,1 

;INITIALIZE TI-||BD SLAVE PICU 

MVI SPCL3.52H 

MVI SPCH3,48H 

MVI SPCH3,2 



WRITE OUT 1CW1 
WRITE OUT ICW2 
IDENTIFY SLAVES TO MASTER 

WRITE OUT ICW1 
WRITE OUT ICW2 
IDENTIFY PRIORITY TO SLAVE 

WRITE OUT ICW1 
WRITE OUT ICW2 
IDENTIFY PRIORITY TO SLAVE 

WRITE OUT ICW1 
WRITE OUT ICW2 
IDENTIFY PRIORITY TO SLAVE 



Since there is a single master, and three slaves, there must be four sets of initiating instructions. 

First, we initiate the master. Again, the interrupt address vector is origined at4000i6- This origin and the specification 
that four bytes will separate each vector will be used when interrupts are requested on levels to which no slave 8259 
PICUs are connected. In this case the value 07i6 is output indicating that IRO, IR1 and IR2 have connected slaves. 

Slave initiation is straightforward. The first slave PICU has labels SPCL1 andSPCHI, representing thelower'and higher 
addressable locations. SPCL2 and SPCH2 are second slave PICU labels, while SPCL3 and SPCH3 are third slave PICU 
labels. 

All three slave PICUs specify a four-byte displacement between interrupt address vectors. Initial origins of 480016- 
4820-1 6 and 4840i 6 are specified for slave 1 , 2 and 3, respectively. Notice that the second byte written but to the high 
order address SPCH1, SPCH2 or SPCH3 identifies the slave's priority. 

Once 8259 PICUs have been initiated, programmable features are controlled by outputting appropriate Control 
codes and inputting appropriate status. Every interrupt service program must end by outputting an "End-Of-ln- 
terrupt" Control code to the 8259 PICU. Any form of "End-Of-lnterrupt" Control code will do. Otherwise, there 
is no well defined sequence in which controls and status should be used. 



4-65 



Table 4-6. A Summary of 8259 PICU Operations 


OPERATION 


INSTRUCTION SEQUENCE 


Select Fully Nested 


None. This is selected after initiation. 


Mode 




Issue simple End Of 


Output 20i 6 (0CW2) to PICUL 


■Interrupt command 




Rotate Priorities 


Output AOi 6 (0CW2) to PICUL 


Mode A with 




End Of Interrupt 




Rotate Priorities 


Output Cni6 (0CW2) to PICUL. n is the new lowest 


Mode B without 


priority. 


End Of Interrupt 




Rotate Priorities 


Output Eni6 (0CW2) to PICUL n is the new lowest 


Mode B with 


priority. 


End Of Interrupt 




Output an interrupt 


Output mask byte to PICUL any time after 


mask 


initiation sequence. 


Read interrupt 


Input PICUH. 


mask 




Enter special 


Output 0CW3 to PICUL with 68i6 in lower 7 bits. 


mask mode 




Exit special 


Output 0CW3 to PICUL with 48i6 in lower 7 bits, 


mask mode 




Specify Polled 


Output 0CW3 to PICUL with OCie in lower 7 bits. 


Mode 




Pollany PICU _ 


Output 0CW3 to PICUL with Oil in bits 4, 3. 2, 




then immediately read from PICUL 


Read IR Status 


Output 0CW3 to PICUL with OA-\q in lower 7 bits. 




Then read from PICUL 


Read IS Status 


Output 0CW3 to PICUL with 0Bi6 in lower 7 bits. 




Then read from PICUL. 


Reset an IS status 


Output 6Ni6 (0CW2) to PICUL if End Of Interrupt. 


bit 


N is the IS status bit to be reset. 


PICUL identifies the PICU lower address (AO = 0). | 


PICUH identifies the 


=ICU higher address (A0 = 1). | 



Here is an example of the end of an interrupt service routine: 
PICUL20H 



MVI 
RET 



;SIMPLE END OF INTERRUPT 
;RETURN TO INTERRUPTED SEQUENCE 



The simplest "End-Of-lnterrupt" (EOl) is sent as 0CW3. This command will reset the highest set bit in the IS register. 
Notice that we thus assume that this interrupt occurred in Fully Nested Priority Mode, where the highest bit corres- 
ponds to the highest priority level. 

In other priority schemes, however, the interrupt level being serviced may not correspond to the highest set bit of the IS 
register. Suppose the interrupt handling scheme is Rotating Priority Mode B with level 2 the lowest priority and a level 
request being serviced: 



LOWEST 



HIGHEST- 



OEEIEIIE 

L__: 



• Interrupt priorities 

• Interrupt levels 

- In Service 



4-66 



A request at level 4 (*) will interrupt the level routine. The IS register would look like this: 

7 6 5 4 3 2 10 



|o|o|oh|o|o|oMI 



"Bit No. 
■ IS Register 



O 

00 

u 
O 

< 
a 
< 



A simple EOl in the level 4 service routine will now reset bit — which is wrong. The following instruction sequence 
will reset the correct IS bit and return: 



MVI 
RET 



PICUL,64H 



;END LEVEL 4 INTERRUPT 

;RETURN TO INTERRUPTED SEQUENCE 



Since we are rotating priorities, the following would be preferable: 



MVI 



RET 



PICUL.E4 



END LEVEL 4 INTERRUPT AND MAKE 

LEVEL 4 LOWEST PRIORITY 

RETURN TO INTERRUPTED SEQUENCE 



The priorities and IS register now look like this: 

LOWEST HIGHEST- 



c 



ia- 



7 6 5 4 3 2 10 



■ Interrupt Priorities 
' Interrupt Levels 

' Bit No. 



|0|0|0|0 0|0{0|l f -< IS Register 

Either of the suggested EOl instructions would allow the level routine to resume. 



THE TMS 5501 MULTIFUNCTION 
INPUT/OUTPUT CONTROLLER 

This is a multifunction peripheral logic device built by Texas Instruments only. It is designed to work with 8080 
or 8080A CPUs. The TMS 5501 does not use the 8228 System Controller; it decodes the Data Bus during the 
SYNC pulse. 

The TMS 5501 provides many of the functions provided by the 8255 PPI, 8251 USART, 8253 Programmable 
Timer/Counter and 8259 Priority Interrupt Control Unit. In each case, the TMS 5501 has simpler logic, with 
fewer options; but for a very large number of applications, TMS 5501 features will be more than adequate. 

Here are the TMS 5501 features provided: 

1) Two external interrupt request lines. 

2) An 8-bit, parallel input port. 

3) An 8-bit, parallel output port. 

4) A single, asynchronous serial I/O channel without handshaking. 

5) Five programmable timers, each of which times out with an interrupt request after an interval that may 
range from 64 microseconds to 16.32 milliseconds. 

Figure 4-38 illustrates those logic functions in our standard microcomputer system illustration which have been 
implemented by the TMS 5501. 

The TMS 5501 is fabricated using N-channel silicon gate technology and is packaged as a 40-pin DIP. 

TMS 5501 DEVICE PINS AND SIGNALS 

Figure 4-39 illustrates TMS 5501 device pins and signals. We will begin by summarizing these signals. 

There are three data busses. DO - D7 are the bidirectional Data Bus pjns via which data is transferred between the 
TMS 5501 and the CPU. X10 - X17 are the pins via which external logic inputs 8-bit parallel data to the TMS 5501. 
XOO - X07 are the eight pins via which the TMS 5501 outputs 8-bit parallel data to external logic. Notice i;hat XO lines 
are negative-true whereas XI lines are positive-true. Optionally XI 7 may be used for low priority external interrupt re- 
quests. 



4-67 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Interrupt Priority 
Arbitration 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Bus Interface 
Logic 



Accumulator 
Register<s) 



Data Counter<s) 



Stack Pointer 



Program Counter 



Direct Memory 

Access Control 

Logic 



System Bus 



I/O Communication 
Serial to Parallel 
, Iriterface Logic 



Programmable 
Timers 



ROM Addressing 

and 

Interface Logic 



1/0 Ports 
Interface Logic 



Read Only 
Memory 



I/O Ports 



RAM Addressing 

and 

Interface Logic 



Read/Write 
Mepiory 



Figure 4-38. Logic of the TMS 5501 Multifunction Input/Output Controller 



4-68 



o 

< 

Q 

< 

@ 



vcc 
Vdd 

RCV 
D7 
D6 
D5 
D4 
D3 
D2 
D1 
DO 
AO 
A1 
A2 
A3 
CE 
SYNC 

.■^ PIN NAME 

D0-D7 

XIO - XI7 

XOO-3<07 

XMT 

RCV 

SENS 

INT 

CE 

AO- A3 

SYNC 

<lJl, 02 

^BB'^CC'^DD-^SS 



TMS 
5501 



- XMT 

- X10 
_ XII 

- XI2 
_ XI3 
_ XI4 
_ XI5 
_ XI6 
_ XI7 

- X07 
» X06 

- )<05 

- 5<04 

- X03 

- ><02 

- xoi 

- XOO 

- INT 

- SENS 

- (t)2 



DESCRIPTION TYPE 

Data Bus to CPU Bidirectional 

Data Bus from external logic Input 

Data Bus to external logic Output 

Transmit serial data line Output 

Receive serial data line Input 

External interrupt sense Input 

Interrupt request Output 

Chip Select Input 

Address Select Input 

Synchronizing signal (SYNC) from 8080A Ihput 

Clock inputs, same as to 8080A Input 
Power Supply (-5V, + 5V, + 12V) arid Ground 



TMS 5501 
OUTPUT 
SIGNAL 
INVERSION 



Figure 4-39. TMS 5501 Multifunction Input/Output Controller Signals 
and Pin Assignments 

Do not miss the significance of XO negative logic; whatever you write to the TMS 5501 for 
parallel output will be complemented. XO signals are the inverse of the oiitput buffer con- 
tents. 

Serial I/O data uses the XMT and RCV p ins. XMT is used to transnnit serial data, whereas RCV is 
used to receive serial data. Note that RCV is a negative-true signal, whereas XMT is a positive-true 
signal. • . . 

External logic may request interrupt service either via the SENS input or via the XI7 input. A low-to-high transi- 
tion on either signal constitutes an interrupt request. SENS is.always part of external interrupt request logic; XI7 must 
be programmed for this purpose — in which case the eight XI pins cannot be used to injDUt 8-bit parallel data. 

Logic internal to the TMS 5501 may also generate interrupt requests. Whatever the source of the interrupt re- 
quest, it is passed on to the CPU via the INT interrupt request signal. 

The TMS 5501 is accessed either as 16 I/O ports or 16 rnemory locations. Addressing logic consists of a chip 
select (CE) and four address select inputs (AO, A1, A2 arid A3). 

The TMS 5501 receives the SYNC timing pulse, and this requires special mention. While SYNC is high, the TMS 
5501 decodes status off the Data Bus, therefore the 8228 System Controller is not needed. 

Additional signals required by the TMS 5501 are the two 8080A clock signals Ol and $2. Slight clock signal 
variations will confuse serial I/O logic which computes baud rates internally. 



4-69 



A feature of the TMS 5501 which you must note carefully is that it cannot handle Wait TMS 5501 
states. Any T\/\/ clock periods in a machine cycle will cause the TMS 5501 to malfuhctioh. WAIT STATE 

There is a further unlikely ramification of the TMS 5501 inability to handle Wait states. If you are 
accessing the TMS 5501 as 16 memory locations, then you cannot have a Halt instruction's object code in the 
memory location immediately preceding the 16 TMS 5501 addresses. If you do, the Halt instruction will execute, 
following which the Address Bus will contain the address of the next sequential memory location — which now is a 
TMS 5501 address. Thus, the TMS 5501 becomes selected. But the TMS 5501 logic cannot cope with a sequence of 
■undefined clock periods, which is exactly what will happen following a Halt instruction's execution. The net effect is 
that following a Halt, the TMS 5501 receiver buffer loaded flag will be inadvertently cleared. 

Always make sure that the memory address directly preceding the 16 addresses assigned to a TMS 5501 remains 
unused. 

TMS 5501 DEVICE ACCESS , 

Some of the 16 I/O port or memory addresses via which the TMS 5501 device is accessed are equivalent to 
memory locations, but others are command identifiers. Table 4-7 defines the manner in which addresses are in- 
terpreted. 

You will find the TMS 5501 far easier to use if you address it as 16 memory locations, because that will give you access 
to memory referencing instructions. 

When creating TMS 5501 select logic, any of the select schemes described earlier in this chapter will do — with one 
addition. Include READY as part of the select logic; if READY is low, a Wait state will follow, and that will cause the 
TMS 5501 to malfunction. By making READY high a necessary component of device select logic, you can avoid this 
problem. 

In the following discussion of individual TMS 5501 capabilities, we will use programming examples to show the effec- 
tiveness of including the TMS 5501 device within your memory rather than I/O space. 



Table 4-7. TMS 5501 Address Interpretations 



A3 


A2 


A1 


AO 


FUNCTION 





6 








Read assembled serial input data byte out of Receiver Buffer 













Read parallel data input via XIO - XI7 













Read RST instruction code, as a data byte, when jiolling interrupt requests 












Read Status register contents to the CPU 





1 








Write command code to the TMS 5501 





1 







Load serial I/O Control register, specifying baud rate and stop bits 





1 







Write data byte to serial transmit logic 





1 






Write data byte to parallel output port 













Write out interrupt mask byte to selectively enable and disable interrupts 












Write initial count to Interval Timer 1 












Write initial count to Interval Timer 2 











Write initial count to Interval Timer 3 




1 








Write initial count to Interval Timer 4 




1 
1 
1 








Write initial count to Interval Timer 5 
No Operation 
No Operation 



TMS 5501 addressable locations 3, 4 and 5 are used for status and controls which generally apply to serial I/O 
and interrupt processing. We will define how these ports are used now, in advance of our discussion of TMS 5501 
serial I/O and interrupt processing capabilities. 



4-70 



Locations 3 and 5 apply to serial I/O logic. Location 3 is a Status register whose bits are interpreted as follows: 



7 6 



o 
ffi 
u> 
o 

< 

Q 

< 

® 



n 



ii ii ii -i nil). 



5 4 3 2 10 

rrn 



Bit No. 

Serial I/O Status register (Address 3) 

• 1 Framing error detected 
1 Overrun error detected 

• 1 No serial data being received 

• 1 Receive Buffer ready to be read 

■ 1 Transmit Buffer empty 
•1 Interrupt pending 

■ 1 Serial data character being received 
■1 Start bit as been detected 



Bits and 1 are standard framing and overrun error indicators. 

If a framing error is detected, Status register bit will be set to 1 and will remain 1 until assembly of the next complete 
serial data character has been completed. 

If Receiver Buffer contents are not read while the next serial character is being input and assembled, an overrun error 
will be reported in bit 1 of the Status register. This error indicator will be cleared as soon as the Status register contents 
are read, or when a reset command is output. Remember, you have the time it takes to receive and assemble one 
character in which to read the previous character out of the Receiver Buffer. This is because receive logic includes a 
double buffer. A character is assembled in a Receiver register; when completely assembled, it is shifted to a Receiver 
Buffer and the next character is assembled in the Receiver register: 



RCV 


r 


Byte N ^ 


Receiver 




Byte N being 


Register 




assembled 


Contents 






Receiver 




Assembled Byte N-1, 


Buffer 




waiting to be read 


Contents 







Byte N + 1 



Byte N + 1 being 
assembled 

Assembled Byte N, 
waiting to be read 



Status bits 2, 3, 6 and 7 monitor the condition of the serial data input signaL During a break, that is, when no valid 
serial data is being input, status bit 2 will be high. As soon as a start bit has been detected, status bit 2 will be reset low 
and status bit 7 will be set high. When the first valid data bit is detected, status bit 6 is also set high. When the 
received character has been assembled in the Receiver Buffer, and may be read by the CPU, status bits 7 and 6 are 
reset and status bit 3 is set. This may be illustrated as follows: 



•End of first data character 




M Marking 

A Start bit 

D Data bits 

P Parity bit 

Stop bits 



4-71 



Status bit 4 applies to serial transmit logic. As soon as the Transmit Buffer is ready to receive another byte of data, 
status bit 4 will be set high. It will remain high until new data has been loaded into the Transmit Buffer. 

Transmit logic, like receive logic, is double-buffered. A byte of data is held in a Transmitter register while being output 
serially; meanwhile, the next data byte hnay be loaded into a Transmitter Buffer. Transmitter Buffer contents are auto- 
matically shifted to the Transmitter register when serial output of a data byte is complete. This may be illustrated as 
follows: 



XMT 



Byte N 



Byte N + 1 



Transmitter 

Register 

Contents 

Transmitter 

Buffer 

Contents 



Byte N being 
output serially 

Write Byte N + 1 into 

Transmitter Buffer 

during this time 



Byte N + 1 being 
output serially 

Write Byte N + 2 into 

Transmitter Buffer 

during this time 



Status bit 4 is high from the instant Transmitter Buffer contents are shifted into the Transmitter register, until a new 
data byte is written into the Transmitter buffer. 

Status bit 5 is set whenever the TMS 5501 has an unacknowledged interrupt request. While this status bit is very 
important in serial I/O operations, it also may have application elsewhere; this bit therefore may be looked upon as an 
exception within the Status register, in that it is the only status flag that does not apply strictly to serial 1/0 operations. 

TMS 5501 addressable location 5 is also dedicated to serial I/O. Into this location you must load a control byte 
which selects baud rate, and the number of stop bits. Register contents will be interpreted as follows: 




ji ,1 ]iii II iTJ 



Bit No. 

Baud Rate Register (Address 5) 



= 1 10 Baud 
= 150 Baud 
= 300 Baud 
= 1200 Baud 
= 2400 Baud 
= 4800 Baud 
= 9600 Baud 
= One stop bit 
= Two stop bits 



Baud rates based 
on 2 mHz clock 



If more than one of bits through 6 are high, then the highest indicated baud rate will be selected. If no baud rate bit is 
high, then all serial transmit and receive logic will be inhibited. 



4-72 



TMS 5501 addressable location 4 is a general command register. Its contents will be interpreted as follows: 



o 
ffi 
w 
o 

< 
o 
< 



7 6 



5 4 3 2 1 



il -i -i n i7\ 



0- 

n- 



'Bit No. 



~< Control Register (Address 4) 



■ 1 = Device reset 

" 1 = Output Mark on idle 

= Output space on idle 
" 1 = Select XI7 as lowest priority interrupt 

= Select interval timer 5 as lowest priority interrupt 
" 1 = Enable TMS 5501 interrupt acknowledge 

= Disable TMS 5501 interrupt acknowledge 
' = Normal baud rate and interval timing 

1 =TMS 5501 <I>1 intemal clocking runs eight times normal rate, which 

1) multiplies all baud rates in the baud rate register by 8, alk>wing 
high speed data transfers at rates up to 76.8 kilo baud 

2) decrements the interval timers every 8 microseconds 

■ = Normal operation 

1 - INT outputs a clock whose frequency depends on bit 4. If bit 4 is reset 
(0), the output frequency is the system ck>ck frequency divided by 128. 
If bit 4 is set (1), the output frequency is the system clock frequency 
divided by 16. 
' Can have any value 



If your system does not require interrupts from the TMS 5501 , you can set bit 5 high to derive a TTL compatible 
clock from the INT output. 

If the TMS 5501 device is reset by outputting 1 to bit 0, then the following events will oc- TMS 5501 
cur: RESET 



1 ) Serial receive logic enters the Hunt mode. Status bits 2, 3, 6 and 7 are all reset; however, reset 
will not clear the Receive Buffer contents. 

2) Serial transnnit logic will output a high marking signal. Status bit 4 will be set high indicating that transmit logic is 
ready to receive another data byte. 

3) The interrupt mask register is cleared with the exception of the Transmit Buffer interrupt, which is enabled. (Inter- 
rupt levels and interrupt masking are described shortly.) 

4) All interval timers are halted. 

The Reset has no effect on any of the following: 

- Parallel input and output port contents 

- Interrupt acknowledge enable 

- Interrupt Mask register contents 

- Baud rate register contents 

- Serial Transmit or Receive Buffer contents 

Control command bit 1 determines whether serial transmit logic will mark or space when not transmitting data. 

A 1 in bit 1 will cause serial transmit logic to mark (output high) while a in bit 1 will cause transmit logic to space 
(output low). 

If Reset conflicts with the break specification, then Reset will override and transmit logic will mark, irrespective of the 
break bit specification. 

The TMS 5501 can receive an interrupt request from one of nine different sources. Using the eight Restart instructions, 
each interrupt request is assigned one of eight priorities. For this to be possible, two interrupt sources share the lowest 
priority interrupt level (RST 7); these two sources are an external request arriving via XI7 and the Interval Timer 5 time 
out interrupt request. You use bit 2 of the control command to select which requesting source will be active at 
any time as the lowest priority interrupt. 

Bit 3 of the control command is a master enable/disable for TMS 5501 interrupt logic. If this bit is output as 0, 
then TMS 5501 interrupt acknowledge logic is disabled — and that effectively disables the entire interrupt processing 
system. Observe that with interrupt acknowledge logic disabled you can still use polling techniques in lieu of interrupt 
processing. 



4-73 



Table 4-8. TMS 5501 Interrupt Logic and Priorities 



Interrupt 

and Mask 

Bit 


Data Bus 
Status 


RST 
Instruction' 


interrupting Source 


05 


04 


03 


(highest) 

1 

2 

3 

4 

5 

6 
7 (lowest) 







1 
1 

1 
1 





1 
1 



1 
1 



1 


1 


1 



1 


RSTO 
RST 1 
RST 2 
RST 3 
RST 4 
RST 5 
RST 6 
RST 7 


Interval Timer 1 

Interval Timer 2 

Extemal SENS Interrupt request 

Interval Tinrier 3 

Serial I/O Receiver Buffer full 

Serial I/O Transmitter Buffer full 

Interval Timer 4 

Interval Timer 5, or external XI7 

interrupt request, whichever has 

been selected by commanqi code 



TMS 5501 INTERRUPT HANDLING 

The TMS 5501 responds to nine different interrupt requests, with priorities as defined in Table 4-8. 

When an interrupt is acl<nowledged, INT is output high by the TMS 5501. If the TMS 5501 INT output is connected 
to the 8080A INT input, then the 8080A will acknowledge the interrupt by outputting D1 high at SYNC high. The TMS 
5501 responds to this acknowledge by placing an RST instruction's object code on the Data Bus, as required by stan- 
dard 8080A timing. This is an utterly standard 8080A interrupt request/acknowledge sequence. 

Interrupts may be selectively disabled by writing a mask to TMS 5501 Register 8; see Table 4-7. A bit will disable 
an interrupt; mask bits are related to priorities as follows: 



7 6 5 4 3 2 10 -* 

1 1 1 1 1 1 1 1 K— 


;. M 1 


. 1' M ;. n 1 



























Bit No. 

TMS 5501 Register 8 

Interval Timer 1 

Interval Timer 2 

External SENS interrupt request 

Interval Timer 3 

Serial I/O Receiver Buffer full 

Serial I/O Transmitter Buffer full 

Interval Timer 4 

Interval Timer 5 or external XI7 interrupt request 



Note that TMS 5501 interrupt priorities apply to the request/acknowledge sequence, only — which is the standard 
passive interrupt priority arbitration sequence used in most microcomputer applications. Once an interrupt is 
acknowledged and is being serviced by an interrupt service routine, it is up to the programmer to disable all interrupts, 
or selected interrupts, if the interrupt service routine is not itself to get interrupted. If, for example, an interrupt were to 
be acknowledged at priority 3 (Interval Timer 3), in the normal course of events the 8080A CPU will disable all inter- 
rupts upon acknowledging any interrupt. Therefore the Interval Timer 3 interrupt service routine will deny any other in- 
terrupt request, whatever its priority, until the Interval Timer 3 service routine completes execution. If the Interval Timer 
3 interrupt service routine were to immediately enable all interrupts, then any other, interrupt request would be 
acknowledged, irrespective of priority. 

If you want to ensure that only higher priority requests interrupt the Timer 3 service routine, then the Timer 3 service 
routine must begin by outputting a mask to disable all lower level interrupts at the TMS 5501 ; then it must enable ail 
interrupts at the CPU. Here is the necessary instruction sequence: 

MVI TMS8,07H :OUTPUT MASK TO REGISTER 8 OF TMS 5501 

El :ENABLE INTERRUPTS 

The mask output in this case has the value 07, since mask bits 0, 1 and 2 only must be set to 1, enabling the highest 
three interrupt priority levels. 



4-74 



TMS 5501 

NONSTANDARD 

FEATURES 



Let us now look at the nonstandard features associated with TMS 5501 interrupt 
handling logic. First of all, so long as there is an unacknowledged interrupt request. Status 
register bit 5 is set to 1 ; next the RST instruction object code for the highest level interrupt 
request is stored in TMS 5501 Register 2. This allows you to bypass normal interrupt pro- 
cessing logic and poll the TMS 5501 instead. 

Q In order to bypass interrupt logic, simply disconnect the TMS 5501 INT output from the 8080A INT input. You can still 

H identify interrupt requests occurring within the TMS 5501 by reading the TMS 5501 Status register. If bit 5 of the 

oc Status register is 1 , then one or more interrupt requests are active within the TMS 5501 . In order to determine which is 

Q. the highest level active interrupt request, read the contents of TMS 5501 memory location 2. The RST instruction ob- 

o ject code corresponding to the highest priority interrupt request will have been assembled in this location. Bits 3, 4 and 

z 5 of the RST instruction object code identify the priority level. Thus you can determine which of the eight priority levels 

""- was the highest active interrupt request. Here is a typical polling sequence: 

H ; ASSUME THAT THE TMS 5501 ADDRESS SPACE CONSISTS OF 16 MEMORY 

§ ;LOCATIONS FROM 8000 THROUGH 800F. TMS5 IS THE SYMBOL ASSIGNED 

o ;T0 THE BASE ADDRESS 



TMS5 EQU 8000H 



m iTEST STATUS REGISTER FOR INTERRUPT PENDING 

o LDA , TMS5+3 ;LOAD STATUS TO ACCUMULATOR 

5 ANI 20H . ;ISOLATE BIT 5 

g JNZ TMS5+2 ;IF NOT ZERO, AN INTERRUPT HAS BEEN 

< ;REQUESTED 

@ - 



It is worth spending a minute looking at the three-instruction sequence illustrated above. The TMS 5501 Status register 
contents are loaded into the Accumulator by the LDA instruction. The next instruction isolates bit 5. If bit 5 is 1, then 
an interrupt has been requested, and the next instruction, a JNZ, branches program execution to a memory location 
within the TMS 5501 itself. Will that work? Indeed, it will. The label TMS5+2 addresses TMS 5501 Register 2, which 
contains an RST instruction's object code; this is the object code which would have been output in response to a nor- 
mal interrupt acknowledge. What the JNZ instruction does is cause this RST instruction's object code to be executed 
next; and that is precisely the logic sequence which a normal interrupt response would have implemented. 

Notice that the very simple method we have illustrated for polling on status only works if the TMS 5501 can be ad- 
dressed as memory locations rather than I/O ports. 

TMS 5501 PARALLEL I/O OPERATIONS 

It is very easy to handle simple parallel I/O, without handshaking, using the TMS 5501 . This is equivalent to 8255 
Mode operation. TMS 5501 address 1 accesses the parallel 8-bit input port, while address 7 accesses a parallel 8-bit 
output port (see Table 4-7). Assuming that the TMS 5501 is addressed as memory, input and output operations are 
handled using any memory reference instructions. 

A very limited amount of parallel I/O handshaking is available. The SENS interrupt input signal can be used by ex- 
ternal logic either to indicate that it has read output data, or to indicate that it has transmitted input data. However, the 
TMS 5501 device itself has no contro l sign als which can be used to prompt external logic; that is to say, the TMS 5501 
has no signal equivalent to the 8255 OBF control. When comparing the parallel I/O capabilities of the TMS 5501 with 
the 8255, therefore, we conclude that 8255 Mode operations can be duplicated without problems, but neither Mode 
1 nor Mode 2 parallel I/O operations with handshaking can be duplicated. Only a primitive level of parallel I/O with 
handshaking exists within the TMS 5501 and even this exists at the expense of external interrupt logic. 

TMS 5501 SERIAL I/O OPERATION 

A significant asynchronous, serial I/O capability is provided by the TMS 5501. Synchronous serial I/O is not sup- 
ported. 

There are very significant differences between the implementation of asynchronous serial I/O by the TMS 
5501, as compared to the 8251 USART. 

The TMS 5501 has separate serial transmit and receive pins (XMT and RCV), but it has no accompanying handshaking 
control signals; instead 5th and 6th priority interrupts identify Receiver Buffer full and Transmit Buffer full, respec- 
tively. Bits 2, 3, 6 and 7 of the Status register (addressable location 3) identify the condition of a serial receive data 
stream. 

4-75 



When using the TMS 5501 , you have to continuously read in the contents of the Status register and test the condition 
of appropriate status bits in order to implement standard serial receive logic; however, in the end you can implement 
the same serial receive logic as is provided automatically by the 8251 USART. Here is the relationship between the 
TMS 5501 and the 8251 USART controls: 

8251 USART TMS 5501 EQUIVALENT 

TxRDY Status register bit 4 

TxE None 

TxC Baud Rate register 

RxRDY Status register bit 3 

RxC Baud Rate register 

SYNDET None 

Probably the most significant difference between TMS 5501 and 8251 USART control is the fact that TMS 5501 baud 
rate is programmed by outputting an appropriate Control code, while it is clocked by rate signals input to the 8251 
USART. The TMS 5501 advantage is that the TMS 5501 does not need external baud rate clock generation logic; 
however there must be a very precise synchronization between the TMS 5501 and whatever external logic it is com- 
municating with. Minor timing differences are no problem when using an 8251 USART since a clock signal can accom- 
pany the serial data stream. Minor timing differences can be intolerable when using the TMS 5501 ; a small difference 
between TMS 5501 baud rate and external clock signals can generate very significant errors. 

TMS 5501 INTERVAL TIMERS 

The TMS 5501 has five programmable Interval Timers. Each timer can be loaded with an initial count ranging 
from 01 (lowest) through FFi g (highest). Each Timer will decrement one count every 64 microseconds. As soon 
as a programmable timer counts out to zero, it requests an interrupt. In our discussion of TMS 5501 interrupt logic, 
we have defined the priority levels assigned to the various Interval Timers. Notice that Interval Timer priorities have 
been spread across the range of priority levels. By using Interval Timer 1 or 2, you can be sure of precise time intervals, 
since an interrupt request will be acknowledged with little or no delay. Timers 4 and 5, being the lowest priority, can be 
used to generate less precise time intervals. It is conceivable that interrupt requests originating at these two timers 
might have to wait a significant amount of time before being serviced — if there is any degree of interrupt traffic within 
the microcomputer system. 

Loading a value into an Interval Timer causes an immediate interrupt request. 

When a nonzero value is loaded into an Interval Timer, it starts to count down immediately. If a new value is loaded into 
an Interval Timer while it is halfway through counting out, then the new value will be accepted; it will override the pre- 
vious value and subsequently will be decremented. Therefore the Interval Timers are retriggerable. 

Once an Interval Timer counts out, it halts. 



4-76 



DATA SHEETS 

This section contains specific electrical and tinning data for the following devices: 

.8080ACPU 
Q • 8224 Clock Device 

^ . 8228 System Controller 

< .8259 PIC 

o . TMS 5501 I/O Controller 

DC 

o 
u 

z 

(/) 

lU 
< 

8 

(0 

< 

o3 

lU 

Z 
cc 
o 

CD 
W 
O 

< 

Q 
< 



@ 



4-D1 



8080A/8080A-1/8080A-2 
ABSOLUTE MAXIMUM RATINGS* 

Temperature Under Bias . CC to +70° C 

Storage Temperature -65°C to +150°C 

All Input or Output Voltages 

With Respect to Vqb -0.3V to +20V 

Vcc. Vdd and Vss With Respect to Vbb -0.3V to +20V 
Power Dissipation 1.5W 



'COMMENT: Stressesabove those fisted under "Absolute Maxi- 
mum Ratings" may cause pennanent damage to the device. 
This is a stress rating only and functional operation of the de- 
vice at these or any other conditions above those indicated in 
the operational sections of this specification is not implied. Ex- 
posure to absolute maximum rating conditions for extended 
periods may affect device reliability. 



D.C. CHARACTERISTICS 

Ta = 0°C to 70°C, Vdd = +12V ± 5%, Vcc = +5V ± 5%, Vbb 



-5V ± 5%, Vss = OV, Unless Othenwise Noted. 



Symbol 


Parameter 


Min. 


Typ. 


Max. 


Unit 


Test Condition 


V,LC 


Clock Input Low Voltage 


Vss-1 




Vss+0.8 


V 




VlHC 


Clock Input High Voltage 


9.0 




Vdd+1 


V 




V|L 


Input Low Voltage 


Vss-1 




Vss+0.8 


V 




V,H 


Input High Voltage 


3.3 




Vcc+1 


V 




Vol 


Output Low Voltage 






0.45 


V 


Iql = 1.9mA on all outputs, 


VoH 


Output High Voltage 


3.7 






V 


Ioh=-150mA. 


Idd(av) 


Avg. Power Supply Current (VddI 




40 


70 


mA 


Operation 
TcY = .48 fisec 


'CC(AV) 


Avg. Power Supply Current (Vcc) 




60 


80 


mA 


'bb (AV) 


Avg. Power Supply Current (Vbb) 




.01 


1 


mA 


l|L 


Input Leakage 






±10 


n^ 


Vss<V,N<Vcc 


ICL 


Clock Leakage 






±10 


HA 


Vss ^ VcLOCK < Vdd 


Idl121 


Data Bus Leakage in Input Mode 






-100 
-2.0 


HA 
mA 


Vss<V,N<Vss+0.8V 
Vss+0.8V<V,N<Vcc 


Ifl 


Address and Data Bus Leakage 
During HOLD 






+ 10 
-100 


HA 


Vaddr/data = Vcc 
Vaddr/data = Vss + 0.45V 



CAPACITANCE 

T. = 25°C Vcc = Vdd = Vss = OV. Vbb = -5V 



Symbol 


Parameter 


Typ. 


Max. 


Unit 


Test Condition 


C0 


Clock Capacitance 


17 


25 


Pf 


fc = 1 MHz 


C|N 


Input Capacitance 


6 


10 


Pf 


Unmeasured Pins 


COUT 


Output Capacitance 


10 


20 


pf 


Returned to Vss 



NOTES: 

1 . The RESET signal must be active for a minimum of 3 clocl< cycles. 

2. When DBIN is high and V|rg > V|h an internal active pull up will 
be switched onto the Data Bus. 

3. AI supply /AT A = -0.45%/° C. 




+25 +50 

AMBIENT TEMPERATURE ("O 



Figure 2. Typical Suppiy Current vs. 
Temperature, Normalizedt'^l 




Figure 3. Data Bus Characteristic 
During DBiN 
Data sheets on pages 4-D2 through 4-D12 are reprinted by permission of Intel Corporation, Copyright 1978. 



4-D2 



8b80A/8080A-1 /8080A-2 
A.C. CHARACTERISTICS (8080A) 

Ta = 0°C to 70°C, VoD = +12V ± 5%, Vqc = +5V ± 5%, Vbb = -5V ± 5%, Vss = OV, Unless Otherwise Noted 



Symbol 



Param«t«r 



•1 
MIn. 



•1 

Max. 



•2 

Min. 



•2 
Max. 



Taat Condition 



O 
m 
(0 
O 

< 

Q 

< 

@ 



,CYi31 



«r. I| 



Clock Rise and Fall Time 



50 



»01 



ay Pulse Width 



60 



1 02 



02 Pulse Width 



<D1 



Delay 0i to 02 



•D2 



Delay Oj '<> ^1 



<D3 



Delay 0^ to 02 Leading Edges 



«daI 



(2| 



Address Output Delay From 02 



175 



Idd'^I 



Data Output Delay From 02 



tpc'^l 

'|DfJ21 



Signal Output Delay From 02 or 02 (SYNC, WR, WAIT, HLDA) 



DBIN Delay From 02 



130 



Cl=100pF 
Cl = 50pF 



to,Iil 



Delay lor Input Bus to Enter Input Mode 



'DF 



»DF 



tDF 



'DS1 



Data Setup Time During 0f and DBIN 



WAVEFORMS 



(Note: Timing measurements are made at the following reference voltages: CLOCK "1" = 8.0V 
"0" = l.OV; INPUTS "1" = 3.3V. "0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = 0.8V.) 



A 



A. 



/ 



*15A) 



"7 "0 
SYNC 



A 



f~\ 



DZIT 



a: 



JT 



> 



J^^i 



"Z i DATA IN 
'0SI I*- 



A 



r 



h-'DF-H 



'ID:. 






TDH 



A 



j^~'i 



:c 






'DC ".-4^ 



/ 






r^-^ 



•a- 



4-D3 



8080A/8080A-1 /8080A-2 
A.C. CHARACTERISTICS (8080A) 

Ta = 0°C to 70°C, Vdd = +12V ± 5%, Vcc = +5V ± 5%, Vbb = -5V ± 5%, Vss = OV, Unless Otherwise Noted 



Symbol 


Paramctar 


MIn. 


Max. 


•1 
Min. 


•1 
Max. 


•2 

MIn. 


•2 
Max. 


Unit 


Test Condition 


tDS2 


Data Setup Time to 02 During DBIN 


150 




120 




130 




nsec 




tOH'^l 


Data Holt time From 02 During DBIN 


ID 




Ml 




ni . 




nsec 




t,El2I 


INTE Output Delay From 02 




200 




200 




200 


nsec 


Cl = 50pF 


»RS 


READY Setup Time During 02 


120 




90 




90 




nsec 




«HS 


HOLD Setup Time to 02 


140 




120 




120 




nsec 




•is 


INT Setup Time During 02 


120 




100 




100 




nsec 




IH 


Hold Time From 02 (READY. INT, HOLD) 

















nsec 




tpD 


Delay to Float During Hold (Address and Data Bus) 




120 




120 




120 


nsec 




tAwl21 


Address Stable Prior to WR 


(5) 




[51 




(51 




nsec 






towf^l 


Output Data Stable Prior to WR 


[6] 




16) 




[61 




nsec 




twDl2) 


Output Data Stable From WR 


[7] 




|71 




[71 




nsec 




tWA'21 


Address Stable From WR 


(71 




[71 




(71 




nsec 


Cl= 100 pF: Address, Data 
"Cl = 50pF.WR,HLDA,DBIN 


tHFl21 


HLDA to Float Delay 


18] 




[81 




[81 




nsec 


tWFl21 


WR to Float Delay 


[91 




[91 




(91 




nsec 




tAHl2I 


Address Hold Time After DBIN During HLDA 


-20 




-20 




-20 




nsec 





-I\ 



f\ 



;^~A 



f 



■i ^. 



:c: 



•wD 



f f _^*— VlF ► 



^ 



NOTES: (Parenthesis gives -1, -2 specifications, respectively) 

^. Data input should be enabled with DBIN status. No bus conflict can then occur and data hold time is assured. 

tDH ~ 50 ns or top, whichever is less. 
2. Load Circuit. 



8080A 
OUTPUT J_ 



F^ 




3. Icy = 'D3 + 'r+2 + '|2 + 'f|2 + '02 + 'r+1 > ^80 ns (- 1:320 ns, -2:380 ns). 
TYPICAL A OUTPUT DELAY VS. A CAPACITANCE 







/ 








/ 








^SPEC 




^^ 









.i CAPACITANCE Ipf) 
""ACTUAL " ''spec' 

4. The following are relevant when interfacing the 8080A to devices having V|h ■= 3.3V: 
al Maximum output rise time frond .8V to 3.3V "= 100ns l9> Cl ' SPEC. 

b) Output delay when measured to 3.0V - SPEC +60ns @i Cl • SPEC. 

c) If Cl * SPEC, add .Gns/pF if Cl> CsPEC. subtract .3ns/pF (from modified delay) if Cl < CspEC- 

5. fAW = 2tcY - lD3 - <rf2 - 140 ns (- 1:110 ns, -2:130 ns). 

6. tow = <CY - 'D3 - 'r|2 - 170 ns (- 1:150 ns, - 2:170 nsj. 

7. If not HLDA, twD ° 'WA = 'D3 * 'r02 +10ns. If HLDA, twb ' 'WA " 'WF- 
8- tHF = tD3 + 'r02-5Ons. 

9. tyvF =<D3 +tr02-1O"« 

10. Data in must be stable for this period during DBIN •T3. Both tQsi a"d 'DS2 """^t be satisfied. 

11. Ready signal must be stable for this period during T2 or Ty^. (Must be externally synchronized.) 

12. Hold signal must be stable for this period during T2 or Ty^ when entering hold mode, and during T3, T4, T5 
and T^JH who" in hold mode. (External synchronization is not required.) 

13.' Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be 

recognized on the following instruction. (External synchronization is not required.) 
14. This timing diagram shows timing relationships only; it does not represent any specific machine cycle. 



4-D4 



8224 



ABSOLUTE MAXIMUM RATINGS' 



Temperature Under Bias C to 70 C 

Storage Temperature — 65°C to 150°C 

Supply Voltage, Vqc -0.5V to +7V 

Supply Voltage, Vqd • • ■ -0.5V to +13.5V 

Input Voltage -1.5V to +7V 

Output Current lOOrinA 



'COMMENT: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



O 

< 
< 
© 



D.C. CHARACTERISTICS 

Ta = O'C to 70''C; Vcc = +5.0V ±5%; Vdd = +12V ±5%. 





Parameter 


Limits 


Units 




Symbol 


Min. 


Typ. 


Max. 


Test Conditions 


If 


Input Current Loading 






-.25 


mA 


Vp = .45V 


"r 


Input Leakage Current 






10 


MA 


Vr = 5.25V 


Vc 


Input Forward Clamp Voltage 






1.0 


V 


Ic = -5mA 


V|L 


Input "Low" Voltage 






.8 


V 


Vcc = 5.0V 


V|H 


Input "High" Voltage 


2.6 
2.0 






V 


Reset Input 
Another Inputs 


V,H-V,L 


RESIN Input Hysteresis 


.25 






V 


Vcc = 5.0V 


Vol 


Output "Low" Voltage 






.45 
.45 


V 
V 


{</>1,'A2). Ready, Reset, STSTB 

Iql =2.5mA 

All Other Outputs 

loL = 15mA 


VoH 


Output "High" Voltage 

READY, RESET 
All Other Outputs 


9.4 
3.6 
2.4 






V 
V 
V 


Iqh = -lOOpA 
loH=-100/iA 
Iqh =-1mA 


Isc'i] 


Output Short Circuit Current 
(All Low Voltage Outputs Only) 


-10 




-60 


mA 


Vo = ov 
Vcc = 5.0V 


Ice 


Po\»"'- Cupply Current 






115 


mA 




'dd 


Power Su ppl y Cu rrent 






12 


mA 





Note: 1. Caution, 0i and 02 output drivers do not have short circuit protection 

Crystal Requirements 

Tolerance: .005% at 0°C -70°C 
Resonance: Series (Fundamental)* 
Load Capacitance: 20-35pF 
Equivalent Resistance: 75-20 ohms 
Power Dissipation (Typ.) : 4mW 

'With tank circuit use 3rd overtone mode. 



4-D5 



8224 

A.C. CHARACTERISTICS 

Vcc = +5.0V ± 5%; Vdd = +12.0V ± 5%; Ta = 0°C to 70°C 





Parameter 


Limits 


Units 


Test 


Symbol 


Min. 


Typ. 


Max. 


Conditions 


t0i 


01 Pulse Width 


9 






ns 




t02 


02 Pulse Width 


9 








tDI 


01 to 02 Delay 











tD2 


02 to 01 Delay 


^^'^V-Uns 
9 






Cl = 20pF to 50pF 


tD3 


01 to 02 Delay 


2tcy 
9 




2^*=y + 20ns 
9 




tR 


01 and 02 Rise Time 






20 




tF 


01 and 02 Fall Time 






20 




tD02 


02 to 02 (TTL^ Delay 


-5 




+15 


ns 


02TTL,CL=3O 

Rl=300n 

R2=600n 






6t^V-30ns 
9 




6tcy 
9 






toss 


02 to STSTB Delay 








^-H^-15ns 
9 








STSTB, CL=15pF 
Ri = 2K 


tpw 


STSTB Pulse Width 


tDRS 


RDYIN Setup Time to 
Status Strobe 


50ns -^^"^V 
9 






R2 = 4K 


tDRH 


RDYIN Hold Time 
After STSTB 


4tcy 
9 








tDR 


RDYIN or RESIN to 
02 Delay 


^^'=y-25ns 
9 








Ready & Reset 
CL=10pF 
Ri=2K 
R2=4K 


tCLK 


CLK Period 




tcy 
9~ 








^max 


Maximum Oscillating 
Frequency 






27 


MHz 




Cin 


Input Capacitance 






8 


PF 


Vcc=+5.0V 
Vdd=+12V 
Vbias=2.5V 
f=lMHz 



|gno 



4-D6 



8224 
WAVEFORMS 



< 

Z 
cc 
o 
m 

o 

< 
a 
< 

@ 



*2ITTLI 



SYNC 
IFROM8080A) 



RDYINOR RESIN 



READY OUT 




VOLTAGE MEASUREMENT POINTS: 01,02 Logic "0" = 1.0V, Logic "1" = 8.0V. All other signals measured at 1.5V. 

EXAMPLE: 

A.C. CHARACTERISTICS (For tcv = 488.28 ns) 

Ta = 0°C to 70°C; Vdd = +5V ±5%; Vpo = +12V ±5%. 





Parameter 


Limits 


Units 




Symbol 


Min. 


Typ. 


Max. 


Test Conditions 


t«l 


(Ai Pulse Width 


89 






ns 
ns 
ns 
ns 
ns 
ns 
ns 

ns 
ns 
ns 
ns 
ns 
ns 


tcY=488.28ns 


t02 


02 Pulse Width 


236 








tDI 


Delay 0i to 02 











tD2 


Delay 02 to 0i 


95 






_ 01 & 02 Loaded to . 


tD3 


Delay 0i to 02 Leading Edges 


109 




129 


CL = 20to50pF 


tr 


Output Rise Time 






20 




tf 


Output Fall Time 






20 








296 




326 




toss 


02 to STSTB Delay 




tD02 


02 to 02 (TTL) Delay 


-5 




+15 




tpw 


Status Strobe Pulse Width 


40 






Ready & Reset Loaded 
to2mA/10pF 


tDRS 


RDYIN SetupTime to STSTB 


-167 






tDRH 


RDYIN Hold Time after STSTB 


217 






All measurements 


tDR 


READY or RESET 
to 02 Delay 


192 






referenced to 1.5V 
unless specified 
otherwise. 


fMAX 


Oscillator Frequency 






1 8.432 


MHz 





4-D7 



8228/8238 



ABSOLUTE MAXIMUM RATINGS* 

Temperature Under Bias -0°Cto 70°C 

Storage Temperature -65°C to 150°C 

Supply Voltage, Vcc -0.5V to +7V 

Input Voltage -1 .5V to +7V 

Output Current. 100mA 



*COMMENT: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS Ta = o°c to 7G°C; Vcc 


= 5V±5%. 








Parameter 


Limits 


Unit 




Symbol 


" Min. 


Typ.ll) 


Max. 


Test Conditions 


Vc 


Input Clamp Voltage, All Inputs 




.75 


-1.0 


V 


Vcc=4.75V; !c=-5mA 


'f 


Input Load Current, 
STSTB 






500 


ma 


Vcc = 5.25V 




D2&D6 






750 


ma 


Vf= 0.45 V 




Do, Di,D4;b5, 

&D7 






250 


ma 






All Other Inputs 






250 


ma . 




Ir 


Input Leakage Current 
STSTB 






100 


AiA 


Vcc = 5.25 V 




DBo-DB7 






20 


ma 


Vr= 5.25V 




All Other Inputs 






100 


n^ 




Vth 


Input IThreshoId Voltage, All Inputs 


0.8 




2.0 


V 


Vcc = 5V 


'cc 


Po\A/^;r siibplY Current 




140 


190 


mA 


Vcc=5.25V 


'J6\. 


Output Low Voltage, 
Do-D7 






.45 


V 


Vcc=4.75V; loL=2mA 




All Other Outputs 






.45 


V 


loL = 10mA 


VOH 


Output High Voltage, 
D0-D7 


3.6 


3.8 




V 


Vcc=4.75V;Ioh=-10mA 




All Other Outputs 


2.4 






V 


Iqh =-1mA 


los 


Short Circuit Current, All Outputs 


15 




90 


mA 


Vcc=5V 


'o(off) 


Off State Output Current, 
All Control Outputs 






100 


AiA 


Vcc=5.25V;Vo=5.25 




-100 


mA 


Vo=.45V 


'int 


INTA Current 






5 


mA 


(See Figure below) 



Note 1 : Typical values are for T/\ = 250C and nominal supply voltages. 



4-D8 



< 
a 

< 

@ 



8228/8238 
WAVEFORMS 



r \^, r^h r ^T, /-\_ 



J — V_^ — \—J — V 



J — V 



STATUS STROBE 
•0*0 DATA BUS ' 
OBIN 

JNTA. JOR. MEMR 
HLOA 



^^ 



\J- 



X 



■*- '$H H 



IV 



iz: 



SYSTEM BUS DURING READ 






^Vf 



) BUS DURING READ- 



1 KZX 



I- - 're 



> 



lOmORMEMW 



M I 



BOM BUS DURING WRITE 



-(• — 






X 



SYSTEM BUS DURING WRITE ■ 



•* 'wD -] 






x: 



SYSTEM BUS ENABLE 



SYSTEM BUS OUTPUTS - 






VOLTAGE MEASUREMENT POINTS: Dfl-Dy (when outputs) Logic "0" = 0.8V, Logic "1" = 3.0V. All other signals measured 

at 1.5V. 



•ADVANCED lOW/MEMW FOR 8238 ONLY. 



A.C. CHARACTERISTICS Ta = o°c to vo'C; Vcc = 5V ±5%. 





Parameter 


Limits 


Units 




Symbol 


Min. 


Max. 


Condition 


tpw 


Width of Status Strobe 


22 




ns 




tss 


Setup Time, Status Inputs Dq-D-j 


8 




ns 




tSH 


Hold Time, Status Inputs D0-D7 


5 




ns 




toe 


Delay from STSTB to any Control Signal 


20 


60 


ns 


Cl = 100pF 


tRR 


Delay from DBIN to Control Outputs 




30 


ns 


Cl = lOOpF 


tRE 


Delay from DBIN to Enable/Disable 8080 Bus 




45 


ns 


Cl = 25pF 


tRD 


Delay from System Bus to 8080 Bus during Read 




30 


ns 


Cl = 25pF 


tWR 


Delay from WR to Control Outputs 


5 


45 


ns 


Cu = 100pF 


tWE 


Delay to Enable System Bus DBo-DBy after STSTB 




30 


ns 


Cl = lOOpF 


tWD 


Delay from 8080 Bus DQ-Dy to System Bus 
DB0-DB7 during Write 


5 


40 


ns 


Cu = lOOpF 


tE 


Delay from System Bus Enable to System Bus DB0-DB7 




30 


ns 


Cl = lOOpF 


tHD 


HLDA to Read Status Outputs 




25 


ns 




tos 


Setup Time, System Bus Inputs to HLDA 


10 




ns 




tDH 


Hold Time, System Bus Inputs to HLDA 


20 




ns 


Cl = lOOpF 



4-D9 



8228/8238 AND 8259/8259-5 
CAPACITANCE 

This parameter is periodically sampled and not 100% tested. 



Symbol 


Parameter 


Limits 


Unit 


Min. 


Typ.tll 


Max. 


C|N 


Input Capacitance 




8 


12 


pF 


COUT 


Output Capacitance 
Control Signals 




7 


15 


pF 


I/O 


I/O Capacitance 
(DorDB) 




8 


15 


pF 



Test Conditions: MS: VgiAS = 2.5V, Vcc = 5.0V, Ta = 25°C, f = 1 MHz. 



Note 2: For Dq-D?: R^ = 4Kn, R2 = "0, 
Cl=25pF. For all other outputs: 
Rl =500n,R2= 1Kn,CL= lOOpF. 



|g > 



A- 



A" 







Figure 1. INTA Test Circuit (for RST 7) 



ABSOLUTE MAXIMUM RATINGS' 



Ambient Temperature Under Bias 0°Cto70°C 

Storage Temperature -65°Cto+150°G 

Voltage On Any Pin 

With Respect to Ground -0.5 V to +7 V 

Power Dissipation 1 Watt 



'COMMENT: 

Stresses above those listed under "Absolute Maximum Ratirigs" 
may cause permanent damage to the device. This is a stress rating 
only and functional operation of the device at these or any other 
conditions above those indicated in the operational sections of this 
specification is not implied. 



D.C. CHARACTERISTICS 

(Ta = 0°C to 70°C; Vcc = 5V ±5%) 



SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


V|L 


Input Low Voltage 


-.5 


.8 


V 




V|H 


Input High Voltage 


2.0 


VCC+.5V 


V 




Vol 


Output Low Voltage 




.45 


V 


l0L = 2mA 


VOH 


Output High Voltage 


2.4 




V 


iOH = -400mA 


VoH-lNT 


Interrupt Output High Voltage 


2.4 
3.5 




V 
V 


ioH = -400mA 
loH = -50M 


.'lUIRo-y) 


Input Leakage Current 
for iRo.7 




-300 
10 


ma 


V|N=OV 
V|N = Vcc 


l|L 


Input Leakage Current 
for Other Inputs 




10 


HA 


V|N = Vcc to OV 


'OFL 


Output Float Leakage 




+10 


MA 


VouT = 0.45V to Vcc 


'cc 


Vcc Supply Current 




100 


mA 





CAPACITANCE 

Ta = 25°C; Vcc = GND = OV 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNIT 


TEST CONDITiONS 


C|N 


Input Capacitance 






10 


pF 


fc=1 MHz 


C|/0 


I/O Capacitance 






20 


pF 


Unmeasured pins returned to Vss 



4-D10 



8259/8259-5 



z 
cc 
o 
m 

V) 

O 

< 

Q 

< 

@ 



A.C. CHARACTERISTICS 

(Ta = 0°C to 70° C; Vcc = +5V ±5%, GND = OV) 

Bus Parameters 
Read: 



SYMBOL 


PARAMETER 


8259 
MIN. MAX. 


8259-5 
MIN. MAX. 


UNIT 


tAR 


CS/Ao Stable Before RD or INTA 


50 




50 




ns 


tRA 


CS/Ao Stable After RD or INTA 


5 




30 




ns 


tRR 


RD Pulse Width 


420 




300 




ns 


tRD 


Data Valid From RD/INTAin 




300 




200 


ns 


tDF 


Data Float After RD/INTA 


20 


200 


20 


100 


ns 


Write: 


SYMBOL 


PARAMETER 


8259 

MIN. MAX. 


8259-5 
MIN. MAX. 


UNIT 


tAW 


Ao Stable Before WR 


50 




50 




ns 


tWA 


Ao Stable After WR 


20 




30 




ns 


tww 


WR Pulse Width 


400 




300 




ns 


tow 


Data Valid to WR (T.E.) 


300 




250 




ns 


twD 


Data Valid After WR 


40 




30 




ns 


Ottier Timings: 


SYMBOL 


PARAMETER 


82 
MIN. 


59 

MAX. 


825 
MIN. 


9-5 
MAX. 


UNIT 


^IW 


Width of Interrupt Request Pulse 


100 




100 




ns 


t|NT 


INT t After IRt 


400 




350 




ns 


t|C 


Cascade Line Stable After INTA t 


400 




400 




ns 



Note 1 ; 8259: Cl = 1 0OpF, 8259-5: Cl = 1 50pF. 



Input Waveforms for A.C. Tests 




0.45 



4-D11 



8259/8259-5 



WAVEFORMS 



Read Timing 



^. 



ADDRESS BUS 



X 



\'"2' 



DATA BUS \\\ VhIGH impedance \\\^ 



/ 



X 



^^^^^^ 



Write Timing 



^. 



-Taw- 



€^: 



X 



J 



:c 



X 



'^^^ 



■^Tww* 



Other Timing 



^1: 



r 



\. 



NTA \ © / f \ © / 

DB -y \\ HIGH IMPEDANCE \\\^ 



iwwwwi Uwwwi i\\ 






7" 



Mote: Interrupt Request must remain "HIGH" (at least) until leading edge of first INT A. 



Read Status/Poil IVIode 



"V 



J V 



f 





/ 




_ 






\_ 


/ 








DATASUSV///////// 


0CW3 f//////////////. 


DATA >//////////////, 



4-D12 



TMS 5501 

TMS 5501 ELECTRICAL AND MECHANICAL SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE 
(UNLESS OTHERWISE NOTED)* 



Supply voltage, Vcc (see Note 1) -0.3 V to 20 V 

Supply voltage, V/qd (see Note 1 -0.3 V to 20 V 

Supply voltage, Vss (see Note 1) -0.3 V to 20 V 

All input and output voltages (see Note 1) -0.3 V to 20 V 

Continuous power dissipation 1.1 W 

Operating free-air temperature range 0°C to 70°C 

Storage temperature range — 65°C to 1 50°C 



o 
o 
w 

CO 

< 

03 
UJ 

Z 
c 
o 
m 
w 
O 

< 
o 

< 

@ 



'Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only 
and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating 
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect 
device reliability. 

NOTE 1 : Under absolute maximum ratings voltage values are with respect to the normally most negative supply voltage, Vqq (substrate). 
Throughout the remainder of this data sheet, voltage values are with respect to V33 unless otherwise noted. 

RECOMMENDED OPERATING CONDITIONS 





MIN NOM MAX 


UNIT 


Supply voltage, Vgg 


-4.75 -5 -5.25 


V 


Supply voltage, Vcc 


4.75 5 5.25 


V 


Supply voltage, Vqd 


11.4 12 12.6 


V 


Supply voltage, Vss 





V 


High-level Input voltage, V|h (all inputs except clocks) 


3.3 Vcc+1 


V 


High-level clock input voltage, V|H(0) 


9 Vdd+1 


V 


Low-level input voltage, V|l (all inputs except clocks) (see Note 2) 


-1 0.8 


V 


Low-level clock input voltage, V|L(0) (see Note 2) 


-1 0.8 


V 


Operating free-air temperature, T/^ 


70 


°c 



NOTE 2: The algebraic convention where the most negative limit is designated as minimum is used in this specification for logic voltage levels only. 



Data sheets on pages D-13 through D-16 are reproduced by permission of Texas Instruments Incorporated. 



4-D13 



TMS 5501 

ELECTRICAL CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED OPERATING CONDITIONS 
(UNLESS OTHERWISE NOTED) 



PARAMETER 


TEST CONDITIONS 


MIN MAX 


UNIT 


Input current (any input except 
clocks and data bus) 


V| = V to Vcc 


±10 


*iA 


l|(0) Clock input current 


vi(0) = ov to Vdd 


±10 


HA 


'l(DB) Input current, data bus 


V|(DB) =0V to Vcc, CEatOV 


-50 


HA 


Vqh High-level output voltage 


IOH=400nA 


3.7 


V 


Vol Low-level output voltage 


'OL "^ ^7 "TiA, 


0.45 


V 


'BB(av) Average supply current from Vbb 


Operating at 1^(0) = 480 ns, 
Ta = 25°C 


-1 


mA 


'CC(av) ' Average supply current from Vcc 


100 


iDD(av) Average supply current from Vdd 


40 


Cj Capacitance, any input except clock 


vcc = Vdd = Vss = ov, 

Vbb = -4.75 to -5.25 V, f = 1 MHz, 
All other pins at V 


10 


pF 


C|(0) Clock input capacitance 


75 


Cq Output capacitance 


20 



TIMING REQUIREMENTS OVER FULL RANGE OF RECOMMENDED OPERATING CONDITIONS 





MIN 


MAX 


UNIT 


tc(0) 


Clock cycle time 


480 


2000 


ns 


M<t>) 


Clock rise time 


5 


50 


ns 


^f(0) 


Clock fall time 


5 


50 


ns 


*W(01) 


Pulse width, clock 1 high 


60 


ns 


tw(02) 


Pulse width, clock 2 high 


200 


300 


ns 


td(01 L-02) 


Delay time, clock 1 low to clock 2 





ns 


td(02-01 ) 


Delay time, clock 2 to clock 1 


70 


ns 


td{01H-02) 


Delay time, clock 1 high to clock 2 (time between leading edges) 


80 


ns 


tsu(ad) 


Address setup time 


50 


ns 


tsu(CE) 


Chip-enable setup time 


50 


ns 


tsu(da) 


Data setup time 


50 


ns 


^sulsync) 


Sync setup time 


50 


ns 


tsu(XI) 


External input setup time 


50 


ns 


th(ad) 


Address hold time 





ns 


th(CE) 


Chip-enable hold time 


10 


ns 


th(da) 


Data hold time 


10 


ns 


th(sync) 


Sync hold time 


10 


ns 


th(XI) 


External input hold time 


40 


ns 


twisens H) 


Pulse width, sensor input high 


500 


ns 


*w(sens L) 


Pulse width, sensor input low 


500 


ns 


*d(sens-int) 


Delay time, sensor to interrupt (time between leading edges) 


2000 


ns 


td(rst-int) 


Delay time, RST instruction to interrupt (time between trailing edges) 


500 


ns 



4-D14 



TMS 5501 



< 

oS 
lU 

Z 
K 
O 

m 

CO 

O 

< 

Q 

< 

® 



SWITCHING CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED 
OPERATING CONDITIONS (SEE FIGURES 6 AND 7) 



PARAMETER 


TEST CONDITIONS 


MIN MAX 


UNIT 


'PZX Data bus output enable time 


CL = 100pF, 
Rl= 1.3 kn 


200 


ns 


tPXZ I^^ta bus output disable time to high-impedance state 


180 


ns 


tpo External data output propagation delay time from $2 


200 


ns 



3V 



'Rl= 1.3kn 



TMS 5501 _ 
OUTPUT 



^ir CL = ioopF 



Ci_ includes probe and Jig capacitance 
LOAD CIRCUIT 



K- 
I 

W01)— U- 



tc(0)- 



J^^ 



tr(0)-H 



• tf (0) 
I I* 4"*d(01L^2) 



J^^N^-L 




NOTE: For 01 or 02 inputs, high and low timing points are 90% and 10% of ^\\-\((p). All other timing points are the 50% level. 

FIGURE 6-READ CYCLE TIMING 



4-D15 



TMS 5501 



^^~% 



/ V 




NEW DATA 



NOTE: For 01 and 02 inputs, high and low timing points are 90% and 10% o* V|(^(0) All other timing points are the 50% level. 

FIGURE 7-VURITE CYCLE TIMING 



SENSOR 



INTERRUPT 



RST INSTRUCTION 
ON DATA BUS 
(See Note 1 ) """ 



>*-tw(sens H)-W«-tw(sens L)-H 



-*d(sens-int)- 



r 



■*d(rst-int)- 



NOTES: 1 . The RST instruction occurs during the output data valid time of the read cycle 
2. All timing points are 50% of V 11^. 



FIGURE 8-SENSOR/INTERRUPT TIMING 



4-D16 



Chapter 5 
THE 8085 



0) The 8085A is Intel's enhancement of the 8080A — just as the Z80 is Zilog's enhancement of the 8080A. The 

H Z80 is described in Chapter 7. 

< 

u Intel is the developer of the 8085A; Intel is also the principal manufacturer of the 8080A. But the individuals at 

CO Zilog who developed the Z80 were previously employed by Intel, at which time they developed the 8080A 

< from the 8008. The Z80 and the 8085A therefore have equal claim to be the legitimate desc'endent of the 

c3 8080A. 

ui 

g The 8085A provides the same logic as the 8080A, 8224 and 8228 three-chip CPU. The 8085A has the following 

g additional enhancements: 

(A 

o 1) The 8085A requires a single +5V power supply. 

5 2) The 8085A uses a single clock signal. 

< 3) The 8085A has a primitive on-chip serial I/O capability which may also be used to input status and output control 
Q signals. 

4) The 8085A has interrupt request pins with hardware-generated interrupt vectoring. 

5) The 8085A operates with a standard 320 nanosecond clock as against the standard 500 nanosecond clock of the 
8080A. But recall that there are versions of the 8080A that operate with a 250 nanosecond clock. 

The 8085A instruction set is almost identical to the 8080A instruction set; in contrast, the Z80 has a massively 
expanded instruction set. The large Z80 instruction set has been criticized for its complexity, but one could argue that 
since the Z80 also provides the complete 8080A instruction set, anyone who does not want to use the additional in- 
structions can simply ignore them. 

The 8085A multiplexes its Data Bus with the low-order Address Bus lines. Such multiplexing demands custom 
support devices, or external demultiplexing logic. 

Figure 5-3 and associated text provide a direct comparison of 8085A and 8080A signal interfaces. 

In addition to the 8085A microprocessor, support devices described in this chapter include: 

-The 8155/8156 static RAM with I/O ports and timer. This device provides 256 bytes of static read/write memory. 
-The 8355 ROM with I/O ports. This device provides 2048 bytes of read-only memory plus I/O logic. 
- The 8755A EPROM with I/O ports. This device provides 2048 bytes of erasable programmable read-only memory with 
I/O logic. ' 

The 8085A is a new version of an earlier device, the 8085. In most respects the two parts 
are identical — however, there are some important differences, which we will note 
throughout this chapter. Where we note no difference, the discussion applies to both the 
8085 and the 8085A. 

Standard 8080A support devices described in Chapter 4 and in Volume III cannot be used with the 8085A 
unless the 8085A is operating with a 500 ns clock. If you are using the 8085A with a 320 ns clock, you must 
use the special -5 series of support parts. 

The 8085A prime source is: 

INTEL CORPORATION 

3065 Bowers Avenue 

Santa Clara, California 95051 



8085 AND 
8085A 



The 8085A second source is: 



ADVANCED MICRO DEVICES 

901 Thompson Place 
Sunnyvale, California 94086 



5-1 



The 8085A uses a single +5V power supply; it is packaged as a 40-pin DIP. 

Using a 320 nanosecond clock, instruction execution times range from 1.3 microseconds to 5.75 microseconds. 

All 8085A devices have TTL compatible signals. 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Instruction Register 



Control Unit 



Interrupt Priority 
Arbitration 



Bus Interface 
Logic 



Accumulator 
Registers) 



Data CounteKs) 



Stack Pointer 



Program Counter 



System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 
Interface Logic 



I/O Ports 
Interface Logic 



Read Only 
Memory 



I/O Ports 



RAM Addressing 

and 
Interface Logic 



Read/Write 
Memory 



Figure 5-1. Logic of the 8085A Microprocessor 

THE 8085ACPU 

Functions implemented on the 8085A CPU are illustrated in Figure 5-1 ; they represent typical CPU logic. The 

8085A has an Arithmetic and Logic Unit, a Control Unit, Accumulators and registers. 

Clock logic is on the 8085A CPU chip; only an external crystal or RC network is needed. 
Bus interface logic which was excluded on the 8080A is provided by the 8085A. 
N-channel silicon gate technology is used by all 8085A devices. 



5-2 



8085A PROGRAMMABLE REGISTERS 

The 8085A programmable registers are identical to the 8080A programmable registers. They may be illustrated 
as follows: 





PSW 


A 


B 


C 


D 


E 


H 


L 


SP 


PC 



Program Status Word ) These two sometimes 
Primary Accumulator J treated as a 16-bit unit 
Secondary Accumulators/Data Counter 
Secondary Accumulators/Data Counter 
Secondary Accumulators/Data Counter 
Stack Pointer 
Program Counter 



Z 
oc 
o 
ta 
v> 
O 

< 

o 
< 

@ 



For a discussion of 8085A programmable registers refer to the 8080A CPU description given in Chapter 4. 

8085A ADDRESSING MODES 

The 8085A uses exactly the same memory addressing modes as the 8080A. Direct and implied memory ad- 
dressing are available. See the 8080A addressing modes description given in Chapter 4 for details. 

8085A STATUS 

The 8085A has the same set of status flags as the 8080A; status flags are stored in the same bits of the Pro- 
gram Status Words. The five status flags provided are: 

Zero (Z) 
Sign (S) 
Parity (P) 
Carry (C) 

Auxiliary Carry (AC) 
Status flags are assigned to bits of the Program Status Words as follows: 



7654 321 ^ 

|s|z|x|Aclx|p|7Tc1 



I j s 



Bit No. 



Unassigned 



For a discussion of status flags refer to the 8080A status description given in Chapter 4. 

8085A CPU PINS AND SIGNALS 

8085A CPU pins and signals are illustrated in Figure 5-2. 

Whereas the internal architecture and the instruction sets of the 8080A and the 8085A are very similar, pins and sig- 
nals are not. We will therefore begin by describing 8085A signals without reference to, or comparison with, the 8080A; 
then we will compare the two interfaces. 

The Address and Data Busses of the 8085A are multiplexed. Pins A8 - A15 are output-only lines which carry the 
high-order byte of memory addresses. ADO - AD7 are bidirectional lines which output the low-order byte of memory 
addresses; ADO - AD7 also serve as a bidirectional Data Bus. 



5-3 




Vcc( + 5V) 

HOLD 

HLDA 

CLOCK (O UT) 

RESET IN 

READY 

lO/M 

SI 

RD 

VVR 

ALE 

SO 

A15 

A14 

A13 

A12 

All 

A10 

A9 

A8 



PIN NAME 

ADO ■- AD7 

A8-'a15 

ALE 

RD 

WR 

lO/M 

SO, SI 

READY 

SID 

SOD 

HOLD 

HLDA 

jNTR 

TRAP 

RST! 

RSTi 

RST 

INTA 

RESET IN 

RESET OUT 

XI, X2 

CLK 

^CC Vss 



DESCRIPTION 

Address/Data Bus 

Address Bus 

Address Latch Enable 

Read Control 

Write Control 

I/O or Memory Indicator 

Bus State Indicators 

Wait State Request 

Serial Data Input 

Serial Data Output 

Hold Request 

Hold Acknowledge 

Interrupt Request 

Non-maskable Interrupt Request 

Hardware vectored 
interrupt requests 

Interrupt Acknowledge 
System Reset 
Peripherals Reset 
Crystal or RC Connections 
Clock Signal 
Power, Ground 



TYPE 

Bidirectional, tristate 

Output, tristate 

Output* 

Output, tristate 

Output, tristate 

Output, tristate 

Output 

Input 

Input 

Output 

Input 

Output 

Input 

Input 

{Input 
Input 
Input 
Output 
Input 
Output 
Input 
Output 



♦This output is tristate on the 8085, but not on the 8085A 



Figure 5-2. 8085A CPU Signals and Pin Assignments 



5-4 



< 

Q 
< 

@ 



ALE is an address latch enable signal which pulses high when address data is being out- ALE DIFFERENCE 

put on ADO - AD7. You may use the falling edge of ALE to strobe the address off IN 8085 AND 

ADO - AD7 into external latches if you are demultiplexing ADO - AD7 into separate Address 8085A 

and Data Busses. ALE is a tristate output on the 8085, an earlier version of the 8085A. •— — — — ^— ^— 

Five control signals control memory and I/O accesses. 

RD is pulsed low for a memory or I/O read operation. 

WR is pulsed low for a memory or I/O write operation. 

lO/M is output high in conjunction with RD or WR for an I/O access. 

lO/M is output low in conjunction with RD or WR for a memory read or write operation. 

The state of the System Bus is further defined by the SO and SI status signals as follows: 



8085A 

CONTROL 

SIGNALS 



SI 


so 


OPERATION SPECIFIED 








Halt 





1 


Memory or I/O write 


1 
1 




1 


Memory or I/O read 
Instruction fetch 



8085A 
DATA BUS 
DEFINITION 
SIGNALS 



8085A 
SERIAL I/O 



External logic that does not have sufficient time to respond to an access can gain additional time by using the READY 
input signal. The READY input can be used to insert Wait state clock periods in any machine cycle. Timing and 
logic associated with Wait states is described later in this chapter. 

Two signals allow a primitive serial I/O capability. The high-order Accumulator bit may be out- 
put via SOD. The signal level at SID may be input to the high-order bit of the Accumulator. 

SID and SOD may also be used to input status and to output control signals. 

Two signals allow external logic to take control of the System Bus. 

HOLD, when input high, floats the Address Bus plus the RD, WR, lO/M and ALE control sig- 
nals. HLDA is output high to acknowledge this Hold condition. 

There are six signals associated with interrupt logic. Interrupts may be requested via INTR, 
RST 5. 5, RST 6.5, RST 7.5 and TRAP. An interrupt request made via INTR is acknowledged 
via the INTA output. 

INTR is the general purpose interrupt request used by external logic: it is equivalent to the 8080A 
INTR signal. 

TRAP is a non-maskable, highest priority interrupt request. TRAP is used for catastrophic failure interrupts. 

RST 5.5, RST 6.5 and RST 7.5 are three interrupt request signals supported by hardware-implemented vectoring. 

Interrupt capabilities of the 8085A are described in detail later in this chapter. 

There are two signals associated with 8085A Reset logic. 



8085A BUS 

CONTROL 

SIGNALS 



8085A 

INTERRUPT 

SIGNALS 



8085A 
RESET 
SIGNALS 



RESET IN is the Reset input signal. This signal need not be synchronized with the clock. RESET 
OUT is a Reset signal output by the 8085A for use throughout the rest of the 8085A microcom- 
puter system. 

X1 and X2 connect an external crystal or RC network to drive clock logic internal to the 8085A. A crystal will be 
connected as follows: 



JT 

D 



XI 



X2 



5-5 



An RC network will be connected as follows: 



U 



XI 



X2 



You can apply a clock signal directly to XI 



+ 5V 



CLK 



XI 



X2 



The input frequency must be twice the operating frequency. Thus, to obtain a 320 nanosecond clock, or 3.125 
MHz, the input frequency must be 6.25 MHz. 

Slave 8085A devices in a multiple CPU system will usually be driven directly by a clock signal. 

A TTL level clock signal (CLK) is output by the 8085A. It may be used to drive slave CPUs, or for any other synchroniza- 
tion purpose within the microcomputer system. The frequency of CLK is the operating frequency of the 8085A; that is, 
the CLK frequency is half the input frequency. 




UtdMd 
byAl£ 



«» A13 

A14 



•Signals no longer needed or not present. 'busen- 

New 8085A signals: RST 5.5, RST 6.5, RST 7.5, TRAP, RESET OUT, SID, SOD 
Shaded signals represent 8085A equivalents of 8080A. 



DBO 


AOO 


DB1 


ADI 


DB2 


Ao: 


DBS 


AOJ 


DB4 


AD4 


DBS 


ADS 


DB« 


AO* 


DB7 


Aor 


mi. 

MEMW 

ITOR 

l/OW 


Ttfti . 

?VR.IO/M 
RO-IO/M 
WR.IO/M 



Figure 5-3. A Comparison of 8085A and 8080A/8224/8228 Signal Interface 



5-6 



A COMPARISON OF 8085A AND 8080A SIGNALS 

No attempt has been made to maintain any Icind of pin compatibility between the 8085A and the 8080A. 

Nevertheless, as illustrated in Figure 5-3, it is relatively simple to derive equivalent system busses when using 

the 8085A or 8080A. But look at Figure 5-3 with an element of caution. Many logical combinations of 8085A signals 

are shown reproducing 8080A signals; in reality you will never generate such logical combinations — a point which 

Q will become clear as the chapter proceeds. The purpose of Figure 5-3 is to illustrate the equivalence of the system 

t- busses generated by the 8085A and the 8080A without indicating that creation of equivalent busses is desira- 

c ble. 

o 

DC The 8080A signals which are shown as having direct 8085A equivalents are either obvious, or will become so after you 

§ have read this chapter. 

2 

~ What is more interesting is to, look at the 8080A signals which no longer exist and the new 8085A signals which have 

lu been added. 

5 Let us first look at the signals which have been dropped. 

« There are the surplus power supplies -5V and -M2V, plus the secondary power supplies required by the 8224 Clock 

< Generator and the 8228 System Controller. Elimination of these signals is self-evident. 

o3 

lu INTE is an 8080A signal that indicates to external logic when interrupts have or have not been enabled internally by the 

^ 8080A. This signal is not very useful, since external logic cannot use the information it provides. Apart from illuminat- 

g ing an appropriate indicator on a minicomputer-like control panel, the INTE signal of the 8080A serves little useful pur- 

g pose. 

S WAIT is a signal which is output high by the 8080A while Wait states are being inserted within a machine cycle. There 

Q is little that external logic can do with this signal, therefore its elimination in the 8085A carries no penalty. 

< 



@ BUSEN is a control input to the 8228 System Controller; it causes the 8228 to float its output signals. This signal is no 

longe r required in the 8085A since the Hold state floats all equivalent 8085A output signals — with the exception of 
INTA, which does not need to be floated. 

The 8224 Clock Generator outputs two synchronizing clock signals — OSC and <I>2 (TTL). <I>2 (TTL) is approximately 
reproduced by CLK; OSC has no equivalent 8085A signal. 

The TANK input to the 8224 Clock Generator allows overtones of the external crystal to be used. No such signal exists 
with the 8085A — which simply means that you have to use the primary frequency of any crystal connected across the 
XI and X2 inputs. 

Seven new signals have been added to the 8085A: it would have been possible to provide separate Data and 
Address Busses by eliminating these seven signals, plus the ALE control signal whose presence is a direct conse- 
quence of having multiplexed Data and Address Busses. Intel has chosen to provide the seven new signals, paying the 
price of having multiplexed Data and Address Busses. 

Let us examine the new signals. 

RST 5.5, RST 6.5, RST 7.5 and TRAP represent additional interrupt request inputs. TRAP is a non-maskable, high 
priority interrupt; the other three interrupt requests are supported by hardware-implemented vectoring. 

RESET OUT is a Reset signal output by the 8085A; it may be used to reset support devices around the 8085A. 

SID and SOD are control signals which provide a primitive serial input and output capability. These signals can also be 
used as a general purpose status input (SID) and a control output (SOD). 

8085A TIMING AND INSTRUCTION EXECUTION 

An 8085A instruction's execution is timed by a sequence of machine cycles, each of which is divided into clock 
periods. 



An instruction is executed in from one to five machine cycles labeled MCI, MC2, MC3, 
MC4 and MC5. 



8085A 

MACHINE CYCLES 



5-7 



The first machine cycle of any instruction's execution will have either four or six clock periods. 
Subsequent machine cycles will have three clock periods only. This may be illustrated as follows: 



8085A 
CLOCK 
PERIODS 



MCI 


MC2 


MC3 


MC4 


MC5 1 


Ti|t2 


T3|T4|T5|T6 


Tl 


T2 


T3 


11 


T2 


T3 


Tl 


T2 


T3 


Tl 


T2 


Id 



Where MC is shaded, the entire machine cycle is optional. Where T is shaded, the clock period is 
optional within its machine cycle. 

8085A machine cycles and clock periods are very similar to those of the 8080A. You willfind in Table 5-1 that the 
number of clock periods required to execute 8085A instructions is equal to the number of clock periods required by the 
8080A to execute the same instructions, or differs by one clock period only. 

THE CLOCK SIGNALS 

The 8085A times its machine cycles using this simple clock signal: 



MCI 


MC2 


MC3 


Tl 


T2 


T3 


T4 


Tl 


T2 


T3 


Tl 



















CLK 




Although the 8085A has no SYNC signal to identify the start of a new machine cycle, you can use the 8085A 
ALE signal for the same purpose. This signal is output true during the first clock period of every machine cycle — at 
which time the ADO - AD7 lines are outputting address data. In addition, you can identify the first (instruction fetch) cy- 
cle of any instruction's execution. SO and SI will both be output high during an instruction fetch machine cycle. Clock 
periods and machine cycles may therefore be identified as follows: 



CLK 



lO/M 



A8-A15 



ADO - AD7 




ALE 



Tl identified 



MCI identified 
byS0 = 1 
and SI = 1 



5-8 



MEMORY ACCESS SEQUENCES 

So far as external logic is concerned, there is very little difference between an instruction fetch, a memory 
read, and a memory write. We will therefore examine timing for these operations together. 



z 
ce 
o 
a 
<n 
o 

< 

Q 

< 

© 



MC1 


MC2 


Tl 


T2 


T3 


T4 


Tl 


T2 


. 


















i 



CLK 



lO/M 



A8-A15 



ADO - AD7 



ALE 




Figure 5-4. A Four Clock Period Instruction Fetch Machine Cycle 

Let us first consider an instruction fetch. Timing is illustrated in Figure 5-4 for a four clock period machine cycle, 
and in Figure 5-5 for a six clock period machine cycle. 

The nnost important aspect of the instruction fetch machine cycle is the fact that it will have either four or six clock 
periods, as against three for all subsequent machine cycles. The instruction fetch machine cycle must have at least four 
clock periods, since the fourth clock period is needed to decode the instruction object code which has been fetched. If 
the instruction requires no subsequent memory accesses, then a fifth and sixth clock period may be needed to perform 
the internal operation specified by the fetched instruction. If additional memory accesses will be required, then the 
fourth clock period of the first machine cycle is sufficient. 

At the end of the first clock period, ADO - AD7 is floated transiently; then it is turned around to act as a Data Input Bus. 
RD is pulsed low to strobe data onto the Data Bus. 

The memory read must occur within three clock periods. Since this is an instruction fetch machine cycle, the CPU will 
place the input in. the Instruction register. If external logic requires more time to respond to the memory access, then it 
can generate additional Wait clock periods. We will describe the 8085A Wait state shortly. 

During the fourth clock period of the instruction fetch machine cycle the instruction object code is interpreted by logic 
of the 8085A CPU. Fifth and sixth clock periods will be required by some instructions to execute required internal 
operations.. 



5-9 



MCI 


MCI 


Tl 


T2 


T3 . 


T4 


T5 


Te 


Tl 


T2 


T3 


T4 























CLK 



lO/M 



A8-A15 



ADO - AD 7 





I ' M ' ■ " I li I 

Unspecified | f PC high-order byte 1 . 



{ 



Input 



y 



order byte instruction 
1| » I obiect code 



Instruction Fetch 



Instruction decode 
and execute 



Figure 5-5. A Six Clock Period Instruction Fetch Machine Cycle 
During the fourth and subsequent clock periods, ADO - AD7 is floated and A8 - A15 contains unspecified data. 



8085A 
DEVICE 
SELECT 
LOGIC 



The fact that ADO - AD7 and AS - A15 are unl<nown data during the fourth and subsequent 
clock periods of an instruction fetch machine cycle must be taken into account when you 
create memory select and I/O device select logic. 

In Figures_5-4 and 5-5 SO and SI are both high, identifying this as an instruction fetch nnachine 
cycle. lO/M is low since the instruction object code is to be fetched from nriemory. An instruction • 
fetch is thus equivalent to a mennory read. 

The address of the memory location to be accessed is fetched from the Program Counter (PC) and is output on 
ADO - AD7 (low-order byte) and A8 - A1 5 (high-order byte). The low-order byte of this memory address is stable on 
ADO - AD7 during the first clock period. ALE is pulsed high at this time. The trailing edge of ALE is designed to act 
as a strobe signal which external logic can use to latch the low-order address byte off ADO - AD7. If you are using 
one of the 808&A support devices (the 8155, the 81 56 the 8344 or the or the 8755A), then the low-order byte 



5-10 



of the memory address is latched off the ADO • AD7 lines for you. If you are using standard memory devices, 
then you must demultiplex ADO • AD7. Any simple latched buffer can be used for this purpose; here is an exam- 
ple of the 8212 I/O port being used as a demultiplexer: 



EC 

o 

ffi 

(0 

o 

< 
< 
© 




Data Bus 



You might argue that there is no harm done if memory or I/O devices select themselves 
when the System Bus is supposed to be idle; if neither the read nor write strobe is present, 
data transfer between the System Bus and the selected device cannot occur. 



MULTIPLE 
DEVICE 
SELECTS 
AND BUS 
LOADING 



Unfortunately, the problem is not so simple. 

It is possible for more than one memory or I/O device to consider itself selected while the bus is 
idle; this may occur under the following conditions: 

1) If I/O devices are being selected as I/O ports, then the Address Bus lines may select an I/O port while 
simultaneously selecting a memory device. 

2) In microcomputer systems that use only a small portion of the total allowed memory — and most microcomputer 
systems fall into this category — memory select logic need not decode unique memory addresses. Here is an ex- 
ample of two 4096-byte memory modules, each of which uses a single line of the Address Bus in order to create 
device selects; 



{> 



A15 
A14 
All 
AO 



CS1 



:} 



\> 



Address to Memory 

Module 1 
'J Address to Memory 
•f Module 2 

- CS2 



5-11 



Memory module 1 will be assigned the address space8000i5 through SFFFis- Memory module 2 will be assigned the 
address space 4000i g through 4FFFi 5. In reality a variety of other addresses will select memory modules 1 or 2. Ad- 
dresses COOO-) 5 through CFFFi 5 will select memory modules 1 and 2. 

A correctly written program will keep either A1 5 or A1 4 low; but while the System Bus is floating, both address lines 
could be high — in which case both memory modules will become selected. 

While signal levels on the Address Bus are changing state, memory and I/O devices may be transiently selected. Tran- 
sient selection may occur during T1 as well as during T4, T5 and T6. Transient selection may leave more than one 
memory or I/O device simultaneously selected for shor| periods of time. 

If more than one memory or I/O device is simultaneously selected, excessive loads m^y be placed on the 
System Bus: At best, these excessive loads will cause devices connected to the System Bus to temporarily malfunc- 
tion; at worst, device failures may result. 

It is very important to prevent devices from being spuriously selected. 

If you use RQ|\^ devices with multiplechip select inputs, you can prevent transient memory 
selection by connecting the 8085A RD output to one of the select (or enable) inputs. This 
will ensure that the device responds only when a valid address is on the System Bus; therefore 
only one ROM device wiUbe selected at a time. Refer to Volume III for information on memory 
devices. 

The simplest way of preventing memory and I/O device selection is to use lO/M. RD and 
WR as contributors to device select logic: 



PREVENTING 

TRANSIENT 

SELECTION 



PREVENTING 
SIMULTANEOUS 
SELECTION 
OF I/O AND 
MEMORY 



ADO A15 



RD. 
WR- 




0^-33 



lO/M- 



Memory 
Select 




lO/M 



5-12 



Timing for the memory select illustrated above may be illustrated as follows: 





Ti 


T2 


T3 




. 






L_ 






L 


CLK^ 


_J 


_/ 


; / 


lO/M 

RDor WR 

Memory 
Select 


A_ 








!_ 










/ 




^ . 












/ 















< 
a 
< 

@ 



I/O device select logic timing differs only in the level of lO/M. 

!0/M distinguishes between memory and I/O devices. When RD or WR is low, memory or I/O 
device addresses must be valid. Thus the logic illustrated above will guarantee that spurious 
memory and I/O device selects never occur. • 

But there is a problem associated with the solution illustrated; memory and ]/0 devices do not receive a valid select sig- 
nal until early in the second clock period. This is unfortunate, since valid addresses are available early in the first clock 
period. Delaying memory select logic until the second clock period may require Wait states to be added between clock 
periods 2 and 3 — and that unnecessarily slows down CPU operations. If e>i;ecution speed is not a problem to you, then 
the simple select logic illustrated above will do. If execution speed is a problem, then you must replace: 



RD 

WR. 



O 



in the simple select logic with alternative logic that may be defined as follows: 



ALE 



RD or WR 



5 



5-13 



The required S output may be generated using two flip-flops as follows: 




RESET 



If your system contains an 8085, rather than an 8085A, the first S output after a Reset will 
occur before the address. lines are valid. Since ALE is tristate in the 8085, a falling edge occurs 
when Reset goes off; at this tinne the address lines may still be floating. One solution is to con- 
nect the first J input above to the Q output of the following D flip-flop: 



SELECT 
PROBLEM 
WITH 8085 



vcc 



ALE 



>CK 7474 



RESET ■ 



{> 



CLR 



The flip-flop above prevents S from going high until after the first rising edge of ALE. 



5-14 



(A 

< 
oS 

UJ 

Z 
cc 
o 
m 

M 

o 

< 

Q 

< 



MCI 


MC2 


MCI 


Tl 


T2 


Ta" 


T4 


Tl 


T2 


T3 


Tl 



















CLK 



lO/M 



A8 - A15 



ADO - AD7 A°'''^^'^ bytei»B>f object code 
I 



ALE 



Instruction Fetch' 



Memory Read 




Figure 5-6. A Memory Read Machine Cycle Following an Instruction Fetch 



Let us now consider a memory read operation; timing is illustrated in Figure 5-6. So far as ex- 8085 

ternal logic is concerned, the only difference between a memory read and an instruction fetch is MEMORY 
the SO and SI signal levels; they are both high for an instruction fetch, but SO is low during a READ TIMING 
memory read. Also, the instruction fetch has four or six clock periods, while the memory read has 
three; but the extra instruction fetch clock periods occur after the memory access is completed. Therefore, so far as ex 
ternal logic is concerned, the extra clock periods of the instruction fetch machine cycle are irrelevant. 



5-15 



CLK 



10/M 



A8-A15 



ADO - AD7 



ALE 



MCI 


MC2 


MCI 


Tl 


T2 


T3 


T4 


Tl 


T2 


■^3 


Tl : 
























Instruction Fetch 



I/O Read 



Figure 5-7. An I/O Read Machine Cycle Following an Instruction Fetch 



Figure 5-7 illustrates I/O read timing. Only the lO/M signal level in Figure 5-7 differs from 
Figure 5-6. 

Memory write timing, illustrated in Figure 5-8, is v ery similar to memory read timing. The 

principal difference is that during a mennory write WR is output low, whereas during a memory 
read RD is output low. Also, during a memory write operation SI is output low while SO is out- 
put high. , 

An I/O write operation is illustrated in Figure 5-9. As compared to Figure 5-8, lO/M is high in 
Figure 5-9 during the write machine cycle; there are no other timing differences. 



8085 I/O 
READ TIMING 



8085 
MEMORY 
WRITE TIMING 



8085 I/O 
WRITE TIMING 



5-16 



MCI 


MC2 


MC1 


Tl 


T2 


T3 


T4 


Tl 


T2 


T3 


Tl 



















< 

< 



lO/M 



A8-A15 



ADO - AD7 Uorder byte\iiiiil object code 




Instruction Fetch 



Menriory Write 



Figure 5-8. A Memory Write Machine Cycle Following an Instruction Fetch 



5-17 



MCI 


MC2 


MCI 


Tl 


T2 


T3 


T4 


Tl 


T2 


T3 


Tl 



















CLK 



lO/M 



A8-A15 



ADO - AD7 




ALE 



WR 



Instruction Fetch 



I/O Write 



Figure 5-9. An I/O Write Machine Cycle Following an Instruction Fetch 

BUS IDLE MACHINE CYCLES 

During a Bus Idle machine cycle no control signals change state on the System Bus. 
There are three types of Bus Idle machine cycles: 

1) 



8085A 
BUS IDLE 
MACHINE 
CYCLE 



2) 



An instruction fetch Bus Idle machine cycle. The 8085A CPU acknowledges an interrupt from 
TRAP, RST 5.5, RST 6.5, and RST 7.5 by generating a Restart instruction internally. No exter- 
nal instruction fetch operations occur; however, logic internal to the CPU requires time to 
create the instruction object code. Therefore a Bus Idle instruction fetch machine cycle is executed. Timing is il- 
lustrated in Figure 5-17. 

The instruction execute Bus Idle machine cycle. Only the DAD instruction uses this machine cycle. The DAD in- 
struction adds the contents of two CPU registers to two other CPU registers. It takes six clock periods for logic in- 
ternal to the 8085 CPU to complete these operations. The six clock periods are generated via two instruction ex- 
ecute Bus Idle- machine cycles. Timing is illustrated in Figure 5-10. 



Figure 5-10 shows a difference in operations between The 8085A and the earlier version, the 
8085. During an instruction execute Bus Idle machine cylce, the 8085A does not gener- 
ate a high pulse on ALE. The 8085, however, pulses ALE high during every Tl of every 
machine cycle — including instruction execute Bus Idle machine cycles. 
3) The Halt Bus Idle machine cycle. Following execution of a Halt instruction an indeterminate number of Bus Idle 
machine cycles are executed for the duration of the Halt condition. Timing is illustrated in Figure 5-14. 



ALE GENERATION 
IN 8085 AND 
8085A 



5-18 



The condition of the lO/M, S1 and S2 signals during a Bus Idle machine cycle varies with the type of Bus Idle 
machine cycle. These three signals will conform to instruction fetch level during an instruction fetch Bus Idle machine 
cycle. During an instruction execute Bus Idle machine cycle, Memory Read signal levels are maintained, but the RD 
control signal is not pulse low. 

During a Halt Bus Idle machine cycle, SO and SI are both low but lO/M, along with other tristate signals, is floated. 



w 

(A 

< 

lU 

Z 
c 
o 
m 

(0 

o 
< 

D 

< 

@ 



MCI 


MC2 


MC3 


Tl 


T2 


T3 


T4 


Tl 


T2 


T3 


Tl 



















CLK 



lO/M 



A8-A15 



ADO - AD7 



ALE 



WR I 




•8085A does not generate ALE; only 8085 generates ALE during MC2 and MC3 of DAD. 



Instruction Fetch 



Bus Idle 



Figure 5-10. A Bus Idle Machine Cycle Following an Instruction Fetch During 
Execution of a DAD Instruction 



5-19 



MCI 


MC2 


MCI 


Tl 


T2 


T3 


T4 


Tl 


T2 


Tw 


Tw 


T3 


Tl 























CLK 



lO/M 



A8-A15 



ALE 



READY 




I PC low -order 
AD0-AD7 f byte 
I 



Instruction Fetch 



Memory Read with Wait States 



Figure 5-11. Wait States Occurring in a Memory Read Machine Cycle 

THE WAIT STATE 

The 8085A will insert Wait states between clock periods T2 and T3 in a manner that is closely analogous to the 
8080A. Timing is illustrated in Figure 5-11, which shows Wait states being inserted in a memory read cycle; a 
Wait state inserted in any other memory reference or I/O machine cycle would differ only in the levels of control 
signals. 

The 8085A sannples the READY line during T2. If READY is low during 12, then a Wait clock period will follow 12. The 
READY line is sampled in the middle of each Wait clock period; Wait clock periods continue to be inserted until READY 
is sampled high. As soon as READY is sampled high, the next clock period will be a T3 clock period — and normal pro- 
gram execution continues. This sampling may be illustrated as follows: 



CLK 



Tl 


T2 


Tyv 


Tw 


Tw 


T3 




9 


i 




9 


i 



READY 



r\ 



5-20 



Wait states are used in an 8085A system exactly as described for the 8080A in Chapter 4 — to give slow memories and 
I/O devices more time in order to respond to an access. Thus the discussion of Wait states provided in Chapter 4 ap- 
plies equally to the 8085A. 

In Chapter 4 a pair of 7474 flip-flops are shown creating a low READY pulse that generates a single Wait state in a 
memory read machine cycle. For the 8085A the following variation applies: 



o 

CQ 
(A 
O 

< 
< 
@ 



lO/M 
ALE 



1— i~\ 

M d J 



^O— 



D1 



Q1 



X:LK 7474 



CLEAR 



CLK (8085A) 



-{> 




•CLK is rising edge triggered 
•CLEAR is low level active 



The circuit will operate with the following timing: 



READY 





Ti 


T2 


Tw 


■^3. 











CLK (8085A) 



ALE 



READY 




If the cycle is a memory read (S = 1, SO = 0) or an instruction fetch (SI = 1, SO = 1), Q1 will go high at the falling edge 
of ALE. This will cause flip-flop 2 to go on at the next falling edge of the 8085A clock, thereby forcing READY low. The 
low on READY will clear flip-flop 1, so that READY will return high on the next falling edge of the 8085A clock. 

THE SID AND SOD SIGNALS 

The 8085A has two instructions which handle single-bit data. 

The RIM instruction inputs data from the SID pin to the high-order bit of the Accumulator. The SIM instruction 
. outputs the high-order bit of the Accumulator to the SOD pin. 

You may use the RIM and SIM instructions in order to implement a primitive serial I/O capability. A more useful applica- 
tion of these instructions is to read single signal status and to output single-signal controls. 



5-21 



When the RIM instruction is executed, the SID signal level is sampled on the rising edge of the clock signal during clock 
period T3 of the instruction fetch machine cycle. The high-order bit of the Accumulator is modified while the clock sig- 
nal is high during T1 of the next instruction fetch machine cycle. Timing may be illustrated as follows: 



CLK 



A, Bit 7 



MCI 


MCI 


Tl 


T2 


T3 


T4 


Ti 


T2 
















When an SIM instruction is executed, the actual change in SOD signal level does not occur until T2 of the next instruc- 
tion fetch machine cycle; that is to say execution of the SIM instruction overlaps with the next instruction fetch. 

This may be illustrated as follows: 



MCI 


MCI 


T, 


^2 


^3 


T4 


•Ti 


^2 


T3 


T4 



















CLK 



A, Bit 7 



SOD 




Following an SIM instruction fetch, the high-order bit of the Accumulator is sampled while the clock is low during T2 of 
the next instruction fetch machine cycle. During the same clock period, the SOD signal level is modified to reflect the 
contents of the high-order Accumulator bit. This overlap is feasible since neither the SOD signal nor the Accumulator 
contents are modified while an instruction is being fetched. Note that SOD must be enabled before it can be accessed 
or changed; you use bit 6 of the Accumulator to enable SOD, as detailed later in this chapter when we describe the 
8085A instruction set. 



5-22 



Figure 5-12 illustrates SID and SOD signal timing during execution of a RIM instruction followed by a SIM in- 
struction. 



z 
oc 
o 
m 

(O 

O 

< 
< 
© 



MCI 


MCI 


MCI 


Tl 


T2 


T3 


T4 


Tl 


T2 


T3 


T4 


Tl 


T2 


T3 


T4 



























CLK 



SOD 



A REG (BIT 7) 



ADO - AD7 



ALE 




A8-A15 j[ PC high-order byte f 



Figure 5-12. A RIM Instruction Followed by a SIM Instruction 



5-23 































MCI 




MCI 


Tl 


T2 


T3 


T4H 


Th 


Th 


Tl 


T2 






















1 



HOLD 



HLDA 



lO/M 




A8-A15 1 PC 



ADO - AD 15 forder byte; 



Figure 5-13. A Hold State Following a Sipgle Machine Cycle Instruction Execution 



THE HOLD STATE 

The 8080A and the 8085A both usp the Hold state as a means of transiently floating the System Bus. During a 
Hold, external logic gains bus control, usually to perform direct memory access operations. 

External logic requests a Hold state by inputting HOLD high. The nnicroprocessor responds by entering the Hold state 
and outputting HLDA high. During h Hold state the microprocessor floats all tristate signals. 



HOLD STATE 
IN 8085 AND 
8085A 



|n the 8085, an earlier version of the 8085A, ALE is a tristate signal and is floated during the 
Hold state. In the 8085A, however, ALE is kept low during Hold. 

Both the 8080A and the 8085A initiate the Hold state at the conclusion of an instruction's execu- 
tion. But there are significant differences between Hold state initiation logic for the 8085A as * 
against the 8080A. 

The SOSOA initiates a Hold state following T3 for a Read nnachine cycle, or following T4 for a Write machine cycle. Tim 
ing is illustrated in Figures 4-9 and 4-10. 



5-24 



The 8085A in contrast, has a fixed, two machine cycle sequence for Hold state initiation; it may be illustrated as 
follows: 



CLK 



HOLD 



HLDA 




HOLD 



< 

Q 

< 

@ 



During every machine cycle. Hold is sampled during T2; if Hold is high at this time, Hold acknowledge is output 
high during T3 and the Hold state begins during T4. Timing is illustrated in Figure 5-13. 

During a six clock period machine cycle, if Hold is low when sampled during T2, then Hold will be sampled again 
during T4. If Hold is sampled high during T4, then a Hold state will be initiated during T6. This may be illustrated as 
follows: 



CLK 



HOLD 



HLDA 



Tl 


T2 


T3 


T4 


T5 


T6H 




















Hold is sampled during every clock period of a Halt state: As soon as Hold is detected high, a two clock period Hold 
state initiation sequence begins. Figures 5-1 4 and 5-1 5 illustrate the onset of Hold states within and before Halt states. 

A Hold state terminates two clock periods after the Hold signal goes low. 

There are no restrictions placed by 8085A logic on the duration of a Hold state. The Hold state lasts for as long as the 
HOLD input is high. Here is an example of a one clock period Hold state occurring during T4 and a three clock period 
Hold state beginning during T6 of a six clock period machine cycle: 



CLK 



HOLD 



HLDA 



MCI 


HOLD 


MCI 


Tl 


T2 


T3 


T4H 


T5 


T6H 


TH 


TH 


Tl 


T2 


T3 


T4 



























^/l^I/\/l/\/lJl_^\_^L^L^L/1 




5-25 



Figure 5-1 3 illustrates a Hold state lasting three clock periods, beginning during T4 of a four clock period machine cy- 
cle. 

THE HALT STATE AND INSTRUCTION 

When a Halt instruction is executed, tlie 8085A enters a IHalt state. The l^alt state consists of an indeterminate 
number of Halt Bus Idle clock periods, during which the SI and SO status signals are both output low while the 
tristate signals are floated. 

In the 8085, an earlier version of the 8085A, ALE is a tristate signal and is floated during the 
Halt state. In the 8085A, however, ALE is kept low during Halt. 

Halt state timing is illustrated in Figure 5-14. 



HALTSTATE 
IN 8085 AND 
8085A 



MCI 


HALT 


MCI 


Tl 


T2 


T3 


T4 


Thalt 


thalt 


Thalt 


Tl 


















i 



A8-A15 



I PC low. 
ADO -AD 15 lorder byte 




, Figure 5-14. A Halt Instruction and a Halt State Terminated by an Interrupt Request 

A Halt state may be terminated by a system reset or by an interrupt request. Figure 5-14 shows an interrupt re- 
quest terminating the Halt state. 

Note that the INTR signal, like the HOLD signal, is sampled two clock periods before anything can happen. Thus, as il- 
lustrated in Figure 5-14, an additional Halt clock period will occur after the clock period within which INTR goes high. 



5-26 



z 
oc 
o 

CO 
0) 

o 

< 
o 

< 







HOLD 


HOLD HOLD 










MCI 


HALT 


MCI 


Tl 


T2 


T3 


T4 


Tl 


THALT ThALT 


THALT 


Tl 




1 


{ rn 


: 15^ 


, r^ 


i r- 


r?i r9- 


1 rn 


1/ rn 


^ 




Figure 5-15. Hold States Occurring Within a Halt State 



8085A HOLD 
WITHIN A 
HALT STATE 



An interrupt request will only be executed if interrupts are enabled; however, the 8085A has a TRAP non-maskable in 
terrupt. Thus you can always exit an 8085A Halt state via a TRAP interrupt request or by resetting the system. 

While in a Halt state you can enter and exit the Hold state. Figure 5-15 illustrates timing for 
the Hold state existing within the Halt state. Notice that the Hold state only lasts for as long as 
the HOLD input is kept high. 

Entering a Hold state within a Halt state also prevents you from terminating the 8085A Halt state 
with an interrupt request; this is because a HOLD request has priority over any interrupt request. Thus, if an interrupt 
request occurs while the 8085A is entering a Hold state, or is in a Hold state, the interrupt request will be ignored until 
the end of the Hold state. At that time, the interrupt request will be acknowledged — providing interrupts are enabled. 

Resetting the 8085A will terminate a Halt state at any time, whether or not you are in a Hold state. 



5-27 





:/: . MCI 




T2 


T3 


Ti 


t2 


"^3 


T4 


T5 


T6 


Tl 




* /^ 

















CLK 



lO/M 



SO 



SI 



A8-A15 



ADO - AD7 



ALE 



RD 



INTA 



INTR 




•The 8085 samples INTR one cycle later than the 8085A 



Acknowledged external 
device must select 
itself and provide 
the instruction object 
code before INTA goes 
high 



Figure 5-16. An Interrupt Being Acknowledged Using a Single Byte Instruction 

EXTERNAL INTERRUPTS 

There are some differences between the interrupt acknowledge logic of the 8085A as compared with the 
8080A; however, the 8080A interrupt acknowledge logic is a subset of 8085A capabilities. 

Providing a valid interrupt request has been applied and interrupts are enabled, the 8085A acknowledges the inter- 
rupt request on terminating execution of the current instruction. The 8085A then executes an interrupt 
acknowledge machine cycle. 

An interrupt acknowledge machine cycle is very similar to a six clock period instruction fetch machine cycle; however, 
during the interrupt acknowledge machine cycle the 8085A, like the 8080A, anticipates receiving an instruction object 
code from an I/O device — presumably the device whose interrupt request is being ackno wled ged. Since an I/O device 
j£Supposed to provide the object code during an interrupt acknowledge instruction fetch, INTA is pulsed low instead of 
RD. Timing is illustrated in Figure 5-16. 

Figure 5-16 shows two differences between the 8085A and the earlier 8085. the 8085A INTERRUPT 

samples INTR during the next-to-last clock period of eachjnstruction's execution, but the DIFFERENCES 

8085 samples INTR one clock period lajer. The level of lO/M during Interrupt Acknowledge IN 8085 AND 

is also different: the 8085A holds lO/M low at this time. 8085A 



5-28 



o 

CQ 
(0 
O 

< 
a 

< 



Note that even though memory is not being accessed. Program Counter contents are output _ 

on the Address Bus during an interrupt acknowledge instruction fetch; providing memory select logic uses lO/M 
and RD, no harm will be done by having a valid address on the Address Bus during an interrupt acknowledge in- 
struction fetch. 

The Program Counter contents are not incremented during the interrupt acknowledge process. 

The 8085A signal INTA serves as a read strobe during interrupt acknowledge. The 8085A 



8085A 

INTERRUPT 

ACKNOWLEDGE 



8085 

INTERRUPT 

ACKNOWLEDGE 



first acknowledges an interrupt with the state of S1, SO, and lO/M: in the 8085A these 
three status signals are all high during an interrupt acknowledge machine cycle. Recall that 
SI and SO both high signifies an instruction fetch, which is always a memory operation. 
Therefore, an "instruction fetch" which access I/O instead of memory is an interrupt acknowledge^ 

In the 8085, an earlier version of the 8085A, interrupt acknowledge has the same SI, S O, and 
lO/M levels as an instruction fetch. This means the interrupt acknowledge si gnal INTA 
serves both as an interrupt acknowledge and a read strobe. External logic must use INTA both 
as a device select signal and a strobe signal identifying the time interval during which the inter- 
rupt acknowledge instruction code must be placed on the Data Bus. This can cause a timing problem. For any other in- 
struction fetch, the trailing edge of ALE can be used to initiate device select timing; thus during any other instruction 
fetch you have from the middle of T1 until the middle of T2 to resolve the device select and wait for the read strobe. But 
you cannot use ALE in this fashion fol lowin g an interrupt acknowledge, since external logic does not know that the in- 
terrupt has been acknowledged until INTA goes low. On the trailing edge of ALE during an interrupt acknowledge in- 
struction fetch machine cycle, the Program C ounte r. contents are being output on the Address Bus even though this 
address is irrelevant. You must therefore use INTA as a signal which disables all I/O device select logic with the 
exception of the device whose interrupt request is being acknowledged. 



WAIT STATES 
DURING 8085 
INTERRUPT 
ACKNOWLEDGE 



If your system contains an 8085, rather than an 8085A, you may well have to insert Wait 
states during an interrupt acknowledge instructi on f etch machine cycle; the 

acknowledged external logic has the duration of the low INTA pulse within which it must 
resolve its select logic and place an instruction object code on the Data Bus. 

Earlier in this chapterwe showed you how you can create a one clock period low READY pulse 

using two 7474 D-type flip-flops. The circuit shown would generate the low READY pulse during a memory read or in- 
struction fetch. The same circuit will also cause a Wait state during an 8085 interrupt acknowledge, which is identical 
to an instruction fetch as far as our small circuit is concerned. 

You can respond to an interrupt acknowledge by transmitting any instruction object code to the 8085A. Usually 
a Restart (RST) or a Call instruction object code will be transmitted. 

Figure 5-16 illustrates timing for a Restart instruction being transmitted following an interrupt acknowledge. The 
Restart instruction has been described in detail in Chapter 4 together with circuits which allow a Restart instruction to 
be created. 

The 8085A contains internal logic to cope with multibyte instruction object codes transmit- 
ted during the i nterr upt acknowledge process. During the second and third instruction fetch 
machine cycles, INTA is pulsed low while lO/M is output high. Thus responding to an interrupt 
acknowledge with a Call instruction simply involves creating a Call instruction's object code. 

The earlier 8085 also handles multibyte instruction object codes during interrupt 
acknowledge. The second and thir d ackn owledge machine cycles are similar to memory read cy- 
cles, the only difference being that INTA pulses instead of RD. 



8085A 

MULTIBYTE 

ACKNOWLEDGE 



8085 

MULTIBYTE 

ACKNOWLEDGE 



The 8085A has four interrupt request pins which the 8080A does not have. These are TRAP, RST 5.5, RST 6.5 
and RST 7.5. Interrupts requested via these pins cause the 8085A to generate its own internal interrupt 
acknowledge instruction. 

The internal interrupt acknowledge instruction results in subroutine calls to the following addresses: 

Interrupt CALL Address 



TRAP 


2416 


RST 5.5 


2Ci6 


RST 6.5 


3416 


RST7.5 


3Ci6 



TRAP is a non-maskable interrupt. 

RST 5.5 and RST6.5 are level sensitive;that means a high level input at these pins generates an interrupt request. 



5-29 



RST 7.5 is edge sensitive: an interrupt request occurs when the input to RST 7.5 nnakes a low-to-high transition. 

TRAP is both level and edge sensitive; the low-to-high transition and the subsequent high level generate an inter- 
rupt request. 

If an interrupt request is generated at RST 7.5 by a low-to-high transition, the 8085A will remember the interrupt re- 
quest, whether or not the RST 7.5 input remains high. You can thus generate an interrupt request via RST 7.5 using 
a high pulse. 

Since you can request an interrupt via an RST 7.5 low-to-high transition, the RST 7.5 interrupt request signal it- 
self cannot reset the interrupt request. This may be illustrated as follows: 



RST 7.5 



y 



y 



Interrupt 
request 



New interrupt request 
only if previous 
request has been 
serviced 



You need not terminalte service of an RST 7.5 interrupt request by executing an SIM instruction with bit 4 of 
the Accumulator set to 1 ; the CPU does this automatically when it recognizes the interrupt. 

A low-to-high transition of the TRAP input creates an interrupt request. The interrupt request will only be 
acknowledged while the TRAP input remains high; however, once a TRAP interrupt request has been acknowledged, 
TRAP must go low and then high again before another interrupt request will be acknowledged. 





MCI 




T3 


Ti 


T2 


T3 


T4 


T5 


T6 


Ti 






















Figure 5-17. A Bus Idle Instruction Fetch Machine Cycle 



5-30 



o 

CD 
(A 
O 

:e 

< 

Q 
< 



8085A TRAP 
INTERRUPT 



8085A interrupt priorities are as follows: 

Highest HOLD 

TRAP 

RST 7.5 

RST6.5 

RST 5.5 
Lowest INTR 

The 8085A executes an instruction fetch Bus Idle machine cycle after acknowledging a TRAP, RST 5.5, RST 6.5 
or RST 7.5 interrupt request. Timing is given in Figure 5-17. 

The TRAP interrupt request cannot be disabled. In the 8085A, but not in the 8085, the TRAP 
interrupt preserves the state of the interrupt enable flag. This allows the user to restore the in- 
terrupt enable status after a TRAP interrupt. 

The RST 5.5, RST6.5, and RST 7.5 interrupt requests can be individually enabled and disabled using the SIM in- 
struction. All interrupts except the TRAP can be enabled and disabled via the EL and Dl instructions. 

You may at any time examine interrupt enable/disable status by executying the RIM instruction. 

In the 8085A, but not the earlier 8085, the first RIM instruction executed after a TRAP in- 
terrupt will show what the interrupt status was just before the TRAP, no matter how many 
lEs and DIs have been executed since the TRAP acknowledge. You must perform RIM after 
every TRAP to ensure that subsequent RIMs will provide accurate interrupt enable status. 

The RIM and SIM instructions are described in detail later in this chapter. 

You will service interrupts in an 8085A system exactly as described for the 8080A system. For a discussion of 
an interrupt acknowledge see Chapter 4. 

Remember that a Hold request has priority over an interrupt request. Thus, an interrupt will not be acknowledged 
while a Hold state exists and the 8085A will respond to a Hold request following an interrupt acknowledge. 



8085A RIM 
AFTER TRAP 



POWER SUPPLY 
OR SIGNAL 





Ml 




Ml 




'''reset 


T1 


T2 


"reset 


Treset Treset 


Tl 


T2 


POWER ON 



















+ 4.75V- 




A8-A15 



ADO - AD7 



•8085 floats ALE during Reset; 8085A does not do this. 



Figure 5-18. Power On and RESET IN Timing for the 8085A 



5-31 



THE RESET OPERATION 

You reset an 8085A by inputting a low signal via RESET IN. 



When power is first turned on, the RESET IN pulse m ust last at least 500 nanoseconds (3 full clock cycles); no 
further req uirements are imposed on the RESET IN signal. Logic internal to the 8085A will synchronize the 
RESET IN pulse with the internal clock. Timing for a Reset following a powerup is given in Figure 5-18. 

Notice that a RESET OUT signal is provided. You can use this signal to reset other devices in the 8085A 
microcomputer system. 

When the 8085A is reset the following events occur: 

1) The Program Counter is cleared; thus the first instruction executed following a reset must have its object code 
stored in memory location 0. 

2) The Instruction register is cleared. 

3) Interrupts are disabled. 

4) The RST 7.5, RST 6.5 and RST 5.5 interrupts are masked out and thus disabled. 

5) All tristate bus lines are floated. In the earlier 8085, ALE is tristate and thus floats during Reset. In the 8085A, ALE 
is not tristate. 

Table 5-1. A Summary of 8085A Instruction Object Codes and Execution Cycles 



INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK PERIODS 


8085A 
MACHINE CYCLES 


8080A 


8085A 


ACI 


DATA 


CE YY 


2 


7 


7 


1 3 


ADC 


REG 


10001XXX 


1 


4 


4 


1 


ADC 


M 


8E 


1 


7 


7 


1,3 


ADD 


REG 


10000XXX 


1 


4 


4 


1 


ADD 


M 


86 


1 


7 


7 


1 3 


ADI 


DATA 


C6 YY 


2 


7 


7 


1 3 


ANA 


REG 


10100XXX 


1 


4 


4 


1 


ANA 


M 


A6 


1 


7 


7 


1 3 


ANI 


DATA 


E6 YY 


2 


7 


7 


1 3 


CALL 


LABEL 


CD ppqq 


3 


17 


18 


2335S 


CC 


LABEL 


DC ppqq 


3 


11/17 


9/18 


23,2335S 


CM 


LABEL 


FC ppqq 


3 


11/17 


9/18 


23,23355 


CMA 




2F 


1 


4 


4 


1 


CMC 




3F 


1 


4 


4 


1 


CMP 


REG 


1011 IXXX 


1 


4 


4 


1 


CMP 


M 


BE 


1 


7 


7 


13 


CNC 


LABEL 


D4 ppqq 


3 


11/17 


9/18 


2 3. 2 3 3 5 5 


CNZ 


LABEL 


C4 ppqq 


3 


11/17 


9/18 


23,23355 


CP 


LABEL 


F4 ppqq 


3 


11/17 


9/18 


23,23355 


CPE 


LABEL 


EC ppqq 


3 


11/17 


9/18 


2 3, 2 3 3 5 5 


CPI 


DATA 


FE YY 


2 


7 


7 


13 


CPO 


LABEL 


E4 ppqq 


3 


n/17 


9/18 


23,23355 


CZ 


LABEL 


CC ppqq 


3 


11/17 


9/18 


23,23355 


DAA 




27 




4 


4 


1 


DAD 


RP 


00XX1001 




10 


10 


1 77 


DCR 


REG 


00XXX101 




5 


4 


1 


DCR 


M 


35 




10 


10 


135 


OCX 


RP 


00XX1011 




5 


6 


2 


Dl 




F3 




4 


4 


1 


El 




FB 




4 


4 


1 


HLT 




76 




4 


4 


1 


IN 


PORT 


DB YY 




10 


10 


1 34 


INR 


REG 


00XXX100 




llllllli 


lliiiill 


1 


INR 


M 


34 




10 


10 


135 


INX 


RP 


00XX0011 




llliiiil 


llllllli 


2 


JC 


LABEL 


DA ppqq 




lb 


7/10 


1 3, 1 3 3 


JM 


LABEL 


FA ppqq 




10 


7/10 


1 3, 1 3 3 


JMP 


LABEL 


C3 ppqq 




10 


10 


133 


JNC 


LABEL 


D2 ppqq 




10 


7/10 


1 3, 1 3 3 


JNZ 


LABEL 


C2 ppqq 


3 


10 


7/10 


1 3, 1 3 3 


JP 


LABEL 


F2 ppqq 


3 


10 


7/10 


1 3, 1 3 3 



5-32 



Table 5-1. A Summary of 8085A Instruction Object Codes and Execution Cycles 

(Continued) 



o 

m 

(A 

O 

< 
< 
@ 



INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK PERIODS 


8085A 
MACHINE CYCLES 


eoeoA 


8085A 


JPE 


LABEL 


EA ppqq 


3 


10 


7/10. 


1 3; 1 3 3 


JPO 


LABEL 


E2 ppqq 


3 


10 


7/10 


1 3, 1 3 3 


JZ 


LABEL 


CA ppqq 


3 


10 


7/10 


1 3, 1 3 3 


LDA 


ADOR 


3A ppqq 


3 


13 


13 


1333 


LDAX 


RP 


000X1010 


1 


7 


7 


1 3 


LHLD 


ADDR 


2A ppqq 


3 


16 


16 


13 3 3 3 


LXI 


RP.DATA16 


00XX0001 
YYYY 


3 


10 


10 


133 


MOV 


REG.REG 


Oldddsss 


1 


5 


4 


1 


MOV 


M.REG 


OinOsss 


1 


7 


7 


1 5 


MOV 


REG.M 


OldddllO 


1 


7 


7 


1 3 


MVI 


REG.DATA 


OOdddllO 
YY 


2 


7 


7 


1 3 


MVI 


M.DATA 


36 YY 


2 


10 


10 


135 


NOP 




00 


1 


4 


4 


1 


ORA 


REG 


10110XXX 


1 


lil5:ilil 


iiiSill 


iiiiliitlifliiilB^^^^ 


ORA 


M 


B6 


1 


7 


1 


13 


ORI 


DATA 


F6 YY 


2 


7 


7 


1 3 


OUT 


PORT 


D3 YY 


2 


10 


10 


136 


PCHL 




E9 


1 


5 


6 


Z 


POP 


RP 


11XX0001 


1 


10 


10 


1 33 


PUSH 


RP 


11XX0101 


1 


11 


12 


255 


RAL 




17 


1 


4 


4 


1 


RAR 




IF 


. 1 


4 


4 


i 


RC 




D8 


1 


5/11 


6/12 


2, 2 3 3 


RET 




C9 


1 


10 


10 


1 33 


RIM 




. , 20 


iBIIilt 




4 


1 


RLC 




07 


1 


4 


4 


1 


RM 




F8 


1 


5/11 


6/12 


2,2 33 


RNC 




DO 


1 


5/11 


6/12 


2,2 33 


RNZ 




CO 


1 


5/11 


6/12 


2,2 33 


RP 




FO 


1 


5/11 


6/12 


2.2 33 


RPE 




E8 


1 


5/11 


6/12 


2,2 33 


RPO 




EO 


1 


5/11 


6/12 


2,2 3 3 


RCC 




OF 


1 


4 


4 


1 


RST 


N 


11XXX111 


1 


11 


12 


233 


RZ 




C8 


1 


5/11 


6/12 


2.23 3 


SBB 


REG 


1001 1XXX 


1 


4 


4 


1 


SBB 


M 


9E 


I 


7 


7 


13 


SB! 


DATA 


DE YY 


2 


7 


7 


13 


SHLD 


ADDR 


22 ppqq 


3^_ _ 


16 


16 


13355 


SIM 




30 


■MmMiMsSi 




4 


t 


SPHL 




F9 


1 


5 


6 


2 


STA 


ADDR 


32 ppqq 


3 


13 


13 


13 3 5 


STAX 


RP 


000X0010 


1 


7 


7 


15 


STC 




37 


1 


4 


4 


1 


SUB 


REG 


10010XXX 


1 


4 


4 


1 


SUB 


M 


96 


1 


7 


7 


1 3 


SUI 


DATA 


D6 YY 


2 


7 


7 


1 3 


XCHG 




EB 


1 


4 


4 


1 


XRA 


REG 


10101XXX 


1 


4 


- 4 


1 


XRA 


M 


AE 


1 


7 


7 


1 3 


XRI 


DATA 


EE YY 


2 


7 


7 


13 


XTHL 


-■• . 


E3 


1 


18 


16 


13355 



ppqq represents four hexadecimal digit memorv address 

YY represents two hexadecimal data digits 

YYYY represents four hexadecimal data digits 

X represents an optional binary digit 

ddd represents optional binary digits identifying a destination register 

sss represents optional binary digits Identifying a source register 



Machine cycle types: 

1 - Four clock period Instruction fetch (Figure 5-4) 

2 - Six clock period instruction fetch (Figure 5-5) 

3 - Memory read (Figure 5-6) 

4 - I/O read (Figure 5-7) 

5 - Memory write (Figure 5-8) 

6 - I/O write (Figure 5-9) 

7 - Bus idle (Figure 5-10) 



5-33 



THE 8085A INSTRUCTION SET 



There are just three differences between the 8085A and the 8080A instruction sets: 

1) The 8085A has two additional instructions — RIM and SIM. 

2) The number of clock periods required to execute instructions differs in sonne cases; Table 5-1 summarizes these 
differences. 

3) Following a Halt instruction's execution, the 8085A floats tristate bus lines in the ensuing Halt state; the 8080A 
does not. 

Because the 8085A and 8080A instruction sets are so similar, the same benchmark program applies to both 
microprocessors. Refer to Chapter 4 for a discussion of this benchmark program. 

Refer to Table 4-4 for a summary of the 8085A instruction set. The only two 8085A instructions not present in 
Table 4-4 are the RIM and SIM instructions. 

When the RIM instruction is executed, the following data is loaded into the Accumulator; 



1 



RIM 



7 6 5 4 3 2 

II I ^ 



- Bit No. 

' This data is loaded into the Accumulator 



i ,\ li A <i il ; 



' RST 5.5 interrupt mask 
RST 6.5 interrupt mask 
' RST 7.5 interrupt mask 
' IVIaster interrupt enable 
■ RST 5.5 interrupt status " 
RST 6.5 interrupt status 
' RST 7.5 interrupt status , 
SID signal level 



= enabled 

1 = disabled 

1 = enabled 

= disabled 

1 = request pending 
= no request 



Thus, the RIM instruction allows you to examine interrupt and external status. 

When the SIM instruction is executed the contents of the Accumulator are interpreted as follows; 

7 6 5 4 3 2 1 -^ Bit No. 

I I I I I J I 1 1^ This data must already be in the Accumulator 



SIM 




}" 



= enable 
= disable 



RST 5.5 mask 
RST 6.5 mask 
RST 7.5 mask 

= ignore bits 0, 1 and 2 

1 = mask as per bits 0, 1 and 2 

1 = reset RST 7.5 latch so a leading edge will cause another 
interrupt request 

— disable serial data out 

1 — enable serial data out 

This bit is transmitted to SOD pin if bit 6 is 1 



Thus the SIM instruction is used to selectively mask interrupts and to output a control signal via the SOD pin. 

Note that if bit 6 of the Accumulator is when the SIM instruction is executed, then the contents of bit 7 will not be 
transferred to the SOD pin. 



5-34 



o 

ID 
CO 

o 

< 

Q 

< 

@ 



From our discussion of the 8085A reset, recall that following a reset RST 5.5, RST 6.5 and RST 7.5 are all disabled; also, 
reset sets the SOD output to 0. Thus, following a reset an RIM instruction would input the following data to the Ac- 
cumulator: 



RIM 



7 6 5 4.3210 -^- 

I I I I lo|i[i|i> — 




Bit No. 
' Data loaded to the Accumulator 

Mask 1 bits disable interrupts 
RST 7.5, RST 6.5 and RST 5.5 
Master interrupt is disabled 

These bits reflect the state of the 
RST 7.5, RST 6.5 and RST 5.5 inputs 

This bit reflects the SID signal level 

8085A MICROPROCESSOR SUPPORT DEVICES 

The 8085 has four special purpose multifunction support devices; they are described in this chapter. 

The 8085A can use any -5 version of the 8080A support devices described in Chapter 4 and Volume III. If you 
Use the low-order eight 8085A address lines, you miist demultiplex the 8085A Address and Data Busses to use 
8080A support devices. 

THE 8155/8156 STATIC READ/WRITE MEMORY 
WITH I/O PORTS AND TIMER 



The 8155 and 8156 are custom circuits designed specifically for the 8085A microprocessor. Each device pro- 
vides 256 bytes of static read/write memory, two or three parallel I/O ports, and a programmable timer. The 
8155 and 8156 devices differ only in the active level of the chip enable signal. 

Figure 5-lSi illustrates that p^rt of general microcomputer system logic which has been implemented on the 
8155 /8156 devices. 

Figure 5-20 provides a functional diagram of 8155/8156 logic. 

The 8155 or 8156 device is packaged as a 40-pin DIP. It uses a single +5V power supply. All inputs and outputs 
are TTL compatible. 

81 55/81 56 DEVICE PINS AND SIGNALS 

8155/8156 pins and signals are illustrated in Figure 5-21. Signals may be divided into the following categories: 

1) CPU interface and control 

2) Parallel I/O 

3) Programmable Timer 

We will first consider CPU interface and control signals. 

ADO - AD7 connect to a bidirectional, multiplexed Data and Address Bus. As illustrated in Figure 5-22, these pins 
connect to the ADO - AD7 bus lines QutJDut by the 8085A microprocessor. 

ALE is the Address Latch Enable control signal output by the 8085A microprocessor to identify addresses on the 
multiplexed Data and Address Bus. 

The 8155 or 8156 has both a memory space and an I/O address space. When lO/M is high, I/O port addresses are 
decoded off ADO - AD7 on the high-to-low transition of ALE; this may be illustrated as follows: 



ADO - AD7 



ALE 



I 



lO/M 




I/O Port Address 



5-35 



Logic to Handle 
Intef-Fupt Requests 

^ from 
External Devices 



Clock Logic 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Interrupt Prioflty 
Arbitration 



Bus Interface 
Logic 



Accumulator 
Register<s) 



Data CounteKs) 



Stack Pointer 



Program Counter 



System Bus 



L_ "_J 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 

Interface Logic 



I 



I/O Ports 
Interface Logic 



Read Only 
Memory 



1/0 Ports 



Direct Memory 

Access Control 

Logic 



RAM Addressing 

and 
Interface Logic 



Read/Write 
Memory 



Figure 5-19. Logic of the 8155 and 8156 Multifunction Devices 

When lO/M is low, the address strobed off ADO - AD? is interpreted as a memory address. 

CE is active high ih the 81 56 device; it is active low in the 81 55. There is no other difference between the 81 55 
and 8156 devices. 

The 8155 or_8156 device uses standard 8085A control signals on its CPU interface. These signals are RD, WR, 
ALE and lO/M. Refer to the description of these control signals given in the 8085A section of this chapter. 



5-36 



lO/M 



O 
< 

o 

< 

@ 



ADO - AD7 

■CE(8155)orCE(8156) 

A_LE 

RD 

WR 

RESET 

TIMER IN 



C=^ 



256x8 

STATIC 

RAM 




TIMER 



B 
10 



TIMER OUT ■^- 



I 



T 



PORTA 



■> 



PAO - PA7 



PBO - PB7 



ji PORT B ,. 

CO 

-PORTCj. 



PC7 



Vcc I + 5V) 
Vss (OV) 



Figure 5-20. Logic Functions of the 8155/8156 Device 




PIN NAME 

ADO - AD7 

PAO - PA7 

PBO - PB7 

PC0-PC5 

RD 

WR 

lO/M 

ALE 

RESET 

ce/ce" 

TIMER IN 
TIMER OUT 
^SS ^CC 



DESCRIPTION TYPE 

Multiplexed Address and Data Bus - Bidirectional 

Eight I/O pins, designated as Port A Bidirectional 

Eight I/O pins, designated as Port B Bidirectional 

Six I/O pins, designated as Port C Bidirectional 

Read from device control Input 

Write to device control Input 

I/O pons or memory select Input 

Address latch enable Input 

System reset Input 

Chip enable Input 

Timer clock Input 

Timer output signal Output 
Ground, Power 



Figure 5-21. 8155/8156 Multifunction Device Signals and Pin Assignments 



5-37 



CLK 



8085 



ALE 

RD 

WR 

lO/M 

RESET OUT 




A8-A15 



-O>0- 



Device 
Select 
Logic 



c 



ADO - AD7 



:> 



CE 



8155 



ALE 

RD 

WR_ 

lO/M 

RESET 



TIMER IN 



TIMER OUT 



Q.PA0-PA7^ 
^PC0-PC5N 



Figure 5-22., An 8155 Device Connected to an 808^A CPU Bus 





Table 5-2. 8155/8156 Device Port C Pin 


Options 


Pin 


ALT 1 


ALT 2 


ALT 3 


ij ALT 4 


PCO 


Input Port 


Output Port 


A INTR (Port A Interrupt) 


A INTR (Port A Interrupt) 


PCI 


Input Port 


Output Port 


A BF (Port A Buffer Full) 


A BF (Port A Buffer Full) 


PC2 


Input Port 


Output Port 


A STB (Port A Strobe) 


A STB (Port A Strobe) 


PC3 


Input Port 


Output Port 


Output Port 


B irJTR (Port B Interrupt) 


PC4 


Input Port 


Output Port 


Output Port 


B BF (Port B Buffer Full) 


PCS 


Input Port 


Output Port 


Output Port 


B STB (Port B Strobe) 



8155 

DEVICE 

RESET 



Tine 8155/8156 device is reset by a iiigii input at the RESET pin. The Reset operation does not 
clear memory or I/O locations within. the 8155/8156 device. Thus all mennorY locations con- 
tain zero, I/O ports are assigned to input mode and the Counter/Timer is stopped with an initial 
zero value. 

8155/8156 PARALLEL INPUT/OUTPUT 

The interface presented by the 8155/8156 device to external logic consists of three I/O ports and two signals 
associated with Counter/Timer Ib^ic. 

We will examine the I/O port logic and then the Counter/Timer logic. 

I/O Ports A and B are 8-bit parallel ports; each may be defined as an input port or an output port. 

I/O Port C is a 6-bit parallel I/O port; it may be used to input or output parallel data, or Port C pins may support 
handshaking control signals for Ports A and B. Table 5-2 defines the four ways in which I/O Port C m ay be used. 

When I/O Ports A and B are used for simple parallel input or output, then their operation is 
identical to Mode as described in Chapter 4 for the 8255 PPI. Handshaking mode is identi- 
cal to 8255 Mode 1. We will therefore discuss 8155 input and output with handshaking briefly. 
For a more detailed discussion refer to the 8255 PPI description given in Volume III. 



8155/8156 I/O 
MODE 



8155/8156 1/0 
MODE 1 



5-38 



Input with handshaking may be illustrated as follows: 



BF 



STROBE 



INTR 



=d 



S 



RD 




An event sequenc e begins with external logic inputting parallel data to I/O Port A or B; external 

logic must pulse STROBE low, at which time the parallel data is loaded into the I/O port buffer. This causes BF, 

the Buffer Full signal, to go high. 

External logic uses the BF signal as an indicator that no more data can be written. 



g As soon as the externally provided low STROBE pulse is over, the interrupt request signal INTR goes high. This allows 

m the 8085A to be interrupted once data has been loaded into the input buffer of the I/O port. 

° ^ and INTR remain high until the CPU reads the contents of the I/O port. The read operation will be identified by a low 

< RD pulse input to the 8155/8156 device. INTR is reset at the beginning of the RD'pulse, while BF is reset at the end of 

5 the RD pulse. BF therefore is high while data is waiting to be read and while data is being loaded into the I/O port buffer 

/Q) or read out of the I/O port buffer. INTR is high only while data is waiting to be read. 

BF and INTR have associated bits in the Status register of the 8155/8156 device. 

You connect INTR to an 8085A interrupt request if you want an interrupt-driven system. You write a program 
which polls the Status register of the 8155/8156 if you want to operate the system under program control. 

Strobed output timing may be illustrated as follows: 




In output mode the I/O port buffer is initially empty, which means that the CPU must transmit data to the I/O port. 
Therefore INTR is initially high. 

As soon as the CPU writes data to the I/O port, the inte rrupt request signal INTR is reset low; this occurs on the leading 
edge of the WR pulse. On the trailing edge of the WR pulse BF is output high, telling external logic that data is in 
the I/O port buffer and may be read. 



External logic strobes the da ta out b y providing a low pulse at STROBE. The leading edge of STROBE resets BF 
low, while the trailing edge of STROBE sets INTR high, causing the CPU to again output parallel data. 

You connect INTR to an appropriate 8085A interrupt request pin if you want an interrupt-driven system. You 
write a program to poll the Status register if you want to operate the 8155/8156 under program control. 

A simple method of using the 8155/8,156 device parallel input/output with handshaking in interrupt mode would be to 
connect INTRA and INTRB to RST 5.5 and RST 6.5. 

8155/8156 DEVICE ADDRESSING 

Having discussed 8155/8156 device memory and I/O ports, we must now look at device addressing. 

The 8155/8156 has 256 bytes of static read/write memory which are addressed by ADO - AD7 while Chip Enable is 
true, and lO/M =0. 



5-39 



The 8155/8156 has eight addressable I/O ports. ADO, AD1 and AD2 select I/O ports while Chip 
Enable is true and lO/M = 1. These are the eight addressable I/O ports: 



AD2 


AD1 


ADO 


PORT 











Status/Connmand registers 








1 


Port A 





1 





Port B 





1 


1 


Port C 


1 








Counter/Timer register, low-order byte 


1 





1 


Counter/Timer register, high-order byte 


1 


1 





Unused 


1 


1 


1 


Unused 



8155/8156 
I/O PORT 
ADDRESSES 



Chip Enable is derived from A8 - A1 5, which holds the high-order byte of a memory address, or the I/O device number. 
Chip Enable thus defines the exact address and I/O space for the 8155/8156 device. Here is one possible con- 
figuration: , 




|0|l|l|0|0|n|n|n|x[x|x|x|x|x|x|xji ^ Valid memory addresses 




ADO - AD7, X can be or 1 

These bits are ignored. They may have 
any value. 



81 55/81 56 memory bytes will be selected by any memory addresses in the range 6n00i q through 6nFF-| q. "n" repre- 
sents any digit in the range through 7. Let us assume that programs access 8155/8156 memory bytes via addresses 
in the range 6OOO16 through 6OFF16; we must further assume that addresses created by values of n in the range 1 
through 7 never occur. 

Now the same chip select that you use to define your memory address space is also going to define your I/O ad- 
dress space. Recall that the 8-bit I/O device number is output twice following execution of an I/O instruction — once 
on the high-order eight address lines A8 - A1 5 and again on the low-order Address/Data Bus lines ADO - AD7. Thus the 
device select code which you generate from the eight high-order address lines for a memory address is the same device 
select code which you generate for the 8155/8156 I/O space. 



5-40 



But whereas the 8155/8156 has 256 addressable memory locations, it has eight addressable I/O ports; I/O ports 
selected as follows: 



z 

DC 

o 

CO 
(0 

o 

< 
o 

< 




Bit No.. 

I/O Port Number 



If Chip Enable is true when A15 - A1 1 is 01 IOO2, then I/O port addresses will be 6O16 through 67i6- 

Address lines A15 - A1 1 represent I/O device number bits 7 through 3. This is because the I/O device number is output 
on A15-A8 following execution of an I/O instruction, it is therefore fortunate that we only used address lines 
A15 - A1 1 to create Chip Enable. Had we used AS, A9 or A10, the low-order three I/O device code bits would have 
served a double purpose — with strange results. 

Suppose A10 = is a prerequisite for device select logic to be true; these are the memory and I/O port selects which 
will result: 



Memory 
Address 



I/O Port 
Address 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 76543210- 
|0h |l |0|0|0|n|n|x|x |x |x |x|x|x|xH0|l jl |0|0|0|x |x| 



> Bit No. 




You can now address only four of the eight 8155/8156 I/O Ports. You cannot include address lines A8, A9 or 
A10 in the device select logic that you use for any 8155/8156 device; if you do, you will limit the I/O 
capabilities of the device. 

lO/M discriminates between exectuion of I/O instructions and memory reference instructions. 

THE 8155/8156 COUNTER/TIMER 

Counter/Timer logic consists of a 16-bit register, addressed as two 8-bit I/O ports, an input clock signal and an 
output timer signal. This may be illustrated as follows: 




Initial Timer constant 
Timer mode 



5-41 



The low-order 14 bits of the CounterA'imer register must be initialized with a 14-bit binary value that will 
decrement on low-to-high transitions of TIMER IN. If TIMER IN is connected to the 8085A clock output signal CLK, 
then the tinner is computing real time. TIMER IN can alternatively be connected to any external logic in which case the 
timer is counting external events. 

The timer times out when it decrements to zero. 

The two high-order bits of the Counter/Timer register define one of four ways in which the TIMER OUT signal 
may be created. 

In Mode 0, TIMER OUT is high for the first half of the time interval and \ow for the second half of 
the time interval. This may be illustrated as follows: 



8155/8156 

TIMER 

MODEO 



TIMER IN 



TIMER OUT j I 



Timer —J 
Initial count 
is N 




START 



STOP 



If N is odd, the extra pulse will occur while TIMER OUT is high. 



In Mode 1. as in Mode 0, TIMER OUT is high for the first half of the count and low for the second half. However, the 
timer is automatically reloaded with the initial value following each time out, creating a square wave which may be il- 
lustrated as follows: 



TIMER OUT 



Timer initial 
count is N 



Reload N Reload N 



V 



START 

Mode 2 outputs a single low clock pulse on the terminal count, then stops the timer. Timing may be illustrated as 
follows: 



TIMER IN 




START 



STOP 



Mode 3 is identical to Mode 2, except that when the timer times out the initial counter value is automatically reloaded. 



5-42 



< 
o 

< 

@ 



8155/8156 CONTROL AND STATUS REGISTERS 

The Control and Status registers of the 8155/8156 are used to control both timer and parallel I/O logic. Let us 
now examine these registers. 

The Control and Status registers of the 8155/8156 device are accessed via a single I/O port address. This is the 
lowest of the 8155/8156 I/O port addresses. When you write to this address you access the Control register; 
when you read from this address you access the Status register. 

8155/8156 internal logic will interpret Control register bits as follows: 



7 6 5 

cm 



4 3 2 



I li 



1 0- 



• Bit No. 

■ Control register 

• Port A definition 

■ Port B definition 
Port C definition 

00 = ALT 1 

01 =ALT3 

10 = ALT 4 

1 1 = ALT 2 

•Port A interrupts 

• Port' B interrupts 



= Input 

1 = Output 



See Table 5-2 



- Disable 

1 = Enable 



(Timer control 
00 = No effect on timer 
-^ 01 = Stop timer immediately, if running 
I 10 = Stop timer after next time out, if running 
I 1 1 = Start timer immediately 



Status register bits are set and reset as follows: 



7 6 

n 



5 4 3 2 



n ii II ii ii Ik 



1 0- 

n- 



Bit No. 

— Status register 

.^ Port A interrupt request 

— Port A buffer full 

— Port A interrupt enabled 1 ■) = jrue 

— Port B interrupt request / = False 

— Port B buffer full 

— Port B interrupt enabled 
—Timer interrupt. Set to 1 on time out, reset to when 

Status register is read or a new count is started 

8155/8156 DEVICE PROGRAMMING 

Accessing 8155/8156 read/write memory is self-evident. If you execute a memory reference instruction that 
specifies an address within the 8155/8156 address space, you will access an 8155/8156 memory byte. 

Parallel I/O programming is also self-evident; you begin by outputting an appropriate code to the Control register jn 
order to define the modes in which various ports will operate, and to enable or disable Mode 1 interrupts. Your only 
caution at this time must be to ensure that the two high-order bits of the Control code are 0; this prevents initiation of 
any timer operations. , 

If you are using I/O ports without handshaking, the Status register is not affected by I/O operations. No control 
signals or status indicate that new data has been input to, or has been read from I/O ports. 

If you are operating the 81 55/81 56 in handshaking mode under program control, then you must poll the Status register 
in order to determine whether data is waiting to be read or must be written. Your program will consist of a series of in- 
put instructions which read status, followed by conditional branches that read or write data. 



5-43 



If you are operating the 8155/8156 parallel I/O in handshaking mode under interrupt control, then whenever data is 
waiting to be read or must be written, the high INTR control signal will vector program execution to an appropriate in- 
terrupt service routine. 

You can at any time read the contents of an I/O port that has been declared an output port. You will simply read 
back whatever data was most recently written out to that I/O port Reading the contents of an output port will have no 
effect on handshaking control signals associated with that port. 

Let us now examine programming associated with 8155/8156 Counter/Timer logic. 

You must first initialize the 1 6-bit Counter/Timer register by outputting two bytes that specify timer mode and initial 
count. The order in which you output these two bytes is unimportant. 

Next you output an appropriate Control code in order to start the timer. When you output a Control code, remember not 
to modify any control bits that define parallel I/O operations. 

Here is an appropriate initialization instruction sequence: 



MVI 
OUT 
MVI 
OUT 
MVI 
OUT 



A,80H 

0C4H 

A,60H 

0C5H 

A,OFAH 

OCOH 



LOAD 6080H AS AN INITIAL COUNTER 
VALUE. SELECT COUNTER MODE 1 



START TIMER 



This instruction sequence assumes that the 8155/8156 I/O port addresses are C0-|6 through C5i6. The code FAiq 
output to the Control register starts the timer, and defines Port A as an input port. Port B as an output port, both in 
handshaking mode with interrupts enabled. 

You can at any time stop the counter, either immediately or following the next time-out. The following instructions will 
stop the counter immediately: 

STOP THE TIMER IMMEDIATELY 



MVI 
OUT 



A,7AH 
COH 



The following instructions will stop the counter after the next time-out: 

MVI A,BAH STOP THE TIMER AFTER THE 

OUT COH NEXT TIME OUT 

The Counter/Timer instruction sequences illustrated above contain a nonobvious propensity for programming 
errors. We start the timer by outputting the code FA-| q to the Control register; we stop immediately by outputting the 
code 7A-| 5 and we stop the timer after the next time-out by outputting the code BA-| 5. In reality, this is the code we are 
outputting: 



7 6 5 4 3 2 1 0- 

I I I'lihiohlol 




Bit No. 



Port A input 

Port B output 

Port C ALT 4 

Enable Ports A and B interrupts 

Timer code: 

1 1 = Start immediately 

Stop after next time out 



01 = Stop immediately 



Whenever you output Control codes to modify 81 55/81 56 timer operation, you must always remember to output bits 
through 5 correctly, in order to maintain previously defined parallel I/O options. A commonly used programming 
technique that frees you from having to remember the condition of irrelevant bits in a control word is to use 
AND and OR masks. Consider this general purpose instruction sequence: 

IN COH INPUT PRESENT CONTROL CODE 

ANI 3FH CLEAR TIMER BITS 

(ORI COH SET TIMER BITS) 

OUT COH RESTORE CONTROL CODE 



5-44 



This technique will not work with the 8155/8156 device, since you cannot read the contents of the Control 
register. If you read from the address of the Control register, you will access the Status rejgister. If you want to 
use a masking technique, you must maintain the Control code in memory. Here is an instruction sequence that will 
work: 

LOAD CONTROL CODE FROM MEMORY 

CLEAR TIMER BITS 

SET TIMER BITS) 

E OUT COH OUTPUT CONTROL CODE TO 8155/8156 

o 



o 



z 



z 



LDA 


CONTRL 


ANI 


3FH 


(ORI 


COH 


OUT 


COH 


STA 


CONTRL 



SAVE CONTROL CODE IN MEMORY. 



o Your instruction sequence will include the ANI mask to clear timer bits, or the ORI mask to set timer bits, but obviously 



not both. . , 

CONTRL is the label for some read/write memory byte which always holds the current 8155/8156 Control code. 

THE 8355 READ ONLY MEMORY WITH I/O 



The 8355 provides 2048 bytes of read-only memory and two 8-bit I/O ports. The device has been designed to 

c interface with the 8085A CPU. 

o 

^ Figure 5-23 illustrates that part of our general microcomputer system logic which has been implemented on the 

° 8355 device. 

5 

< The 8355 is packaged as a 40-pin DIP. It uses a single -I-5V power supply. All inputs and outputs are TTL-com- 

< patible. The device is implemented using N-channel MOS technology. 

® Figure 5-24 functionally illustrates logic of the 8355 device. A simple 8085A-81 55/81 56-8355 configuration is 

illustrated in Figure 5-26. 

There are many similarities between the 8155/8156, which we have already described, and the 8355. Where 
appropriate we will refer back to the 8155/8156 discussion for clarification of concepts. 

8355 DEVICE PINS AND SIGNALS 

8355 pins and signals are illustrated in Figure 5-25. 

The 8355-8085A interface differs somewhat from the 81 55/81 56-8085A interface in that the 8355 has more 
memory, fewer addressable I/O ports, plus the ability to address 1/0 ports within the memory space of the 
device. 

Having 2048 bytes of addressable read-only memory, the 8355 requires eleven address pins. These are derived 
from AD0-AD7 and A8-A10. 

Having only four addressable I/O ports, the 8355 I/O address logic decodes ADO and AD1 only. I/O ports are selected 
as follows: 



AD1 


ADO 










I/O PORT A 





1 


I/O PORT B 


1 
1 




1 


DATA DIRECTION REGISTER A 
DATA DIRECTION REGISTER B 



5-45 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Arithnnetic and 
Logic Unit 



Instruction Register 



Control Unit 



Interrupt Priority 
Arbitration 



Bus Interface 
Logic 



Accumulator 
Register<s) 



Data CounteKs) 



Stack Pointer 



Program Counter 



; Direct Memory 

Access Control 

Logic 



System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 
Interface Logic 



I/O Ports 
Interface Logic 



Read Only 
Memory 



I/O Ports 



I 



RAM Addressing 

and 
Interface Logic 



Read/Write 
Memory 



Figure 5-23. Logic of the 8355 and 8755 Multifunction Devices 



5-46 



o 
ffi 

(0 

o 

< 

< 



CLK 



READY -^ 



ADO - AD7 



A8-A10 



CE 

CE 

lO/M 

RD 

low 

RESET 
lOR 



CO 



2Kx8 
ROM 



PORTA 

8 ^ PAO - PA7 



CO 



PORTB 

8 > PBO - PB7 



CO 



Vgs (OV) 



Figure 5-24. Logic Functions of the 8355 Device 



8355 device select logic must generate the chip enable signals CE and CE from thie five address lines A1 1-A15. 
The discussion of select logic given for the 8155/8156 device applies also to the 8355. 

If you select 8355 memory and I/O ports in their respective address spaces, the control signals ALE. RD, and 
lO/M are used exactly as described for the 8155/8156 device. 

But you can also access 8355 I/O ports within the 8355 memory space using control signals lOW and lOR. 

low and lOR are control signals which override lO/M and RD when accessing I/O ports. 

Providing CE and CE are true, a low input on IOW_will cause data on the Data Bus to be written into the I/O port 
selected by ADO and AD1, irrespective of the lO/M level. Similarly, lOR low will cause the contents of the I/O port 
selected by ADO and AD1 to be output on the Data Bus. 

You can connect lOW directly to the WR control signal, and thus write into the four I/O ports of the 8355 device as 
though they were the four low-or der memory bytes. But connecting lOR to RD is not so straightforward. The 8355 
device may receive a low input on lOR, together with low inputs on RD and lO/M; it will then attempt to read the con- 
tents of a read only memory byte and an I/O port at the same time. While elaborate schemes could be devise d for 
generating separate selects that map the four I/O ports in to a memory space of its own, it is wisest to ignore the lOR 
signal if you are using 8355 memo ry a nd I/ O log ic. Use lOR only when the 8355 is configured as two I/O ports — 
and the 8355 memory is unused. lOR and lOW are used in 8048 microcomputer systems; that is the principal 
reason they were designed into the 8355 device. 



5-47 




PIN NAME 

ADO - AD7 
A8-A10 
PAO - PA7 
PBO - PB7 
RD 
lOR 

iow 

lO/M 

ALE 

RESET 

CE,CE 

READY 

CLK 

Vss- Vcc 



DESCRIPTION TYPE 

Multiplexed Address and Data Bus Bidirectional 

Memory Address Lines Input 

Eight I/O pins, designated as Port A Bidirectional 

Eight I/O pins, designated as Port D Bidirectional 

Read from device control Input 

Read from I/O port control Input 

Write to I/O port control Input 

I/O ports or memory select Input 

Address latch enable Input 

System reset Input 

Chip enables Input 

Wait state request Output, tristate 

Timing for Walt state request Input 

Ground, Power 



Figure 5-25. 8355 Multifunction Device Signals and Pin Assignments 




•Complexity of device select logic depends on 
the number of devices in the system. 



Figure 5-26. An 8085A-81 55/81 56-8355 Microcomputer System 



5-48 



o 

a 

(A 

o 

< 

Q 
< 



8355 READY LOGIC 

The 8355 device has on-chip logic to create a READY signal that will insert one Wait state into the 8085A 
machine cycle that references the 8355 device. 8355 READY signal timing may be illustrated as follows: 



CLK 



CE-CE 



ALE 



READY 



MCI 




Tl 


T2 


Tw 


T3 


T4 


Tl 




. 










i 1 L A " 1 




\ r ■" 


1 1 


I r' 




The READY output is floated by the 8355 device while CE'CE is false. 

READY js forced low by the combination of Chip Enable true while ALE is high; READY stays low until the first low-to- 
high transition of CLK following the end of the ALE pulse. If you refer back to Figure 5-1 1, you will see that this READY 
logic creates a single Wait state. 

The problem with the READY logic illustrated above is that in order to have Chip Enable true while ALE is high, chip 
enable logic must be tied directly to Address Bus lines. Refer to the timing diagram below and you will see that AO- 
A15 is stable while ALE is high. 

But as we discussed earlier in this chapter, you can derive chip enable logic directly from A8-A15 only in small 8085 
microcomputer systems. When a large number of support devices are connected to the System Bus, you must 
guarantee against spurious device selects by including control signals in the chip enable logic. Logic illustrated earlier 
in this chapter shows h ow to create a chip select signal that is true between the trailing edge of ALE and the low-to- 
high transition of RD or WR. The following chip enable timing results: 



CLK 



A8-A15 



Tl 



T2 



T3 



\ I — u-y — L_j — ^ / — \ / 




5-49 



Tinning illustrated above is theoretically the best guarantee against spurious selects; but it will not work if you want to 
create a single Wait state when using an 8355 device. If Chip Enable (CE) goes true on the trailing edge of ALE, READY 
will never be reset low: 



CLK 



ALE 



CE-CE 



RD or WR 



READY 



A 



Tl 



& 



MCI 



T2 



T3 



^ 



T4 




You can resolve this problem by simply inverting ALE as a clock input to the select logic flip-flop. 

But when do you need to induce a Wait state? 

8355 device timing is fast enough to respond to memory and I/O accesses without the inclusion of a Wait state, unless 
you have buffers on the System Bus and the buffers introduce unacceptably long response delays. Therefore, ignore 
the READY signal logic of the 8355 in small 8085A systems and derive chip enable logic directly from the high-order 
address lines A1 1-A15. In larger systems where buffers on the System Bus force the 8355 device to require a Wait 
state, use READY logic of the 8355 device. 

8355 I/O LOGIC 

Let us now lool< at the I/O logic of the 8355 device. This device has two I/O ports whose pins can be individually 
assigned to input or output. This assignment is made by loading appropriate Control codes into a Data Direction 
register associated with each I/O port. A 1 in any bit position of the Data Direction register defines the associated I/O 
port pin as an output pin. A in any bit position defines the associated I/O port pin as an input pin. Thjs may be illustr- 
ated as follows: 



Data Direction 

Register A 

(Port 2) 



I/O Port A 
(Port 0) 



1 



* 

i* 

i« 

» 

* 

» 

^ 

^ 



Data Direction 

Register B 

(Port 3) 




I/O Port B 
(Port 1) 




1 






^- 


1 








1 













■^ 


1 

















1 








1 




-^ 


'^ 



Observe that the 8355 has no I/O with handshaking. For I/O with handshaking you should use the 8155/8156 or the 
8255 devices. 



5-50 



THE 8755A ERASABLE PROGRAMMABLE READ 
ONLY MEMORY WITH I/O 



o 
m 

V) 

O 

< 
o 
< 



8755 AND 
8755A 



The 8755A device provides 2048 bytes of erasable programmable read-only memory and two 8-bit I/O ports. 
The only difference between this device and the 8355, which we have just described, is the fact that the 
8755A read-only memory is programmable and erasable. There are minor pin and signal variations supporting 
the EPROM. These differences are identified in Figure 5-27. 

The 8755A is a new version of an earlier device, the 8755. The only difference between the 
two is the level of Vqq during normal read operations: -f-5V on the current 8755A, but OV 
on the earlier 8755. 

This discussion of the 8755A device is limited to describing how you program the read-only memory. In all other ways, 
the 8755A device is identical to the 8355. 

There are two Chip Enable signals on the 8755A device; CE is the standard chip enable, which must be true when the 
8755 device is being accessed for any purpose, either in normal operation or when programming the read-only memo- 
ry. CE is a high true signal. 

The second Chip Enable signal, CE/PROG, is first held low, then is pulsed true only when you are programming the 
read-only memory. You must apply a +25V pulse lasting between 50 and 1 00 milliseconds, beginning with the leading 
edge of ALE. At this time, data will be written into the addressed read-only memory location. Timing may be illustrated 
as follows: 



ADO - AD7 




READY 



You erase the programmable read-only memory by exposing it to ultraviolet light for a minimum of twenty minutes. 



5-51 




8755A 




Vcc( + 5V) 

PB7 

PB6 

PB5 

PB4 

PB3 

PB2 

PB1 

TOO 

PA7 

PA6 

PAS 

PA4 

PA3 

PA2 

PA1 

PAO 

A10 

A9 

A8 



PIN NAME 

ADO - ADS 
A8-A10 
PAO - PA7 
PBO - PB7 
RD 
lOR 

low 

lO/M 

ALE 

RESET 

CE 

PROG AND CE 

READY 

CLK 

Vdd 



'ss- ^cc 



DESCRIPTION TYPE 

Multiplexed Address and Data Bus Bidirectional 
Memory address lines Input 
Eight I/O pins, designated as Port A Bidirectional 
Eight I/O pins, designated as Port B Bidirectional 
Read from device control Input 
Read from I/O port control Input 
Write to I/O port control Input 
I/O pons or memory select Input- 
Address latch enable Input 
System reset Input 
Chip enable Input 
PROM programming chip enable Input 
Wait state request Output, tristate 
Timing for Wait state request Input 
Programming voltage: 

+ 25V to program 

+ 5V in normal read operation* 
Ground, Power 



*Vdd '^ OV in earlier 8755 read mode 



Figure 5-27. 8755A Multifunction Device Signals and Pin Assignments 



5-52 



DATA SHEETS 

This section contains specific electrical and timing data for the following devices: 

. 8085A CPU 

Q .8155/8156 RAM/10 

|Ii . 8355 ROM/10 

^ . 8755A EPROM/IO 

o 

a. 

cc 
o 
o 

z 

w 

UJ 

5 



< 
o 
< 

@ 



5-D1 



8085A 

ABSOLUTE MAXIMUM RATINGS' 



Ambient Temperature Under Bias C to 70 C 

Storage Temperature — 65°C to +150 C 

Voltage on Any Pin 

With Respect to Ground .- 0.5 to + 7V 

Power Dissipation 1.5 Watt 

D.C. CHARACTERISTICS 

(Ty^ = 0°C to 70°C; V^c = 5V ±5%; Vgs = OV; unless otherwise specified) 



*COMMENT: Stresses above those tist6d urnJer "Absolute 
Maximum Ratings" may cause permanent damage tp the 
device. This is a stress rating only and functional Cfi$ra- 
tion of the device at these or any other conditions abdvf} 
those indicated in the operational sections of this specif J' , 
cation is not implied. Exposure to absolute maximum, 
rating conditions for extended periods may affect device 
reliability. 



Symbol 


Parameter 


Mln. 


Max. 


Units 


Test Conditions 


V,L 


Input Low Voltage 


-0.5 


+0.8 


V 




V,H 


Input High Voltage 


2.0 


Vcc+0.5 


V 




Vol 


Output Low Voltage 




0.45 


V 


loL = 2mA 


VOH 


Output High Voltage 


2.4 




V 


'oh = -400m A 


'cc 


Power Supply Current 




170 


mA 




'IL 


Input Leakage 




±10 


ma 


Vin=Vcc 


Ilo 


Output Leakage 




±10 


ma 


0.45V < Vout < Vcc 


ViLR 


Input Low Level, RESET 


-0.5 


+0.8 


V 




V|HR 


Input High Level, RESET 


2.4 


Vcc+0.5 


V 




Vhy 


Hysteresis, RESET 


0.25 




• V 






TIMING CH 


lARACTEF 


nsTics 







Bus Timing Specification as a Tcyc Dependent 



^AL 


- (1/2) T- 50 


MIN 


*LA 


- (1/2) T- 60 


MIN 


*LL 


- (1/2) T- 20 


IVIIN 


^LCK 


(1/2) T- 60 


MIN 


^LC 


(1/2) T- 30 


MIN 


Ud 


(5/2 + N) T - 225 


MAX 


^RD 


- (3/2 + N)T-180 


MAX 


^RAE 


(1/2) T- 10 


MIN 


*CA 


- (1/2) T- 40 


MIN 


^DW 


(3/2 + N) T - 60 


MIN 


%D 


- (1/2) T- 60 


MIN 


^CC 


(3/2 + N) T - 80 


MIN 


*CL 


- (1/2) T- 110 


MIN 


*ARY 


(3/2) T - 260 


MAX 


^HACK 


- (1/2) T- 50 


MIN 


^HABF 


(1/2) T + 50 


MAX 


^HABE 


(1/2)T + 50 


MAX 


^AC 


- (2/2) T - 50 


MIN 


*1 


(1/2) T- 80 


MIN 


^2 


- (1/2) T- 40 


MIN 


^RV 


- (3/2) T- 80 


MIN 



NOTE: N is 
T = 



equal to the total WAIT states. 
tCYC- 



Data sheets on pages 5-D2 through 5-D18 reprinted by permission of Intel Corporation, Copyright 1978. 



5-D2 



8085A 



< 
o 
< 



A.C. CHARACTERISTICS (t^ = o°c to yo-'c; Vcc 


= 5V ±5%; Vss = OV) 






Symbol 


Parameter 


Min. 


Max. 


Units 


Test Condition»t 


^CYC 


CLK Cycle Period 


320 


2000 


ns 


See notes 1,2, S,4, 5^' 


^1 


CLK Low Time 


80 




ns 


- ' 


^2 


CLK High Time 


120 




ns 




Vt, 


CLK Rise and Fall Time 




30 


ns 




^AL 


Address Valid Before Trailing Edge of ALE 


110 




ns 




^LA 


Address Hold Time After ALE 


100 




ns 




^LL 


ALE Width 


140 




ns 




^LCK 


ALE Low During CLK High 


100 




ns 




^LC 


Trailing Edge of ALE to Leading Edge of 
Control 


130 




ns 




^AFR 


Address Float After Leading Edge of 
READ (INTA) 







ns 




^AD 


Valid Address to Valid Data In 




575 


ns 




^RD 


READ (or INTA) to Valid Data 




300 


ns 




^RDH 


Data Hold Time After READ (INTA) 







ns 




^RAE 


Trailing Edge of READ to Re-Enabling 
of Address 


150 




ns 


TcYc = 320ns; 


^CA 


Address (A8-A15) Valid After Control 


120 




ns 


Cl = 150pF 


^DW 


Data Valid to Trailing Edge of WRITE 


420 




ns 




^WD 


Data Valid After Trailing Edge of WRITE 


100 




ns 




tec 


Width of Control Low (RD, WR, INTA) 


400 




ns 




^CL 


Trailing Edge of Control to Leading Edge 
of ALE 


50 




ns 




^ARY 


READY Valid From Address Valid 




220 


ns 




^RYS 


READY Setup Time to Leading Edge of CLK 


110 




ns 




*RYH 


READY Hold Time 







ns 




^HACK 


HLDA Valid to Trailing Edge of CLK 


110 




ns 




^HABF 


Bus Float After HLDA 




210 


ns 




^HABE 


HLDA to Bus Enable 




210 


ns 




tUDR 


ALE to Valid Data In 




460 


ns 




^RV 


Control Trailing Edge to Leading Edge of 
Next Control 


400 




ns 




^AC 


Address Valid to Leading Edge of Control 


270 




ns 




^HDS 


HOLD Setup Time to Trailing Edge of CLK 


170 




ns 




^HDH 


HOLD Hold Time 







ns 




*INS 


INTR Setup Time to Falling Edge of CLK 
(Ml, T1 only). Also RSTand TRAP 


160 




ns 




t|NH 


INTR Hold Time 







ns 





NOTES: 1. 
2. 






A8-1 5 Address Specs apply to lO/M, SO and SI . 

For all output timing where C|_ ^ 150pf use the following correction factors: 
25pf <CL<150pf : -.10 ns/pf 
150pf <CL<300pf : +.30 ns/pf 
Output timings are measured with purely capacitive load. 

All timings are measured at output voltage V|_ = .8V, Vh " 2.0V, and 1 .5V with 20ns rise and fall time on inputs. 
To calculate timing specifications at other values of T^YC u^ t^* table in Table 2. 
L.E. = Leading Edge T.E. > Trailing Edge 



5-D3 



8085A 

WAVEFORMS 




Figure 10. Clock Timing Waveform 



Read Operation 



-a: 



^ \ f u^ u^ V 



■V:a- 



'n: 



ADDRESS ^ ^// 



■}'- 



\ 



■«LC-Jt 
^ 



1 



miz 



i- 



•'"^ ' 



X 



■ wiiiw vpoi.aiiuii 



A T L_J ^^ ^ V 



■■'■a: 



p — 'lck — ► 



][: 



3: 



X 



•i 



'*. 



1:1 



/ 



'i' — 

-J — «CL-- 



Figure 11. 6085A Bus Timing 



5-D4 



8085A 



^\^-/ \. 



7 % 



J~^^ ^. 



/ 



/ 



jZ. 



\ 



(ADDRESS, CONTROLS) 



:> 



■<: 



z 
cc 
o 

CD 
U) 
O 

< 
o 

< 

@ 



Figure 13. 8085A Hold Timing' 




lO/M IS ALSO FLOATING OURINO THIS TIME 



Figure 14. 8085A interrupt and Hoid Timing 



5-D5 



8155/8156 



ABSOLUTE MAXIMUM RATINGS* 



Temperature Under Bias 0°Cto+70°C 

Storage Temperature -65°Cto+150°C 

Voltage on Any Pin 

With Respect to Ground -0.3Vto+7V 

Power Dissipation 1.5W 



*COMMENT: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS (Ta 


= 0°C to 70°C; Vcc = 5V ±5%) 






SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


V|L 


Input Low Voltage 


-0.5 


0.8 


V 




V|H 


Input High Voltage 


2.0 


Vcc-K).5 


V 




Vol 


Output Low Voltage 




0.45 


V ' 


IOL = 2mA 


VOH 


Output High Voltage 


2.4 




V 


lOH = -400/iA 


l|L 


Input Leakage 




±10 


ma 


V|N = Vcc to OV 


Ilo 


Output Leakage Current 




±10 


ma 


0.45V <VouT <Vcc 


Ice 


Vcc Supply Current 




180 


mA 




Iil(CE) 


Chip Enable Leakage 
8155 
8156 




+100 
-100 


ma 
ma 


V|N = VcctoOV 



5-D6 



8155/8156 



< 

Q 

< 

@ 



A.C. CHARACTERISTICS ITa = Ccto 70°C; Vcc = 


5V ± 5%) 








SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


tAL 


Address to Latch Set Up Time 


50 




ns 




tLA 


Address Hold Time after Latch 


80 




ns 




tLC 


Latch to READ/WRITE Control 


100 




ns 




tRD 


Valid Data Out Delay from READ Control 




170 


ns 




^AD 


Address Stable to Data Ou^ Vajjd 




400 


ns 




tLL 


Latch Enable Width 


100 




ns 




tRDF 


Data Bus Float After READ 





100 


ns 




tCL 


READ/WRITE Control to Latch Enable 


20 




ns 




tec 


READ/WRITE Control Width ' 


250 




ns 




tow 


Data In to WRITE Set Up Time 


150 




ns 




two 


Data In Hold Time After WRITE 







ns 




tRV 


Recovery Time Between Controls 


300 




ns 




tWP 


WRITE to Port Output 




400 


ns 




tpR 


Port Input Setup Time 


70 




ns 




tRP 


Port Input Hold Time 


50 




ns 


1 50 pF Load 


tSBF 


Strobe to Buffer Full 




400 


ns 




tss 


Strobe Width 


200 




ns 




tRBE 


READ to Buffer Empty 




400 


ns 




tsi 


Strobe to INTR On 




400 


ns 




tRDI 


READ to INTR Off 




400 


ns 




tpss 


Port Setup Time to Strobe Strobe 


50 




ns 




tPHS 


Port Hold Time After Strobe 


120 




ns 




tSBE 


Strobe to Buffer Empty 




400 


ns 




tWBF 


WRITE to Buffer Full 




400 


ns 




twi 


WRITE to INTR Off 




400 


ns 




tTL 


TIMER-IN to TIMER-OUT Low 




400 


ns 




tTH 


TIMER-IN to TIMER-OUT High 




400 


ns 




tRDE 


Data Bus Enable from READ Control 


10 




ns 





Note: For Timer Input Specification, see Figure 10. 



5-D7 



8155/8156 



WAVEFORMS 

Read Cycle 



\ 



/ 



\ 



X 



£ 



\ 



A 

Z 



7 
X 



J iZK 



/^~^\ 



^K 






f 



Write Cycle 



\ 



/ 



\ 



i: 



/ 



■^r 



V 



z 



:di: 



X 



7 
X 



X 



DATA VALID 



/ '\ 



J 



\ 



f 



Figure 7. 8155/8156 ReacVWrlte Timing Diagrams 



5-D8 



< 

< 
@ 



8155/8156 



Strobed Input Mode 



STROBE 



INPUT DATA 
FROM PORT 



Strobed Output Mode 



OUTPUT DATA 
TO PORT 



\ 



\ 



i: 



/ 



\ 



^i^.^^/ 



X 



/ 



\ 



^U-J' 



\ 



■•wp 



Figure 8. Strobed I/O Timing 



/ 



5-D9 



8155/8156 



Basic Input Mode 



>: 



'~~>C 



\ / 



X 



Basic Output Mode 



\ ?' 



•DATA BUS TIMING IS SHOWN IN FIGURE?. 



♦-•wp-* 



^ y r — 



X 



Figure 9. Basic I/O Timing Diagram 



LOAD COUNTER FROM CLR 
I 2 I 




TIMER OL|T 
(SQUARE WAVE) 



fJOTEl: THE TIMER OUTPUT ISPERIODIC IF IN AN AUTOMATIC COUNTDOWN FROM S TO 1 
RELOAp MODE (M, MODE BIT -II 



tcYc 320 nsac MIN. 

t, AND tf 3b nsac MAX. 

ti '' 80 nsac MIN. 

t2 120 nsac MIN. 

ItlAND tTH 400 nsac MAX. 



Figure 10. Timer Output Waveform 



5-D10 



< 

€3 

UJ 

Z 

c 
o 

CQ 
(A 

o 

< 

Q 

< 



8355 



ABSOLUTE MAXIMUM RATINGS' 



Temperature Under Bias 0''Cto+70°C 

Storage Temperature -65°Cto+150"'C 

Voltage on Any Pin 

With Respect to Ground -0.3Vto+7\/ 

Power Dissipation 1.5W 



'COMMENT: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS (Ta 


= 0°C to 70°C; Vcc = 5V ± 5%) 






SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


VlL 


Input Low Voltage 


-0.5 


0.8 


V 


Vcc = 5.0V 


V|H 


Input High Voltage 


2.0 


Vcc-K).5 


V 


Vcc = 5.0V 


Vol 


Output Low Voltage 




0.45 


V 


i0L = 2mA 


VOH 


Output High Voltage 


2.4 




V 


loH = -400mA 


l|L 


Input Leakage 




10 


HA 


V|N = Vcc to OV 


luo 


Output Leakags Current 




±10 


ma 


0.45V <VouT <Vcc 


'cc 


Vcc Supply Current 




180 


mA 





A.C. CHARACTERISTICS (Ta = o°c to 70°C; Vcc = 5V ± 5%) 



SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


tCYC 


Clock Cycle Time 


320 




ns 




Ti 


CLK Pulse Width 


.80 




ns 


Cload = 150pF 


T2 


CLK Pulse Width 


120 




ns 




tf.tr 


CLK Rise and Fall Time 




30 


ns 




tAL 


Address to Latch Set Up Time 


50 




ns 




tLA 


Address Hold Time after Latch 


80 




ns 




tLC 


Latch to READ/WRITE Control 


100 




ns 




tRD 


Valid Data Out Delay from READ Control 




170 


ns 




tAD 


Address Stable to Data Out Valid 




400 


ns 


1 50 pF Load 


tLL 


Latch Enable Width 


100 




ns 




tRDF 


Data Bus Float after READ 





100 


ns 




tCL 


READ/WRITE Control to Latch Enable 


20 




ns 




tec 


READ/WRITE Control Width 


250 




ns 




tow 


Data In to WRITE Set Up Time 


150 




ns 




two 


Data In Hold Time After WRITE 


10 




ns 




twp 


WRITE to Port Output 




400 


ns 




tpR 


Port Input Set Up Time 


50 




ns 




tRP 


Port Input Hold Time 


50 




ns 




tRYH 


READY HOLD TIME 





160 


ns 




tARY 


ADDRESS (CE) to READY 




160 


ns 




tRV 


Recovery Time between Controls 


300 




ns 




tRDE 


Data Out Delay from R EAD Control 


10 




ns 





5-D11 



8355 

WAVEFORMS 




Figure 4. Clock Specification for 8355 



"MO 
lO/M 



z>: 



(CE-D- 
(CE = 0) 



J 



A / \ / ^. J V 



\ 



:^-^zx 



\ 



\ 



\ 



)C 



> — c 



)C 



/ 



♦ tone *■ 



f 



):: 



1 



Figure 5. ROIM Read and I/O Read and Write 



5-D12 



8355 




Figure 6. Wait State Timing (READY 5 0) 



< 
o 

< 



A. INPUT MODE 



RDOR 
lOR 



\ 



PORT 
INPUT 



zy^: 



/ 



X 



DATA* 
BUS 



X 



B. OUTPUT MODE 



\ 



PORT 
OUTPUT 



/ 



*WP' 



y: 



GLITCH FREE 
■ OUTPUT 



DATA* 
BUS 



X 



X 



*DATA BUS TIMING IS SHOWN IN FIGURE 3. 



Figure 7. I/O Port Timing 



5-D13 



8755A 



-/O.. 



ABSOLUTE MAXIMUM RATINGS* 



Temperature Under Bias -10°C to +70°C 

Storage Temperature -65°Cto+150°C 

Voltage on Any Pin 

With Respect to Ground -0.5Vto+7V 

Power Dissipation 1.5W. 



^COMMENT: Stresses above those li'stedundi^ "Jk^solute 
Maximum Ratings" may cause permanent, da/ri3{^li$^ the 
device. This is a stress rating only and functidnal '^^6^$- 
tion of the device at these or any other conditions 3b(^,^ 
those indicated in the operational sections of this specifi-^^ 
cation is not implied. Exposure to absolute maximum, 
rating conditions for extended periods may affect device 
reliability. 



D.C. CHARACTERISTICS Ha 


= 0°C to 70°C; Vcc = 5V ± 5%) 






SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


V|L 


Input Low Voltage 


-0.5 


0.8 


V 




V|H 


Input High Voltage 


2.0 


Vcc+O.B 


V 




Vol 


Output Low Voltage 




0.45 


V 


loL = 2nnA 


VOH 


Output High Voltage 


2.4 




V 


lOH = -400/iA 


l|L 


Input Leakage 




10 


fxA 


V|N = Vcc to OV 


Ilo 


Output Leakage Current 




±10 


mA 


0.45V <VouT <Vcc 


Ice 


Vcc Supply Current 




180 


mA 





A.C. CHARACTERISTICS (Ta = o°c to 70°C; Vcc 


= 5V ± 5%) 






SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNITS 


TEST CONDITIONS 


tCYC 


Clock Cycle Time 


320 




ns 




Ti 


CLK Pulse Width 


80 




ns 


Cload = 150pF 


T2 


CLK Pulse Width 


120 




ns 


(See Figure 3) 


tf.tr 


CLK Rise and Fall Time 




30 


ns 




tAL 


Address to Latch Set Up Time 


50 




ns 




tLA 


Address Hold Time after Latch 


80 




ns 




tuc 


Latch to READ/WRITE Control 


100 




ns 




tRD 


Valid Data Out Delay from READ Control 




170 


ns 




tAD 


Address Stable to Data Out Valid 




450 


ns 


150pF Load 


tLL 


Latch Enable Width 


100 




ns 




tRDF 


Data Bus Float after READ 





100 


ns 




tcL 


READ/WRITE Control to Latch Enable 


20 




ns 




tec 


READ/WRITE Control Width 


250 




ns 




tow 


Data In to WR ITE Set Up Time 


150 




ns 




tWD 


Data In Hold Time After WRITE 


30 




ns 




twp 


WRITE to Port Output 




400 


ns 




tPR 


Port Input Set Up Time 


50 




ns 




tRP 


Port Input Hold Time 


50 




ns 




tRYH 


READY HOLD TIME 





160 


ns 




tARY 


ADDRESS (CE) to READY 




160 


ns 




tRV 


Recovery Time between Controls 


300 




ns 




tRDE 


Data Out Delay from READ Control 


10 




ns 





5-D14 



8755A 

WAVEFORMS 




♦f — - 



Figure 5. Clock Specification for 87S5A 



o 

< 

Q 

< 

@ 



X 



x 



\ 



/ 



X 



>-€iy[ 



\ 



X 



\ 



\ 



\ 



>—< 



/ 



/ 



> 






\ 



Figure 6. PROM Read, I/O Read and Write Timing 

Please note that CE1 must remain low for the entire cycle. 
This is due to the fact that the programming enable 
function common to this pin will disrupt internal data bus 
levels if CE1 is taken high during the read. 



5-D15 



8755A 



Input Mode 



A. INPUT MODE 



RDOR 
lOR 



\ J 



PORT 
INPUT 



^: 



X 



DATA" 
BUS 



x 



Output Mode 



B. OUTPUT MODE 



\ 



/ 



*WP" 



PORT 
OUTPUT 



.X 



GLITCH FREE 
OUTPUT 



DATA* 
BUS 



X 



X 



•DATA BUS TIMING IS SHOWN IN FIGURE 6. 



Figure 7. I/O Port Timing 



y^ 



CECE 




Figure 8. Walt State Timing (READY = 0) 



5-D16 



8755A 



D.C. SPECIFICATION FOR PROGRAMMING 

(Ta = O^C to 70°C; Vcc = 5V ±5%; Vss = OV) 



■^ 












SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNIT 


Vdd 


Programming Voltage 
(during wrije to EPROM) 


24 


25 


26 


V 


•dp 


Prog Supply Current 




15 


30 


mA 






W^ 



^r^^ 



o 

CQ 
(O 
O 

< 

Q 

< 



A.C^SPECIFICATION FOR PROGRAMMING 

(Ta = 0°C to Vp^C; Vcc = 5y ±5%; Vss = OV) 



SYMBOL 


PARAMETER 


MIN. 


TYP. 


MAX. 


UNIT 


tps 


Data Setup Time 


10 






ns 


tPD 


Data Hold Time 









ns 


ts 


Prog Pulse Setup Time 


2 






MS 


tH 


Prog Pulse Hold Time 


2 






MS 


tpR 


Prog Pulse Rise Time 


0.01 


2 




MS 


tPF 


Prog Pulse Fall Time 


0.01 


2 




MS 


tPRG 


Prog Pulse Width 


45- 


50 




msec 



5-D17 



8755A 



WAVEFORMS 



FUNCTION 


PIN NO. 


ALE 


11 


A/Do-7 


12-19 


A8-10 


21-23 


CE 


2 


PROG/CE 


1 


Vdd 


5 


RD 


9 



PROGRAM CYCLE ■ 



-VERIFY CYCLE- 



_PROQRAM 
CYCtE 



J^~\ 



^~\ 



IXEiiEXZ)' 



^X X. 



T 



'PS 



DATA TO BE 
PROGRAMMED 



r~~~\ 



yOCiEEEX 



)CZX 



^:: 



•VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE (WITH Vqq = +5V FOR 8755A, Vp^ = OV FOR 8755.) 



Figure 10. 87S5/8755A Program Mode Timing Diagram 



5-D18 



I Chapter 6 

I THE 8048 MICROCOMPUTER DEVICES 

o 
u 

z 

cA The 8048 series microcomputers are single-chip 8-bit devices which have been developed by Intel to compete 

H in the market for low-cost, high-volume applications. This is a market where the 8080A, with its high chip 

I counts, does not do well. One version of the 8048, the 8748, is also likely to do exceptionally well in low- 

o volume, custom applications because it is very easy to use. 

< The 8048 looks like a one-chip 8080A with heavy F8 influence. The F8 was the first 8-bit microprocessor to 

<>3 bring the economics of low chip counts to the attention of the semiconductor industry. It is therefore not 

z surprising to find an F8 influence in the 8048. (The F8 has now been superceded by the 3870; both parts are de- 

g scribed in Chapter 2.) 

a 

g It is intriguing to note that, |n terms of general architectural organization, there are striking similarities between 

2 the 8048 and the MCS6530 (which is described in Chapter 10). 

a The 8041 and 8021 are slave microcomputers of the 8048 family. On simple inspection the principal difference 

"^ betvveen the 8p48 qpd^he 8041/8021 would appear to be that the 8041/8021 cannot generate external 

© System Busses. In fact, there are non-obvious differences between the 8048 and the 8041/8021; there are 

further significant differences between the 8041 and the 8021. 

The 8048 is a simple, single-chip microcomputer that may be a stand-alone device, or part of a multi-microprocessor 
configuration. As a stand-alone device, the 8048 may or may not have external additional logic. Thus, the 8048 is a 
straightforward, low-end, low-cost microprocessor with less versatility than a device such as the 8085. 

If you continue the philosophical progression from the 8085 to the 8048, you reach the 8021. This is a single-chip 
microcomputer with no expansion capabilities, and very low-cost. If the 8021 exists in a multi-microprocessor con- 
figuration, then so far as the 8021 is concerned there is logic beyond its perimeters. The fact that this logic contains 
one or more microprocessors is quite immaterial to the manner in which the 8021' will be programnnpd. 

The 8041, |n sharp contrast, is a slave microprocessor that assumes the presence of a master microprocessor on one 
side and external logic on the other side. The 8041 thus becomes an interface and control part — whjch is how the 
8041 should be considered. But you will observe that a large number of microprocessor support parts also act as inter- 
faces between a microprocessor, assumed to exist on one side, and some other logic, assumed to exist on the other 
side. This is a very accurate parallel to draw. The 8041 is, in fact, a universal interface device, limited only by the speed 
of the part and the amount of programmed logic that can be included in it The 80.41 can seirve a wide variety of inter- 
face logic functions. Thus, whenever you consider using a complex interface controller part, you should also con- 
sider using the 8041 as an alternative. Because .the 8041 is programmable, you can tailor it to meet, exactly, the re- 
quirements of the specific microprocessor on one side and specific logic on the other side. This is spmething you can- 
not do with dedicated controller parts such as floppy disk and CRT controllers, which must look generically, rather than 
specifically, upon the CPU on one side and the device being controlled on the other side. 

There is also an erasable programmable read-only memory version of the 8041; it is the 8741. 

8048 series microcomputers are summarized in Table 6-1. 

The only support device described in this chapter is the 8243 I/O Expander. In addition, the 8155, the 8355, and 
the 8755 multifunction devices (which have been described in Chapter 5) can be used with 8048 family 
microcomputers. 



6-1 



The prime source for the 8048 series rnicrocomputers is: 



INTEL CORPORATION 

3065 Bowers Avenue 

Santa Clara, California 95051 



Second sources for the 8048 include: 



ADVANCED MICRO DEVICES 

901 Thompson Place 
Sunnyvale, California 94086 

SIGNETICS 

811 East Arques Avenue 

Sunnyvale, California 94043 

Neither of the 8048 second sources are likely to have significant product volumes until mid-1 978. 

Intersil plans to introduce a CMOS version of the 8048 in early 1979. 

The 8048 series microcomputers use a single +5y power supply. There are two versions of each microcomputer; one 
uses a 2.5 microsecondclock while the other uses a 5 microsecorid clock. 8048 instructions execute in either one or 
two clock periods. The 8021 uses a 10 microsecond clock. A new version of the 8049 uses a 1,4 /^sec clock. . 

Air8048,-8049 and 8041 devices are packaged as 40-pin DIPs and h^ve TTL-compatible signals. 8021 devices are 
packaged as 28-pin DIPs and have TTL-compatible signals. 









Table 6-1. 


A Summary of 8048 Ser 


ies Microcomputers 






ON CHIP MEMORY 


CYCLE 
TIME 


I/O PORTS 


EXTERNAL 
INTERRUPTS 


TIMER 


PACKAGE 
PINS 


EXPANDABLE 


ANALOG TO 

DIGITAL 
CONVERTER 


HOM/EPROM 


RAM 


8048 


1024 ROM 


64 


2.5 fisec 


3x8 bits 




Yes 


40 


Yes 


No 


8035 


■;v 0' ' 


64 


2.5 /usee 


3x8 bits 




Yes 


40 


Yes 


No 


8035-8' 





64 


5.0 ;itsec 


3x8 bits 




Yes 


40 


Yes 


No 


8748 


1024EPROM 


64 


2.5 fisec 


3x8 bits 




Yes 


40 


Yes 


No 


8748-8 


1024 EPROM 


64 


5.0 /osec 


3x8 bits 




Yes 


40 


Yes 


No 


8049 


2048 ROM 


64 


1.4/xsec 


3x8 bits 




Yes 


40 


Yes 


No 


. 8041 


1024 ROM 


64 


2.5 fisec 


3x8 bits 





Yes 


40 


Nfj 


. No 


8741 


1024 EPROM 


64. 


2.5 fisec 


3x8 bits 





Yes 


40 


No 


No 


8021 


1024 ROM 


64 


10 fisec 


2x8 bits 
1x4 bits 





Yes 


28 


No 


No 


8022 


2048 ROM 


64 


lO/nsec 


3x8 bits 


1, 


Yes 


40 


No 


Yes 



THE 8048, 8748/8049, 8749 AND 8035 
MICROCOMPUTEI^P 

For a description of an 8048, 8748, 8049, 8749, or 8035 device, read the following text; where ambiguities 
may arise |n your mind, remember these overriding rules: 

1) The 8049 is an 8048 with twice as much on-chip program memory, and, in newer models, higher execution speed. 
There are no other differences between these two parts. 

2) A,n 8035 is an 8048 with no on-chip program memory. There are no other differences between these two parts. 

For a description of an 8041, 8741 or 8021 device, read the following text, then read the specific device discus- 
sion that appears later 1n this chapter. 

Functions implemented pn the three versions of the 8048 microcomputer are illustrated in Figure 6-1. With the 
exception of the 803^, yoM will see that complete microcomputer logic is provided within a single package. But 

rerhembet, just because a function is present in Figure 6-1, that does not mean to say it will be sufficient foryoUr ap- 
plication. For example, read/write memory is shown as present, yet there are only 64 bytes of read/write memory'on 
any 8048 series rnicrocom'puter chip. 



6-2 



o 

< 

< 
@ 



Clock Logic 



Logic to Handle 
Interrupt Requests 

frorn 
External Devices 



Arithmetlh and 
Logic Unit 



Instruction Register 



Control Unit 



Interrupt Priority 
Arblti-ation 



Bus Interface 
Logic 



Accumulator 
Registeris) 



Present in all 
rriicrocbmpliters 

Not present in 
the 8035 



Data Counters) 



Stack Pointer 



Program Counter 



Direct Memory 

Access Control 

Logic 



System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 
Interface Logic 



I 



I/O Ports 
Interface Logic 



RAM Addressing 

and 
Interface Logic 



Read Only 
Memory 



I/O Ports 



Read/Write 
Memory 



8049 SERIES . ~ 
MICROCOMPUTERS 



Figure 6-1. Logic of the 8048 Series Microcomputers 

The only differences between 8048 series and 8049 series microcomputers are in the on- 
chip read-only memory and execution speed; 8049 series microcomputers have twice as 
much on-chip read-only memory as 8048 series microcomputers, and execute instructions 
80% faster. ; ,^^ 

AN 8048 AI^D 8049 FUNCTIONAL OVERVIEW 

Logic of the 8048 and 8049 series microcomputers is illustrated functionally in Figure 6-2. 

The Arithmetic and Logic Unit, the Control Unit and the Instruction register are all inaccessible to you as a user; 
therefore we will ignore this portion of the microcomputer. 

1024 bytes of program memory are provided by the 8048 arid 8748 microcomputers; the 8035 has no program memo- 
ry. The 8049 has 2048 bytes of program memory. The 8048 and 8049 have Read Only Memory (ROM), while the 8748 
has Erasable Programmable Read Only Memory (EPROM); this is the only difference between the 8048/8049 and the 
8748. 

There is a 12-bit Program Counter which allows the 8048 series microcomputers to access 4096 bytes of program 
memory. Since the 8048 and 8748 microcomputers have only 1024 bytes of program memory on the computer chip, 
the additional 3072 bytes must be external if you are going to expand program memory to the maximum addressable 
space. All 8035 microcomputer program memory is external. Only 2048 bytes of external program memory can be ad- 
ded to an 8049. 



6-3 



PiO- P17 



DO- D7 



Program 

Counter may 

be output on 

P23 - P20 plus 

D7 - DO 



P20 - P27 



Interrupt Request 

System Reset 

PROM/Expander strobe 

CPU/Memory Separate 

External Crystal 

Address Latch and Clock 

Program Memory Enable 

Single Step 

Read Strobe 

Write Strobe 

Test input or Timer output 

Test or Event Counter input 




-^- 



rC=^ 



O 



C^ 



INT 



RESET 

PROG 

EA 

XTAL1 

XTAL2 

ALE 

PSEN 

SS 

RD 

WR 

TO 

T1 



C 



<:=:> 



c 



CO 



Program Counter 



Program 
Status Word 



c 



c^ 



Accumulator 



Counter/Timer 



^ 



1024 X ,8 Bits 

ROM (8048) 

or EPROM 

(8748) 



:> 



Arithmetic and 

Logic Unit, 

Control Unit 

and Instruction 

Register 



:> 



64 X 8 Bits 
RAM 



Figure 6-2. Functional Logic of, the 8048, 8049, 8748, 
8749 and 8035 Microcomputers 



6-4 



< 

c3 

UJ 

Z 

e 
o 
m 
m 
O 

< 

Q 

< 



All 8048 series microcomputers (with the exception of the 8021) have three 8-bit I/O ports. 8048 SERIES 
For the 8048 series and 8049 series microcomputers, one of these ports, the Bus Port, is a I/O PORTS ' 
truly bidirectional I/O port with input and output strobes. Outputs can be statically latched, 
while inputs are nonlatching. This means that external logic must hold input data true at Bus Port pins until the data 
has been read. All eight pins of the Bus Port must be assigned either to input or output; you cannot mix input and out- 
put on the Bus Port. 

Bus Port is used as the primary I/O port in a single-chip microcomputer system. In multiple-chip microcomputer 
systems Bus Port serves as a multiplexed Address and Data Bus. 

I/O Ports 1 and 2 are secondary I/O ports with characteristics that differ significantly from Bus Port. If you output 
parallel data to I/O Port 1 or 2, it is latched and maintained at the I/O port until you next write data. But the only way 
external logic can input data to I/O Port 1 or 2 is by pulling individual pins from a high to a low level. Thus when a high 
level is being output at any pin of I/O Port 1 or 2, external logic can pull this level low — and subsequently if the CPU 
reads back data from the I/O port it will read a bit value. This may be illustrated as follows: 



CPU 
(7) 11110101 



output 



I/O Port 
•11110101 



External Logic 



\ 



Pull one pin low 



© 



© 



11010101- 



input 



11010101 



11010101 



External logic cannot create a high level at any pin of I/O Port 1 or 2 which is outputting a low level. 
Here is a summary of I/O Port 1 and 2 capabilities: 

1) You can at any time output parallel data to I/O Port 1 or 2. The data will be latched and held until the next output. 

2) Individual pins of I/O Ports 1 and 2 can serve as input or output pins. When you output data to I/O Port 1 or 2, you 
must output a 1 bit to any input pin. This may be illustrated as follows: 



Data Output ^ X 1 1 X X 1 X 1 (X = or .1) 
7 6 5 4 3 2 10 




Bit No. , 

I/O Port 1 or 2 (O = Output, I = Input) 



3) External logic writes to input pins of I/O Ports 1 and 2 by leaving low levels alone, and by pulling high levels low, 

Figure 6-3 illustrates logic associated with each pin of I/O Ports 1 and 2 in all 8048 series 
microcomputers. 

Output data is latched by a D-type flip-flop. 



8048 SERIES 
I/O PORT 
PIN LOGIC 



The Q and outputs of the D-type flip-fjop control a pair of gates on either side of the pin connec- 
tion. To provide fast switching times in O-to-1 transitions, a relatively low impedance (~5K ohms) is switched in for ap- 
proximately 500 nanoseconds whenever a 1 is output. 



6-5 



ORL, ANL 



INTERNAL 
BUS 



WRITE 
PULSE 



5^ 



+ 5V + 5V 

Q 



D 
FLIP 
FLOP 



CLK 



PCH 



SOKft 



= 5Kn 



it- (► 



= 3Kn 



T. 



I/O PIN 
PORT 1 AND 2 



INPUT BUFFER 



Figure 6-3. 8048 I/O Ports 1 and 2 Pin Logic 

Pins are continuously pulled up to +5V through a relatively high impedance (~50K ohms). When a is output to the 
D-type flip-flop, a low inripedance (~3K ohms) overcomes the pull-up and provides TIL current sinking capability. 

When a pin of I/O Port 1 or 2 is at a high level, external logic can sink the bOKil pull-up. But when the pin is at a low 
level, external logic cannot overcome the low impedance to ground; thus it cannot pull the pin up to a high level. 

By placing an input buffer between the pin and the switching gates, pin logic allows the CPU to read current levels in- 
duced by external logic — -but only while external logic is connected to the pin. 

The buffer connecting the Q output of the D-type flip-flop to the D input is present to enable 8048 instructions that 
mask I/O port data. 

Later in this chapter we will look at I/O ports in more detail, showing programming and desigh examples. 



6-6 



8048, 8748 AND 8035 MICROCOMPUTER PROGRAMMABLE REGISTERS 

The 8048 series microcomputers have an 8-bit Accumulator, a 12-bit Program Counter and 64 bytes of 
scratchpad memory. Scratchpad memory may be visualized either as read/write memory or as general purpose 
registers. 

The Accumulator, Program Counter and scratchpad memory may be illustrated as follows: 

8 Bits 



< 

oa 
iij 

z 

EC 

o 
m 
w 
o 

< 
o 

< 



Data Counters < 

R2 
R3 
R4 
R5 
R6 
R7 

50 ■ 

51 ■ 

52 ■ 

53 ■ 

54 ■ 

55 ■ 

56 ■ 

57 - 

Data Counters i 

(RV 

R2' 

R3' 

R4' 

R5' 

R6' 

R7- 



00 

01 

02 

03 

04 

05 

06 

07. 

08 

09 

OA 

OB 

OC 

OD, 

OE 

OF 

10 

11 

12 

13 

14 

15 

16 

17^ 

18 

19 

1A 

IB 

1C 

ID 

IE 

IF 

20 



General Purpose 
Registers 



Stack 



Alternate General 
Purpose Registers 



jeneral Scratchpad 



8-bit Accumulator 
12-bit Progrann Counter 



6-7 



The Accumulator is the principal conduit for all data transfers. The Accumulator is always one source and the 
destination for Arithmetic or Boolean operations involving memory or registers. 

Tw/o sets of eight scratchpad bytes serve as secondary registers. At any time one set of general purpose registers 
is selected while the other set of general purpose registers is not selected. 

The first two general purpose registers of each set, RO and R1, act as Data Counters to address scratchpad 
memory and external data memory. Thus you address scratchpad memory using implied memory addressing via 
general purpose Register RO or R1 ; you can address any one of the 64 scratchpad bytes, including the general purpose 
registers, or even the Data Counter register itself. 

In between the two sets of eight general purpose registers there is a 16-byte stack. The Stack Pointer is main- 
tained in the Program Status Word; therefore we will defer our discussion of stack operations until we look at status. 

8048 SERIES ADDRESSING MODES 

The 8048 series microcomputers separate memory into program memory and data memory. 
Without resorting to complex expansion schemes, you are limited to a maximum of 4096 
program memory bytes and 320 data memory bytes. 

The 8048 and 8748 microcomputers have 1024 bytes of program memory on the CPU chip. The 

8049 microcomputer has 2048 bytes of program memory on the CPU chip. More program memory, if present, must be 
external to the CPU chip. The 8035 microcomputer has no on-chip program memory; it requires all program memory to 
be external. 

All 8048 series microcomputers provide 64 bytes of read/write data memory on the CPU chip. In addition, 256 bytes of 
external data memory may be addressed. The external data memory space must be shared by external data memo- 
ry and any external I/O ports — that is to say, I/O ports other than the microcomputer's own three I/O ports or 8243 
Expander ports. 

8048 series microcomputer address spaces and addressing modes are illustrated in Figure 6-4. 

Let us first examine program memory addressing. 



8048 SERIES 

MEMORY 

SPACES 



A single address space is used to access all of program memory. In the normal course of events 8048 SERIES 

program memory is addressed via the 12-bit Program Counter. The high order Program PROGRAM 

Counter bit is isolated in Figure 6-4 because when the Program Counter is incremented only MEMORY 

bits through 1 are affected. You must execute special instructions to modify the contents of ADDRESSING 

the high order Program Counter bit. Program memory is therefore effectively divided into two 

memory banks, each containing up to 2048 bytes of program memory. You cannot branch, via Jump-on-Condition in- 
structions, from one program memory bank to the other, nor can instructions stored in one program memory bank 
directly access the other. You can switch completely from one program memory bank to the other by preceding a JMP, 
CALL or RET instruction with a SEL MB instruction. 

Two types of program memory addressing are available: you can read data from program memory and you can 
execute Jump instructions. 

You can unconditionally jump anywhere within the currently selected program memory bank; this may be illustrated as 
follows: 



These bits 
replaced 



Arbitrary 
PROGRAM Memory 
MEMORY Address 




010A 

010B ) JMP instruction 

010C I object code 

010D 



6-8 



Program Memory 



O 
m 

M 

o 

< 
o 
< 



0000 



Memory / 03FF 
BankO \ 0400 



07FF 



0800 



Memory / OBFF 
Bank 1 \ OCOO 



OFFF 



00 



On 8048, 8748 

and 

8049 Chip 



On 8049 
Chip 













^ ^ 


■""^ 








^ 




10 9 8 


1 












1 


11 


7 6 5 4 3 2 10 


b 








_ 














J 



PC 




FF 



00 



3F 



External 
Data Memory 




7 


6 


5 


4 


3 


2 


1 






































On Chip 

Scratchpad 

Memory 



A = Accumulator 
PC = Program Counter 
RO, R 1 are general purpose registers 
in scratchpad memory 



Figure 6-4. 8048 Series Microcomputers' Memory Addressing 



6-9 



Thus the JMP instruction stored in program memory bytes OIOB15 and OlOCis causes program execution to jump to 
location 06BAi6- 

You can also jump using a form of paged, indirect addressing, where the Accumulator points to an indirect address 
stored in the current page of program memory. This may be illustrated as follows: 

Arbitrary 
Program Memory 
Memory Addresses 



Accumulator 



Program 
Counter 




JMPP @, 



Jump here 



All conditional Jump instructions allow you to branch within the current page of program memory only. This may be il- 
lustrated as follows: 

Arbitrary 
Program Memory 
Memory Address 




Replace AD 

with 2C if 

condition is met 





1 

1 








F6 


_ 


2C 













0A2A 
0A2B 
0A2C 
0A2D 



OAAB 
OAAC) 
OAADj 
OAAE 



Jump here 



JC instruction 



6-10 



o 

CQ 
CO 

o 
< 

Q 

< 

@ 



You can read data from program memory, but there are no instructions which allow you to write data to program 
memory. Instructions (other than immediate instructions) that read data from program memory use paged, im- 
plied addressing. There are two forms of paged, implied programming memory addressing; they may be illustrated as 
follows: 



Arbitrary 

Memory Program 

Address, Memory 



Arbitrary 
Program Memory 
Memory Address 



01AA 
MOVP A,@A 01AB 




The illustration above compares execution of the MOVP and M0VP3 instructions. These are the two instructions which 
allow you to read a byte of data from program memory into the Accumulator. Both instructions load 4A into the Ac- 
cumulator, as illustrated above. 

When the MOVP instruction is executed, the program memory address is formed by concatenating the high-order four 
bits of the Program Counter with the contents of the Accumulator: 



Program Counter 



EJ3 EaI 



Accumulator 



When the M0VP3 instruction is executed, the program memory address is computed by appending the Accumulator 
contents to 0011: 



P Q I Accumulator 



Program Memory Address 



Thus the MOVP instruction loads into the Accumulator the contents of a program memory byte within the current pro- 
gram page. The M0VP3 instruction loads into the Accumulator the contents of a byte from program memory page 3. 

Note carefully that paged addressing of program memory carries with it the usual page boundary problems. The 

program memory addressing modes which replace the low-order eight Program Counter bits keep the four high-order 
Program Counter bits — after the Program Counter has been incremented. 

Refer back to the JMPP @A instruction. This instruction is illustrated as being stored in program memory location 
015BiB. But suppose this instruction were stored in memory location OlFF-js; then after the JMPP instruction is 
fetched, the Program Counter will no longer contain OlFFig. it will contain O2OO15. Now instead of jumping to pro- 
gram memory location OICB16. you would jump to program memory location 02CBi6- 

This page boundary problem is common to all microcomputers that use absolute paged addressing. For a complete dis- 
cussion of this problem refer to Volume I — Basic Concepts, Chapter 6. 



6-11 



Note that the 8048 has no instructions which write into program memory. If you want to write into program 
memory you must have external logic which overlaps external program and data memory. 

Let us now look at data memory addressing. First of all, notice that scratchpad memory and external data memory 
have overlapping address spaces. Separate and distinct instructions access scratchpad memory as against external 
data memory. External data memory does not represent a continuation of scratchpad memory. For example, there will 
be memory bytes with addresses in the range 00-\q through 3Fi6 in the scratchpad and in external data memory. 

Implied memory addressing is the only addressing mode available to you when accessing data memory. 

Instructions that access scratchpad memory take the scratchpad memory byte address from the low-order six bits of 
General Purpose Register RO or R1. 

Instructions that access external data memory take the external data memory address from all eight bits of General Pur- 
pose Register RO or R1. 

The eight general purpose registers within scratchpad memory can be addressed directly. We could argue that this 
constitutes a limited scratchpad memory direct addressing capability; but in order to remain consistent with other 
microcomputers described in this book, we will classify these direct accesses of general purpose registers as register- 
to-register operations rather than direct addressing of data memory. 

A PROGRAM MEMORY MAP 

The instruction set of the 8048 microcomputer is designed to allocate the on-chip program memory as follows: 



3FF 



300 
2FF 



200 
IFF 



100 
OFF" 



Data Tables 



Programs 



007 
















003 












000 





j Time 
) orlgi 



Timer interrupt calls subroutine 
rigined here 



External interrupt calls subroutine 
orlgjned here 



Restart calls subroutine 
origined here 



The M0VP3 instructions assume that the 256 byte.s of program memory with addresses 300-|6 - 3FFi6 have been set 
aside to hold tables of constant data. 

Interrupt logic (which is described later) uses low memory locations 0, 3 and 7 to origin interrupt service routines that 
will be executed in response to a restart, an external interrupt or a timer interrupt. Jump instructions will normally be 
located in these low program memory locations. 



6-12 



8048 SERIES STATUS 

8048 series microcomputers have an 8-bit Program Status Word which may be illustrated as follows: 



■ These four bits saved on Stack 



7 6 5:4:^ 2 1 



a a ii 





Bit No. 

Program Status Word 



■Stack Pointer 
-Register bank select 

= Scratchpad bytes 0-7 selected 

1 = Scratchpad bytes 18- IF selected 

■ FO, software flag 

■ AC, Auxiliary Carry 
. C, Carry 



O 

< 
a 
< 

© 



C and AC are the standard Carry and Auxiliary Carry statuses as defined in Volume I and used throughout this 
book. 

FO is a flag which you set or reset using apprdtiriate Status instructions. A conditional Jump instruction tests the 
level of FO. FO is not connected to external logic and cannot be modified or tested by external logic. 

BS identifies which set of general purpose registers is currently selected. If BS is 0, then scratchpad bytes 
through 7 are serving as general purpose registers. If BS is 1, then scratchpad bytes 18i6 through 1Fi6 are serving as 
general pijrpose registers. 

The low-order three Program Status Wbrd bits serve as a Stack Pointer. The 16 Stack bytes are treated as eight 
16-bit registers, with the current top of Stack identified by the three low-order Program Status Word- bits. 

A subroutine Call instruction pushes the Program Counter contents and the foiir high-order Program Status 
Word bits onto the Stack as follows: 



Program 
Counter 



PPPPQQQQRRRR 



PSW IS S S S 1 XXX 



-Bit No. 



■Bit No. 



Scratchpad 
Memory 


> XXX 

>XXX+1 

■^— Bit No. 


Lowest 

Scratchpad 

Address 


QQQQRRRR 


\ 

Higf 

Scratc 

Add 




SSSSPPPP 












7 


lest 

;hpad 

ress 



in the illustration above. P. Q. R. S and X represent any binary digits. 



6-13 



Observe that the begirihing of the Stack has the lowest scratchpad address. The order in which Program Status Word 
and Progrann Counter contents are pushed onto the Stacl< is illustrated above. Here is a specific case: 



PSW 


7 


Fl 




■».r- 


V 


PC 


2 


•4 


^ 




Full 



Full 



Full 



Full 



4A 



72 



07 

08' 

09 

OA 

OB 

OC 

OD 

OE 

OF 

10 



-Beginning of Stack 



You need to know the exact order in which data is stored on the Stack since the Stack is also accessible as general 
scratchpad nnemory. 

There are two RetiJrri-from-Subroutine instructions; one restores Program Counter contents only, the other restores 
Program Counter and Program Status Word contents. 

Since the Stack has eight 16-bit registers, subroutines may be nested eight deep. If you are using interrupts, then the 
combined total of suBJ-butine nestihg levels on either side of the interrupt must sum to 7 or less. For example, if the in- 
terrupt service' routine nests subroutines to a maximum level of 3, then non-interrupt programs cannot nest 
subroutines to a level greater than 4. The interrupt itself requires one Stack location. 

8048 SERIES MICROCOMPUTER OPERATING MODES 

8048 series microcomputers can operate in a variety oif modes. Many signals serve more than one functjoh, de- 
pending on the operating mode. 

In order to clarify this potentially confusing subject, we will summarize 8048 series operating modes in the 
paragraphs below, then we will summarize device signals; these two summaries are followed by an in-depth 
analysis of operating modes, illustrating timing and signal functions. 

Internal execution mode is the simplest case; the 8048 series microcomputers normally 
operate in Internal Execution mode, at which time they execute programs without access- 
ing external program memory or data rnemory. All iriformation transfer with external logic oc- 
curs via I/O ports or control signals. The 8035, having no internal program memory, cannot oper- 
ate in Internal Execution mode. 



Expandable 8048 series microcomputers can access external program and data memory. Having 
external. program memory and/or data menhory causes the microcomputer to output additional 
control signals which identify external program and data memory accesses. This is External 
Memory Access mode. Memory addresses are output via the Bus Port and four pins of I/O Port 2; 
bidirectional data transfers occur via the Bus Port. This may be illustrated as follows: 



8048 SERIES 
INTERNAL 
EXECUTION 
MODE 



8048 SERIES 
EXTERNAL 
MEMORY 
ACCESS MODE 



8048 

, 8748 

• 8035 




P20- 


P23 


K. 


> 


A 


DBO 


- DB7 


K 


c 






> 



















Data Bus 

RD 
WR 
PSEN 
ALE 



Address Bus 



Control Bus 



6-14 



External Memory Access mode represents the simplest case for the 8035 microcomputer, which has no on-chip pro 
gram memory. 

The 8048 series microcomputers can be operated in Debug mode. In Debug mode the CPU is 
disconnected from its internal program memory. All program memory accesses are deflected to 
external program memory. This may be illustrated as follows: 



8048 AND 
8748 DEBUG 

Mode 



< 
a 

< 



Internal 
Program 
Memory 



■0000 — ^ 



"O 03FF- 



External 
Debug 
Memory 



0400 



OFFF 



External 
Program 
Memory 



8048 SERIES 

SINGLE 

STEPPING 



8748 

progIramming 
mode 



Since the 8035 has no internal program memory, it is always in "Debug mode." 

You will use Debug mode to test microcomputer systems built around an 8048 series microcomputer. Typically, special 
purpose test and verify programs will be maintained in external debug memory. 

Single stepping is not really a mode, but is worth mentioning in connection with Debug 
mode since it is a_powerful debugging tool. In any of the operating modes you can apply a 
Single Step signal (SS) which halts instruction execution following the next instruction fetch. This 
allows you to execute programs one instruction at a time in order to locate errors or gain a better 
understanding of event sequences. 

The 8748 microcomputer contains Erasable Programmable Read Only Memory (EPROM). In 
Programming mode you can program the EPROM. 

Finally, there is a Verify mode. In Verify mode you can read the contents of internal or ex- 
ternal program memory as data. Verify mode is used in conjunction with Programming mode 
to test data written into EPROMs. Verify mode can also be used on its own to examine the con- 
tents of program memory for any 8048 series microcomputer. 

8048 SERIES MICROCOMPUTER PINS AND SIGNALS 

Figure 6-5 illustrates pins and signals for the 8048 series microcomputers. We will briefly summarize functions 
performed by signals before discussing how signals are used in different modes. 

DBO - DB7 serves both as a bidirectional I/O port and as a multiplexed Address and Data Bus. When no external 
data or program memory accesses are occurring, DBO - DB7 serves as a simple bidirectional I/O port or latch. During 
external program or data memory accesses, DBO - DB7 serves as a bidirectional Data Bus as well as outputting the low- 
order eight bits of all memory addresses. Data inputs are not latched in bidirectional mode. External logic must hold in- 
put signal levels until the CPU has read input data. 



8048 SERIES 
VERIFY MODE 



6-15 




PIN NAME 
DBO - DB7 



P17 
P27 



pio 

P20 

ALe 

RD 

WR 

PSEN 

EA 

SS 

INT 

TO 

T1 
RESET 

vss 
Vgc 
Vdd 



PROG 
XTAL1, XTAL2 



DESCRIPTION 

Bidirectional I/O port. Data Bus and 
low-order eight Address Bus lines 
I/O Port 1 :. 

I/O Port 2. P20 - P23 also serves as four > 
high-order Address Bus lines 
External clock signal and address 
iatch enable 

Data merriory read control 
Data memory write control 
External program memory read control 
External program memory access 
Single step control 
Interrupt request 
Test input, optional clock output 
and. Program/Verify mode select 
Test input, optional event counter input 
System reset and EPROM address latch 
Ground 
+ 5V 

+ 25V to.program 8748. + 5V standby 
for 8048 RAM 

+ 25V input to program 8748. Control 
output for 4-bit I/O 
External crystal connections 



TYPE 

Bidii'ectibnal, tristate 

Quasibidirectional 
Quasibidirectional 

Output 

Outijut 

Output 

Output 

Input 

Input 

Iriput 

Bidirectional 

Input 
Input 



Bidirectional 



Figure 6-5. 8048, 8748 and 8035 Microcomputer Pins and Signals 



6-16 



o 



PI - PI 7 and P20 - P27 support I/O Ports 1 and 2, respectively. We described the characteristics of these two I/O 
ports earlier in this chapter. During external accesses of program memory the four high-order address lines are output 
via P20 - P23. 

ALE is a control signal which is pulsed high at the beginning of every instruction execution machine cycle. This 
signal may be used as a clock by external logic. During external memory accesses, the trailing edge of ALE strobes 
memory addresses being output. 

RD is a control signal which is pulsed low to strobe data from external data memory onto the Data Bus. 

WR is a control signal which is strobed low when external data memory is to read data off the Data Bus. 



o PSEN is a control signal which is strobed low when external program memory is to place data on the Data Bus. 

~- External logic inputs EA high in order to separate the CPU from internal program memory and force the microcom- 

uj puter into Debug mode. 

< — 

5 SS IS input low in order to stop instruction execution following an instruction fetch; this allows you to single step 

° through a program. 

< INT is the input for external interrupt requests. If the interrupt is enabled, a low input at INT causes a subroutine call 
'*' to program memory location 3 when the current instruction finishes execution. 

oc TO is a test input which may be sampled by a conditional Jump instruction. TO is also used while selecting External 



Program mode and Verify mode. The internal CPU clock signal can be output via TO. 



° T1 is a test input which can be sampled by a Jump-on-Condition instruction. T1 can also be used to input a signal 

§ to Counter/Timer logic when it is serving as an event counter. 



< RESET is a standard system reset input signal. The normal RESET signal should be output from 

@ an open collector or active pull-up: 

Qvcc 



8048, 8748 
AND 8035 
RESET 



1K 



.|m)o 



•RESET 



The power-on RESET should be generated as follows: 



-O"-^ VW-— 9 RESET 

iKn 



1 



10V 



There is an internal pull-up resistor which, in combination with an external 1 /xF capacitor, generates an adequate inter- 
nal RESET pulse. If the RESET pulse is generated externally, then it must be held below 0.5V for at least 50 millise- 
conds. 

This is what happens when you reset an 8048 series microcomputer: 

1) The Program Counter and the Program Status Word are cleared. This selects register bank and program memory 
bank 0. Also, the first instruction executed following a Reset will be fetched from program memory location 0. 

2) The Bus Port is floated. 

3) I/O Ports 1 and 2 are set to Input mode. 

4) External interrupts are disabled. 

5) The counter/timer is stopped and TO is disconnected from the timer. 

6) The timer flag and internal flags F1 and FO are cleared. 



6-17 



An external crystal, if present, is connected across XTAL1 and XTAL2. Typically a 6 MHz crystal will be used. You 
can input a clock signal directly to XTAL1. If you do. the input clock signal should have a frequency in the range of 1 
MHz to 6 MHz, or 1 1 MHz for the 8049. 

The 8048 series microcomputers use power supplies in a number of interesting ways. 

Vcc is the standard +5V power supply. Vss is the standard ground connection. 

Vqq is an additional +5V standby power supply. This standby power supply will maintain the contents of 
scratchpad memory when all other power has been removed. Typically Vdd will be connected to a battery so that 
when the system is powered down data can be preserved in scratchpad mennory (8048, 8035L and 8049 only). 

The 8748 and 8749 microcomputers use Vdd 3"** PROG in order to program the EPROM. While programming the 
EPROM, a voltage of +25V is input at Vqd- +25V pulses lasting 50 milliseconds are input at PROG. A single byte of 
program memory will be written during a single PROG +25V pulse. 

PROG serves as a control strobe output to the 8243 Input/Output Expander during the execution of instructions 
that reference the Expander ports. This function of PROG is described in more detail later in this chapter, when we de- 
scribe the 8243 I/O Expander. 

8048 SERIES TIMING AND INSTRUCTION EXECUTION 

Let us begin our detailed analysts of 8048 series microcomputer operations by looking at basic instruction tim- 
ing. 

A master clock signal must be input via XTAL1, or the clock signal may be generated internally by connecting a 

crystal across XTAL1 or XTAL2. A 6 MHz crystal is recommended. This clock signal is divided by 3 to generate a 
master synchronizing 2 MHz signal which is used throughout the microcomputer system. You can output this 2 
MHz clock signal via the TO pin. 

All -8 versions of 8048 series microcomputers operate at half speed; they use 3 MHz crystals and generate a 1 
MHz master synchronizing signal. 

Instructions execute in machine cycles. Every machine cycle has five clock periods. 

Using a 2 MHz clock signal, therefore, each machine cycle will last 2.5 microseconds. Instruc- 
tions execute in either one or two machine cycles. 

INTERNAL EXECUTION MODE 

Figure 6-6 illustrates timing for the simplest case — executionof a single machine cycle in- 
struction accessing internal program or data memory only. The only signal change seen beyond the microcomputer 
chip itself is the ALE pulse — and the CLK signal, if you elect to output it via TO. The events which occur during each 
clock period are illustrated in Figure 6-6; but remember, these operations are internal to the microcomputer. They are 
beyond your access or control. 

Figure 6-6 also illustrates timing for instructions that execute in two machine cycles, but access only program and/or 
data memory internal to the microcomputer chip. Once again external logic sees ALE, and optionally CLK. 



8048 SERIES 
MACHINE 
CYCLES AND 
CLOCK PERIODS 



6-18 



o 
m 

CO 

O 

S 
< 

Q 
< 

® 



MCI 


MCI 




T1 


T2 


T3 


T4 


T5 


T1 


T2 


T3 


T4 


T5 



























(TO) CLK 



ALE 



Lr\i\rLf\rLrvru\j\f\j 



r\ 



r~\ 



Output instruction address 



Input instruction 
I 



1 

Increment PC 



Decode instruction 



/ 



Execute Instruction 



Output next instruction address 



Input Instruction 






Decode instruction' 



y 



Increment PC 



Execute instruction 



Output next instruction address 



Figure 6-6. Execution of 8048 Single Machine Cycle Instructions 
without any External Access 



(TO) CLK 



ALE 



PSEN 



DBO - DB7 



P20 - P23 





MCI 


MCI 




T1 


T2 


T3 


T4 


T5 


T1 


T2 


T3 


T4 


T5 




1 























LrLaj-LrLrLnj~LrLrLnj 




I ^ I 

Instruction Extemal 

must be Address 

stable Strobe 
on DBO - DB7 



A = Address 

I = Instruction Code 

D = I/O Data 



Instruction 

must be 

stable 

on DBO - DB7 



Figure 6-7. An 8048 Series External Instruction Fetch 



6-19 





MCI 


MCI 




T1 


T2 


T3 


T4 


T5 


T1 


T2 


T3 


T4 


T5 




1 

1 1—1 


1— 1 


1— I 


1— » 


1— I 


r— » 


1—1 


1— I 


1— » 


1— 1 


1 



(TO) CLK 



ALE 



u\^LI\I\I\I\I\I^J\I\J 



WR 



RD 



DBO - DB7 




A = Address 
DO = Data Out 
Dl = Data In 
These two machine cycles would never occur in the sequence illustrated. 
They are shown together for comparison only. 



Figure 6-8. An 8048 Series External Data Read or Write 



EXTERNAL MEMORY ACCESS MODE 

Now consider external program and data memory accesses. 

Figure 6-7 illustrates timing for an external program memory read. The external program memory address is output 
via DBO - DB7 (low-order eight address lines) and P20 - P23 (high-order four address lines). The address is maintained 
stable just long enough for external logic to latch it on the high-to-low transition of ALE. 



The low PSEN pulse serves as an external program memory read strobe. While PSEN is low, external program memory 
must decode the latched address and place the contents of the addressed m emory byte on the DBO - DB7 lines. The 
microcomputer will read DBO - DB7 on the trailing (low-to-high) transition of PSEN. 

Timing associated with reading data from external data memory and writing to external data memory is illustr- 
ated in Figure 6-8^iming is very similar to the external instruction fetch illustrated in Figure 6-7. Instead of PSEN 
being pulsed low, RD is pulsed low to strobe data input; WR is pulsed low to strobe data output. Since the total exter- 
nal data memory address space is 256 bytes, the complete address is transmitted via DBO - DB7; thus P20 - P23 is in- 
active during an access of external data memory. 

Note that the 8048 series microcomputers have no Wait state. External memory must 
therefore respond to read or write operations within the allowed time. This is not much of a prob- 
lem since 8048 series microcomputers operate relatively slowly; most standard memory devices 
will have no trouble meeting timing requirements. If you want to use slower memories, use the 
slower 5 microsecond machine cycle versions of the 8048 microcomputers. 



8048 
WAIT 
STATE 



6-20 



ALE 



8048 
8748 
8049 
or 
8035 



P23 
PSEN 

m 

WR 



DBG - DB7 ADO - AD7 

P20 - P22 A8 - A10 

:> 



JP 



ALE 



8355 
8755 



lOR 

jOW 

CE 



PAO- PA7 



PBO - PB7 



Signals not directly involved in the 8048-8355 interface are not shown. 



Figure 6-9. An 8048-8355 Configuration 



8048 
8748 
8049 

or 
8035 



PSEN (Program Memory) 
(Data Memory) 



■^ RD 1 

-^- WR ( 



ALE 



DBO - DB7 



C=; 



:> 



DIO - DI7 



P20 - P23 



^ 



r 



5V 



STB 



8212 



MD 

DS2 DS1 



DIO - DI3 



'> 



DI4 

JDI5 
DI6 
D'7 



+ 5V 



DOO - D07 



^ 



Data Bus 
DO- D7 



AO- A7 



J^ 



5V 



> Address Bus 



STB 



8212 



MD 

DS2 DS1 



F^ 



DOO - D07 



:> 



A8- A15 



J^ 



5V. 



Figure 6-10. Dennultiplexing DBO - DB7 to Create Separate 
Address and Data Busses 



6-21 



Let us examine microcomputer configurations that include external memory. 

Vendor literature illustrates complex microcomputer systems built around 8048 series microcomputers; while 
such large microcomputer systems are certainly feasible, they are not advisable. If you are going to expand an 
8048 series microcomputer system to more than two or three devices, in all probability an 8085 system would 
be more economical and powerful — not to mention a number of other microcomputers described in this book. 
We will therefore confine ourselves to illustrating 2- and 3-chip configurations. 

Figure 6-9 illustrates an 8048-8355 (or 8755) configuration. The 8355 (or 8755) is a multifunction support 
device described in Chapter 5. 

Figure 6-10 shows how you can connect standard memory devices to an 8048 series microcomputer. 

Let us examine Figure 6-9. The 8048 Bus Port is directly compatible with ADO - AD7, the multiplexed Data and Ad- 
dress Bus of the 8355 device. 



The three high-order address lines required by the 8355, A8, A9 and A10, are taken 8355 OR 8755 

directly from P20. P21 and P22. P23, the high-order address line output by the 8048, is CONNECTED 

used to enable the 8355. As shown in Figure 6-9, this means the 8355 will respond to ad- TO AN 8048 

dresses in program memoryjbank 1. If you are using an 8035 microcomputer, then P23 SERIES 

could be connected to the CE enable pin of the 8355; now the 8355 will respond to ad- MICROCOMPUTER 

dresses in program memory bank 0. It would make little sense having the 8355 respond to 

addresses in program memory bank when using an 8048 or 8748, because the first 1024 bytes of program memory 

are internal to these microcomputers; that means the first 1024 bytes of 8355 memory would never be accessed. The 

8049 microcomputer has 2048 bytes of on-chip program memory, so you would access no 8355 memory. 

Control signals needed to read data out of 8355 program memory are easily derived. The 8048 ALE output is exactly 
what is needed for the 8355 ALE input. The memory strobe RD required by the 8355 is adequately generated by the 
PSEN output of the 8048. 

You can also access the 8355 I/ O po rts by connecting the RD and WR outputs of the 8048 to the lOR and lOW 
inputs of the 8355; the lOR and lOW control inputs of the 8355 were specifically designed for this purpose. RD 

and WR control signals are generated by the 8048 series microcomputers in order to access data memory external to 
the microcomputer device itself. Thus the I/O ports of the 8355 device must be accessed within the address space of 
external data memory. In Figure 6-9 external data memory addresses 0, 1, 2 and 3 will access the 8355 I/O ports — and 
their respective Data Direction registers. Of course, the 8355 I/O ports can be accessed only while the 8355 is selected 
— via a high CE input. 

In order to attach standard memory devices to an 8048 series microcomputer, you 
must demultiplex the DBO - DB7 lines to create separate Data and Address Busses. 
Figure 6-10 shows how to do this using two 8212 I/O ports. 8212 I/O port operations 
are described in Chapter 4. In Figure 6-10 the 8212 I/O ports are being used as simple out- 
put ports v/ithout handshaking. By tying STB and MD high, the 8212 I/O ports will output 
whatever is being input while the device is selected. We use the ALE signal to complete 
selection of the 8212 I/O ports; thus while ALE is high the two ports are selected. 

Timing may be illustrated as follows: 



STANDARD 

MEMORY 

DEVICES 

CONNECTED 

TO AN 8048 

SERIES 

MICROCOMPUTER 



ALE 



DBO - DB7 



P20 - P23 D 



8212 DO 




6-22 



o 
m 
(n 
O 

< 

Q 

< 

@ 



Thus the 821 2 ports output DBO - DB7 or P20 - P23 levels latched while ALE is high. Once ALE goes low, 821 2 port 
outputs remain constant. 

But there are a few subtleties associated with Figure 6-10. 

When an 8048 series microcomputer is accessing external program memory, a 1 2- bit ad dress is output via DBO - DB7 
and P20-P23; therefore the entire Address Bus is needed as illustrated. A low PSEN pulse serves as the external 
memory read strobe. 

When 8048 series microcomputers access external data memory, however, only DBO - DB7 is affected. Thus the sec- 
ond 8212 I/O port creates address lines A8 - A15, which will carry the most recent data output to I/O Port 2 — for ex- 
ample, you may set all I/O Port 2 pins to during initialization. If I/O Port 2 is undefined, spurious selection of program 
memory will occur in configurations that include external program and data memory. At the time ALE is output as a 
high pulse no other signals indicate whether the subs equent memory acce ss w ill involve program memory or data 
memory. It is only the separate control strobes — PSEN for program memory, WR and RD for data memory — that in- 
sure the correct memory module will be accessed. If your 8048 program uses I/O Port 2 for data output as well as for 
external memory addressing, you should buffer the System Bus; make sure, in this case, that the System Bus has suffi- 
cient capacity to handle two selected memory devices simultaneously. 

Even though two memory devices m ay be selected simultaneously, you will not ru n int o memory access contentions 
since program memory is strobed by PSEN while data memory is strobed by RD and WR. Only one of these signals will 
be active at any time. 

DEBUG MODE 

You can bypass program memory internal to the 8048 series microcomputer by inputting a high signal at EA. 
While EA is high, timing for all program memory accesses will confor m to ex ternal program memory accesses as 
illustrated in Figure 6-7. You may change the level of EA only when RESET is low; that is, you cannot switch bet- 
ween internal and external memory during program execution. 

Here is one of the ways in which you may use Debug mode: 

In user end products an external memory device may contain test and verify programs. A service representative will ex- 
ecute these test and verify programs by applying a high input at EA. For example, you could connect an 8355 multi- 
function device to the 8048, selecting it via program memory bank 0. If EA is taken out to a switch, a serviceman will be 
able to execute programs out of the first 1024 bytes of 8355 program memory, instead of internal microcomputer 
memory. 

EA is also used by programming and verification modes. This use of EA, however, has nothing to do with Debug 
mode. 

SINGLE STEPPING 

If you input a low signal at SS, then when ALE next pulses high, it will stay high until SS returns high. While ALE is 
high, instruction execution ceases and the current Program Counter contents are output via DBO - DB7 and P20 - P23. 
Timing may be illustrated as follows: 



ALE 



SS 



I~\ 



DBO - DB7 



P20 - P23 





PCO - 7 



PCS- PC11 



Stop Cycle 



The CPU only tests SS level while ALE is high. At other times SS level is irrelevant. 

Single stepping is an 8048 series microcomputer program debugging aid. Intel literature suggests the circuit il- 
lustrated in Figure 6-1 1 to create an SS signal that is initiated by an ALE pulse and terminated by a pushbutton. 



6-23 



+ 5V 



SINGLE 
STEP 

b— * 



10K 



+ 5V 



r— O^ 

+ 5V .^ 



MOMENTARY 
PUSHBUTTON 



10K 



(>— O 



n 



+ 5V 



10K 




PRESET 
D Q 

: 1/2 7474 
\> CLOCK 

CLEAR 



Y 



■SS 



<l- 



ALE 



1/2 7400 



Figure 6-11. An 8048 Single Step Circuit 

if you do not wish to single step, then connecting the Single Step switch in the Run position will hold PRESET at 
ground, which forces the Q output high; instructions will execute normally. With the Single Step switch in the Single 
Step position, PRESET is heldjiigh; now the ALE_input to CLEAR beconnes active. As soon as ALE goes low the Q out- 
put is also driven low; thus SS is low. The low SS is detected on the next high ALE pulse, at which time ALE remains 
high and the cycle is stopped. This condition persists until the pushbutton is depressed. Depressing the pushbutton 
creates a low-to-high clock transition which forces SS high — thus terminating the stopped condition. You, as a user, 
will see a program advance one Instruction every time you press the pushbutton. 

While an 8048 series microcomputer is stopped in a single step, the current Program Counter contents are out- 
put via the Bus Port (DBO - DB7) and P20 - P23. The Bus Port output presents no problem since you would expect to 
see address information output at this time. But if I/O Port 2 is being used as a regular I/O port, then prior data present 
on lines P20 - P23 will not be available during the address output. Thus if you wish to view I/O data output vjhWa 
single stepping, you must latch I/O Port 2 data externally. 

PROGRAMMING MODE 

Of the 8048 microcomputer series, only the 87XX numbered microcomputer program memory can be written 
into. We will now examine the vvay in which the 8748 EPROM is programmed and verified. 

In all probability, you will program an 87XX memory using a development tool which automates the entire pro- 
cess. That being the case, the event sequence which we are about to describe is not particularly interesting to 
you, since it is taken care of by the PROM programmer. But if you build your own PROM programmer, or if for 
any reason you need to understand the PROM programming sequence, then read on. 

While programming and verifying the EPROM, you should input a clock signal at XTAL1 with a frequency between 1 
and 6 MHz; you can also use the on-chip oscillator at this time. 

Operations now proceed one byte at a time; you write a byte into program memory, then you verify that the data has 
been written correctly. 



6-24 



o 

GQ 
(0 
O 

< 
< ' 
@ 



XTAL1 



RESET 



TESTO 



+ 5V 



+ 5V 



fwj\j\i\i\j\i\f\rj\f\fy\f\ 



+ 5V \ I 

\—L 



BUS and PROG can only be driven at this time- 



EA 



+ 25V 
+ 5V 



BUS 



P20 - P21 



ADDRESS AO - A7 



DATA 



[DATA OUT 



£ 



ADDRESS A8 - A15 



Vdd 



+ 25V 
+ 5V 



PROG + 5V 
+ 0V 



+ 25V 



r\-r 



Figure 6-12. 8748 EPROM Programming and Verification Timing 
In the discussion which follows, refer to Figure 6-12, which illustrates timing for the program/verify sequence. 



Step 1) Initially 4-5V is input at Vdd- TO and EA. RESET is held at ground. Under these conditions you insert the 
8748 into the programming socket. You must make certain to insert the 8748 correctly. If you insert the 
8748 incorrectly you will destroy it. 

Step 2) TO is pulled to ground;, this selects Programming mode. 

Step 3) +25V is applied to EA. This activates Programming mode. 

Step 4) A 10-bit memory address is applied via DBO - DB7 and P20 - P23. Remember, there are 1024 bytes of pro- 
gram memory on the 8748 device: The low-order eight address bits are input via DBO - DB7 while the two 
high-order address bits are input via P20 and P21. 



Step 5) -I-5V is applied at RESET. This latches the address. 

Step 6) The data to be written into the addressed programmed memory byte is inpdt at DBO - DB7. 

Step 7) In order to write the data into the addressed program memory byte apply -I-25V to Vdo- then ground PROG, 
then apply a +25V pulse at PROG;, the -I-25V pulse at PROG must last at least 50 milliseconds. 

Step 8) Now reduce Vqd to -I-5V. Programming is complete and verification is about to begin. 

Step 9) In order to verify the data just written, apply -I-5V to the TO input. This selects Verify mode. 

Step 10) As soon as Verify mode has been selected, the data just written is output oh DBO - DB7. You must read and 
verify this data using appropriate external circuitry. Verification is now complete. 



In order to write into the next memory byte, select Programming mode again by connecting TO and RESET to ground; 
then return to Step 3. 

Repeat the program/verify sequence, byte-by-byte, until the entire program memory has been written into. 

In order to erase the EPROM expose it to ultraviolet light for a minimum of 20 minutes. 



6-25 



VERIFICATION MODE 

You can verify the contents of an 8048 series microcomputer program memory at any time. 

When verifying program memory contents for an 8048 series m icrocomputer with EPROM, you enter the Verify mode 

by applying +25V to the EA pin and +5V to the TO pin. RESET must be held at ground while you apply +5V to the TO 

pin. 

Using an 8048 series microcomputer with ROM, you enter the Verifymode by applying +12V to the EA pin. 

Once in the Verify mode, place the address of the program memory location which is to be read at DBO - DB7 (low- 
order byte) and P20 - P2i (high-order four bits). 

Latch this address by applying -f-5V to RESET. 

While RESET is high, the contents of the addressed program miemory location are output via DBO - DB7. 

You may repeat the verification process, byte-by-byte. 

Verification timing is illustrated as follows; 



TO (8748 only) 



EA 






( + 5V, 8748 only) 



/+ 25V 8748 \ 
'\+ 12V 8048/ 



RESET 



f-^4— 5— > 



DBO - DB7 y Address (AO - A7) ' | Data Out T (aq^^?) I Data Out IT 

P20 - P21 I Address (A8-A11) \ Address (A8-A'l 1 ) | 



INPUT/OUTPUT PROGRAMMING 

8048 series microcomputers (with the exception of the 8021) have three I/O ports, the physical characteristics of 
which we have already described. Instructions alloW ydij to input or output Accumulator data via any one of the 

three I/O ports. You can also directly mask data resident at an I/O port using an AND mask or an OR mask. 

There are two types of input/output beyond the 8048 series microcomputer chip itself. 

The low-order four bits of I/O Port 2 may be connected to the 8243 Input/Output Expander which has four in- 
dividually addressable 4-bit I/O ports. The 8243 Input/Output Expander is described later in this chapter. 

You can also implement I/O ports within the external data memory address space for the expandable microcom- 
puters of the 8048 series. We have already seen how you do this using an 8355 multifunction device connected to an 
8048 series microcomputer. In this particular case the two I/O ports of the 8355 device are addressed as external data 
memory locations and 1. Any other implementation of external I/O ports is allowed; however, in every case the I/O 
ports must be addressed as external data memory bytes using external data memory access instructions. 

HOLD STATE 

There is no Hold state that external logic can induce in an 8048 series microcomputer. This is not unreasonable, 
since the purpose of the Hold state is to enable direct memory access operations — which would make little 
sense in a microcomputer system as small as an 8048, which has a maximum of 256 external data memory 
bytes. 



6-26 



COUNTER/TIMER OPERATIONS 

All 8048 series microcomputers have an internal counter/timer. Counter/timer logic may be illustrated as 
follows: 



CLK 



< 
Q 

< 




8-bit register 



*n 



Time out flag 

Time out 
interrupt request 



The Counter/Timer register is eight bits wide; it is accessed via Accumulator instructions, which move Accumulator 
contents to the Counter/Timer register or move Counter/Timer register contents to the Accumulator. 

Generally stated, this is how the counter/timer works: 

You begin by loading an initial value into the Counter/Timer register. Next, you start the counter/timer by executing 
the STRT T or STRT CNT instruction. The counter/timer will increment continuously until stopped by a Stop 
Counter/Timer instruction. 

Whenever the counter/timer increments from FFis to OO-is- it activates a counter/timer interrupt request and sets a 
time-out flag. If the counter/timer interrupt has been enabled, then program execution will branch to the appropriate 
interrupt service routine. If the counter/timer interrupt has been enabled, then you must test for a time-out by execut- 
ing the JTO Branch-on-Condition instruction. 

You can operate the counter/timer as a counter or as a timer. The STRT T instruction operates the counter/timer as 
a timer, in which case the internal system clock increments the Timer register once every 480 crystal oscillations 
(80 microseconds, assuming a 6 MHz crystal). 

You operate the counter/timer as a counter by executing the STRT CNT instruction. Now high-to-low transitions of a 
signal input at T1 increment the counter. The minimum time interval between high-to-iow T1 transitions is 45 crystal 
oscillations (7.5 microseconds, assuming a 6 MHz crystal). There is no maximum delay between T1 high-to-low transi- 
tions. Once T1 goes high it must remain high for at least 3 crystal oscillations (500 nanoseconds, assuming a 6 MHz 
crystal). 

You execute the STOP TCNT instruction to stop the counter/timer, whether it is operating as a counter or as a timer. 

Here is an instruction sequence which initiates the counter/timer operating as a timer with interrupts enabled: 

MOV A,#TSTART :LOAD INITIAL COUNTER/TIMER CONSTANT 

MOV T,A 

EN TCNTI lENABLE TIMER INTERRUPT 

STRT T , ;START THE TIMER 

The following instruction sequence operates the counter/timer as a counter with interrupts disabled: 

DIS TCNTI ;D1SABLE COUNTER INTERRUPT EARLY IN PROGRAM 



MOV A,#TSTART ;|.OAD INITIAL COUNTER/TIMER CONSTANT 

MOV T,A 

STRT CNT ;START COUNTER 

INTERNAL AND EXTERNAL INTERRUPTS 

The 8048 series microcomputers have a simple interrupt scheme that is effective and adequate for small 
microcomputers. Interrupts can originate from one of three sources: 

1) A Reset. This is a non-maskable interrupt. 

2) An external interrupt induced by setting INT low. (This is not available on the 8041 and 8021 series microcom- 
puters.) 

3) A counter/timer interrupt which is automatically requested every time the Counter/Timer register increments from 
FFi6to00i6- 



6-27 



External interrupts and counter/tinner interrupts can be enabled and disabled individually. 

When any one of the three interrupt requests is acl<nowledged, the microcomputer executes a Call instruction 
to one of these three locations: 

Reset: GALL 

External interrupt: CALL 3 

Counter/Timer interrupt: CALL 7 

The Reset interrupt always has highest priority and cannot be disabled. 

If an external interrupt request and a counter/timer interrupt request occur simultaneously, the external interrupt will 
be acknovyledged first. When either an external interrupt or a counter/timer interrupt is acl<nowledged, all inter- 
rupts (except Reset) are disabled until an RETR instruction is executed. VVithin an External or Timer interrupt 
service routine you cannot enabje interrupts under program control. This may be a problem if you are using the 
timer and external interrupts in timer sensitive appjications. If execution time for an external interrupt's service routine 
extends over more than one counter/timer time out, then you will fail to detect one or more time outs. The simplest way 
of resolving thjis problem is to make sure that your External interrupt service routinesare very short — executing in 75% 
of the counter/timer interval, or less. If this is not feasible, then you must monitor the counter/timer by testing its time 
out flag rather than by using counter/timer interrupt logic. You can execute the JTF conditional Jump instruction at 
frequent intervals within the main program and interrupt service routines, thus catching time outs irrespective of when 
they occur.: 

You cari re-enable interrupts within an interrupt service routine by executing a dummy RETR instruction. Here is 
an appropriate instruction sequence: 

START OF INTERRUPT SERVICE ROUTINE 



CALL ENAB ;RE-ENABLE INTERRUPTS 

EN ' ■ I 

EN TCNTI 



END OF INTERRUPT SERVICE ROUTINE 
ENAB RETR 

Enabling interrupts within a service routine, as illustrated above, is not recommended in an 8048 microcomputer 

system. ' . 

Two problems need to be resolved when using external interrupts in an 8048 series microcomputer system: an 
interrupt aclcnowledge must be created, and in multiple interrupt configurations we must be able to identify the 
interrupting source. 

8048 series microcomputers have no interrupt acknowledge signal. An interrupt acknowledge signal must be created; 
otherwise external logic does not know when to remove its interrupt request. Arid if the interrupt request remains after 
an RETR instruction executes, the interrupt will be reacknowledged. The only straightforward way of acknowledg- 
ing an interrupt is to assign one of the |/0 port pins to serve as an interrupt acknowledge signal. The external in- 
terrupt service routine will begin by outputting an appropriate low pin signal. Here is one possibility: 

ANL P1,#7FH : RESET PIN 7 OF I/O PORT 1 LOW 

ORL P1,#80H :SET PIN 7 OF I/O PORT 1 HIGH 

Here, the output at pin 7 of I/O Port 1 is a low pulse with a duration of two machine cycles (5.0 microseconds). 

But remember, if you use an I/O port pin as an interrupt acknowledge, you cannot use the same pin to perform standard 
I/O operations. 



6-28 



o 

m 

(A 

o 
< 

Q 

< 

® 



lACK 

(PI 7) lACKO IACK1 IACK2 IACK3 IACK4 IACK5 IACK6 IACK7 



xy 



fOK> 



C> 



^ 



k3 



NI> 



C> 







K> 



MIH=D4D-^ 



O 



E 



C> 



9318 

or 
74148 



P10 



•P11 



•P12 



I> 



.INT 
to CPU 



INTO INT1 



INT2 



INT3 



INT4 



INT5 



INT6 



INT7 



Figure 6-13. An Eight-Device Daisy Chained Interrupt Request/Aci<nowledge Scheme 

If there are nnany external devices which can request interrupt service, then the nnost effective way of handling multiple 
interrupts is via a daisy chain. Daisy chain logic has been discussed in Volume I — Basic Concepts . The acknowledged 
device in the daisy chain must create a device code that is input to an I/O port. Figure 6-13 illustrates a scheme 
whereby eight devices in a daisy chain may request interrupt service, and upon being acknowledged, the 
selected device will input a unique code to I/O Port 1. The high-order bit of I/O Port 1 serves as an interrupt 
acknowledge. I/O Port 1 bits 0, 1 and 2 receive as inputs a 3-bit code identifying the acknowledged device. 

The daisy chain logic in Figure 6-1 3 is creat ed using a chain of eight AND ga tes an d eight NAND gates. The AND gates 
are chained in order of priority, with I NTO having the highest priority and INT7 having the lowest priority. The first 
NAND gate receives as its inputs INTO and the acknowledge signal output via pin 7 of I/O Port 1. Subsequent NAND 
gates receive as their inputs an interrupt request signal, the acknowledge signal and the output of the previous AND 
gate. The output of each NAND gate becomes an interrupt ackno wledge signal which is low-true. Thus in Figure 6-13 
there are eight low-true interrupt requ ests, re presente d by si gnals INTO through INT7, and there are eight low-true in- 
terrupt acknowledges, repre sented by lACKO through IACK7. Each exter nal dev ice capable of requesting an interrupt 
must output a low-true INTn which it removes upon receiving a low-true lACKn. For device 3 this may be illustrated as 
follows: 



INT3 



IACK3 




The eight interrupt request signals INTO through INT7 are in put to an AND gate. The AND gate generates a master low- 
true interrupt request, INT. If any one or more of the INTn signals are low, then the AND gate will output a low INT. 

The eight interrupt acknowledge signals lACKO - IACK7 are input to an 8-to-3 Decoder. The 8-to-3 Decoder will receive 
seven high signals and one low signal. The one low signal will be identified by the decoder 3-bit output which is 
transmitted to pins 0, 1 and 2 of I/O Port 1. 



6-29 



This then is the event sequence associated with an interrupt request: 

1) INT is input low to the 8048. 

2) The interrupt is acknowledged by the CPU, which branches to an interrupt service routine. 

3) The first instruction of the interrupt service routine outputs a low level via pin 7 of I/O Port; 1. 

4) The interrupt service routine receives back, via pins 0, 1 and 2 of I/O Port 1 , the device code for the acknowledged 
device. You must make sure that the program being executed gives external logic time to return this code. You 
may have to insert No Operation instructions to create the necessary time delay. 

5) A high level is output via pin 7 of I/O Port 1. 

6) Using the code input via pins 0, 1 and 2 of I/O Port 1, branch to the appropriate interrupt service routine. 

Here is the initial instruction sequence required by the logic of Figure 6-13: 

ORG 3 

;START OF INTERRUPT SERVICE ROUTINE 
JMP EXTINT 



ORG 


EXTINT 


ANL 


P1.#7FH 


NOP 




IN 


A,P1 


ORL 


P1,#80H 


ANL 


A,#7 


JMPP 


@A 



SET I/O PORT 1 PIN 7 LOW 

ALLOW SETTLING TIME 

INPUT PORT 1 CONTENTS 

SET I/O PORT 1 PIN 7 HIGH 

CLEAR ALL ACCUMULATOR BITS BAR 0, 1 AND 2 

JUMP TO IDENTIFIED INTERRUPT SERVICE ROUTINE 

Let us examine the interrupt service routine beginning instruction sequence illustrated above. 

When an 8048 series microcomputer is initially reset, all I/O port pins output high levels. Thus you do not have to in: 
itialize pin 7 of I/O Port 1 to a high level. 

We actually identify one of eight device interrupt service routines by creating a 3-bit code in bits 1, 2 and 3 of the Ac- 
cumulator. We then perform an indirect Jump. This Jump instruction will branch to a location on the current page of 
program memory; the address is fetched from the location in the current page addressed by the Accumulator contents. 
We illustrated this addressing technique earlier in the chapter. 

Given the instruction sequence illustrated above, the first eight program memory locations on the same page as the 
JMPP instruction must be set aside for eight addresses; these are the starting addresses for the interrupt service 
routines. This may be illustrated as follows: 



EXTINT 



ORG 


#0300H 




DB 


ISO 


ADDRESS OF 


DB 


IS1 


ADDRESS OF 


DB 


IS2 


ADDRESS OF 


DB 


IS3 


ADDRESS OF 


DB 


IS4 


ADDRESS OF 


DB 


IS5 


ADDRESS OF 


DB 


IS6 


ADDRESS OF 


DB 


IS7 


ADDRESS OF 


ANL 


#7FH 


SET I/O PORT 



INTERRUPT SERVICE 
INTERRUPT SERVICE 
INTERRUPT SERVICE 
INTERRUPT SERVICE 
INTERRUPT SERVICE 
INTERRUPT SERVICE 
INTERRUPT SERVICE 
INTERRUPT SERVICE 
1 PIN 7 LOW 



ROUTINE 
ROUTINE 1 
ROUTINE 2 
ROUTINE 3 
ROUTINE 4 
ROUTINE 5 
ROUTINE 6 
ROUTINE 7 



The daisy chained interrupt scheme discussed above can also be implemented using the circuit in Figure 6-14. 
The advantage of this circuit is that it requires fewer chips than the circuit of Figure 6-13. As far as the 8048 
program is concerned, however, the two circuits are identical. 

The INT and device code inputs are generated in exactly the same way. However, an eight-line-to-three-line priority en- 
coder (931 8 or 74148) replaces the network of AND gates. As the function table for the encoder shows, the device code 
output on lines A2, A1 and AO is that of the highest priority request. The CPU enables the code outputs by sending the 
acknowledge signal. 



6-30 



o 

< 

Q 
< 



lACK (P17) ■ 
INTO ■ 
INTI- 
JNT2, 
INT3 ' 
INT4 ■ 
INTS; . 
INT6 ■ 
lt^7. 



G2A 
G2B 
G1 



74LS138 



P10 
P11 
P12 



I> 



-^ INT to CPU 



74LS138 


74S138 FUNCTION TABLE 
















9318, 


74148 FUNCTION TABLE 










INPUTS 












































OUTPUTS 
















NPUTS 


















ENABLE 


SELECT 




































G1 gT* 


C B A 


YO 


yT 72 Y3 Y? 


Y5 


Y6 


Y7 


IT 


10 


11 


12 


13 


14 


15 


16 


17 


A2 


A1 


AO 


GS 


EO 


X H 


XXX 


H 


H H H H 


H 


H 


H 


H 


X 


X 


X 


X 


X 


X 


X 


X 


H 


H 


H 


H 


H 


L X 


XXX 


H 


H H H H 


H 


H 


H 




,H 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 


L 


H L 


L L L 


L 


H H H H 


H 


H 


H 




X 


X 


X 


X 


X 


X 


X 


L 


L 


L 


L 




H 


H L 


L L H 


H 


L H H H 


H 


H 


H 




X 


X 


X 


X 


X 


X 


L 


H 


L 


L 


H 




H 


H L 


L H L 


H 


H L H H 


H 


H 


H 




X 


X 


X 


X 


X 


L 


H 


H 


L 


H 


L 




H 


H L 


L H H 


H 


H H L H 


H 


H 


H 




X 


X 


X 


X 


L 


H 


H 


H 


L 


H 


H 




.H 


H L 


H L L 


H 


H H H L 


H 


H 


H 




X 


X 


X 


L 


H 


H 


H 


H 


H 


L 


L 




H 


H L 


H L H 


H 


H H H H 


L 


H 


H 




X 


X 


L 


H 


H 


H 


H 


H 


H 


L 


H 




H 


H L 


H H L 


H 


H H H H 


H 


L 


H 




X 


L 


H 


H 


H 


H 


H 


H 


H 


H 


L 




H 


H L 


H H H 


H 


H H H H 


H 


H 


L 




L 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 




H 


•G2=G2AVG2B 


H 


= high level, L = 


= low level, 




X = 


Irrelevant 





Figure 6-14. A Low Chip Count Implementation of an Eight-Device Daisy Chained 
Interrupt Request/Acknowledge Scheme 

In Figure 6-13, a network of NAND gates generated the low-true interrupt acknowledge signal to inform the appropri- 
ate device that its interrupt was being serviced. In Figure 6-14, a three-line-to-eight-line decoder {74S138 or 74LS138) 
translates the device code output by the encoder and sets the corresponding acknowledge line low, as is shown in the 
function table for the decoder. 

Connecting the enable inputs as shown prevents spurious acknowledgements or phantom device codes, provided that 
the CPU gives the external devices time for response and propagation delay. 



6-31 



THE 8048 MICROCOMPUTER SERIES 
INSTRUCTION SET 

Table 6-2 summarizes the instruction set for the 8048 series microcomputers. Instruction object codes and tim- 
ing are given in Table 6-3. This instruction set reflects the specific architecture of 8048 series microcomputers. For ex- 
ample, there are separate I/O instructions to access the three on-chip I/O ports, as against 8243 Input/Output Expander 
I/O ports. Also, there are separate instructions to access on-chip scratchpad read/write memory, as against external- 
data memory. 

The 8048 instruction set is probably more versatile than any other one-chip microcomputer instruction set de- 
scribed in this book. The only omission that may cause problems is the lack of an Overflow status; this will make 
multibyte signed binary arithmetic harder to program. 

THE BENCHMARK PROGRAM 

The benchmark program we have been using in this book is not realistic for the 8048 with its limited data memory. 
Using the 8048 you would not load data into some general depository, then transfer it to a specific data table. 

In order to provide some illustration of 8048 instructions, however, we will slightly modify the benchmark program and 
move a number of data bytes from the top of scratchpad memory to a table in external data memory. Since the data in 
scratchpad memory must have been input from an I/O port, we will assume that the number of scratchpad memory 
bytes is stored in General Purpose Register R7. The table in external memory begins at a known location and the first ta- 
ble byte addresses the first free table location. Operations performed may be illustrated as follows: 



Scratchpad 




First free byte 



6-32 



o 

< 

< 
@ 



LOOP 



These 

A 

A03 

R 

REG 

RN 

T 

C 

AC 

MBO 

MB1 

MBN 

I 

12 

PC 

PC10 

PCL 

PCH 

SP 

PSW 



MOV 

MOVX 

MOV 

ADD 

MOVX 

MOV 

MOV 

MOVX 

DEC 

INC 

DJNZ 



RO,#TBASE 

A,@RO 

R1,A 

A,R7 

@RO,A 

R0,#3FH 

A.@RO 

@R1,A 

RO 

R1 

R7,L00P 



LOAD EXTERNAL TABLE BASE ADDRESS INTO RO 

LOAD ADDRESS OF FIRST FREE BYTE INTO A 

SAVE IN R1 

ADD NEW BYTE COUNT TO A 

RESTORE IN FIRST FREE BYTE OF EXTERNAL TABLE 

LOAD SCRATCHPAD ADDRESS INTO RO 

MOVE DATA FROM SCRATCHPAD TO A 

STORE IN EXTERNAL DATA TABLE 

DECREMENT RO 

INCREMENT R1 

DECREMENT R7, SKIP IF NOT ZERO 



are the abbreviations used in Table 6-2: 

The Accumulator 
Accumulator bits 0-3 
Register RO or Rl 

Accumulator, RO, Rl, R2, R3. R4, R5, R6 or R7 
Register RO, Rl, R2, R3, R4, R5, R6 or R7 
Timer/Counter 
Carry status 
Auxiliary Carry status 
Program memory bank 
Program memory bank 1 
MBO orMBI 
The Instruction register 
Second object code byte 
The Program Counter 
The Program Counter, bits 0-10 
The Program Counter, bits 0-7 
The Program Counter, bits 8-1 1 
Stack Pointer: PSW bits 0, 1 and 2 

The Program Status Word which has bits assigned to status flags as follows: 
7 6 5 4 3 2 10 -^ Bit No. 



S 

DATA 

DEV 

PORT 

ADDR 

ADDR8 

[] - 

[[]] 

{[]) 
([]) 



AC 



FO 



F1 



SP2 



SP1 



SPOl 



PSW bit C, FO or F1 

8-bit immediate data 

An I/O device 

I/O Port PI, P2orBUS 

An 1 1-bit address, specifying a data memory byte 

The low-order eight bits of a memory address 

Contents of location identified within brackets 

Scratchpad memory byte addressed by location identified within brackets 

External memory byte addressed by location identified within brackets 

Program memory byte addressed by location identified within brackets 



6-33 



— Move data in direction of arrow 

' ' Exchange contents of locations on either side of arrow 

+ Add 

Subtract 

A AND 

V OR 

V Exclusive-OR 
BUS Bus I/O port 
PI I/O Port 1 
P2 I/O Port 2 

EP 8243 Expander Port P4, P5, P6 or P7 

PN PI or P2 



6-34 



ADAM OSBORNE & ASSOCIATES. INCORPORATED 



Table 6-2. A Summary of 8048 Microcomputer Instruction Set 



TYPE 


MNEMONIC 


OPERANDISI 


8021 


8041' 


8048 
8049 


BYTES 


STATUS 


OPERATION PERFORMED 


C 


AC 


O 


ANL 

AMD 

IN 

IN 

INS 
MOVD 
MOVD 

ORL 
ORLD 

OUT 
OUTL 


PORT.#DATA 

EP,A 

A,PN 
A.DBB 
A,BUS 

A,EP 

EP,A 
PORT,#DATA 

EP,A 
DBB.A 
PORT,A 








2 






[F^Tl — CPORT] ADATA 

AND immediate data with |/0 Port PI, P2 or BUS 
[EP]-[A03] A[EP] 

AND expander port P4, P5, P6 or P7 with Accumulator bits 0-3 
[A]-[PN] 

Input I/O Port PI or P2 to Accumulator 
[Al— [BUS] 

Input to Accumulator from Data Bus buffer 
[A]-[BUS] 

Input BUS to Accumulator with strobe 
[A03]-[EP] 

Input expander port P4, P5, P6 or P7 to Accumulator bits 0-3 
[EP]-[A03] 

Output Accumulator bits - 3 to expander port P4, P5. P6 or P7 
[ PORT] — [ PORT] V DATA 

OR immediate data with I/O Port PI, P2 or BUS 
[EP]-[A03]V [EP] 

OR Accumulator bits 0-3 with expander port P4, P5. P6 or P7 
[BUS]-[A] 

Output from Accumulator to Data Bus buffer 
[PORT]-[A] 

Output Accumulator contents to I/O Port PI, P2 (or BUS 8048, 8049 only) 


Ul 

O 

z 

lU 

cc 

lU 

u. 

K 

> 
e 
O 

> 

E 
< 

s 

E 

a. 


MOV 
MOV 
MOVP 

M0VP3 

MOVX 
MOVX 
XCH 
XCHD 


Aj@R 
e«,A 
A,@A 

A,(a>A 

A@R 
@R,A 

A.(aR 














[A]-[[R]] 
Load contents of scratchpad byte addressed by RO or R1 into Accumulator 

[[R]]-(A] 
Store Accumulator contents in scratchpad byte addressed by RO or R1 

[A]-([PCH] [A]) 
Load into the Accumulator the contents of the program memory byte addressed by the Ac- 
cumulator and Program Counter bits 8-11. 

tA]-(3[A]) 
Load into the Accumulator the contents of the program memory byte with binary-.address 
001 1XXXXXXXX where XXXXXXXX represents initial Accumulator contents. 

[Al-!(Rli 
Load contents of external data memory byte addressed by RO or R1 into Accumulator 

:[R]1-(A) 
Store Accumulator contents in extendi data memory byte addressed by RO or R1 . 

lAl [(Rll 

Exchange contents of Accumulator and scratchpad iTMmory byte addressed by RO or R1 

[A03] [[R1031 

Exchange contents of Accumulator bits 0-3 with bits - 3 of scratchpad memory byte ad- 
dressed by PO or R1 



Table 6-2. A Summary of 8048 Microcomputer Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


8021 


8041 


8048 
8049 


BYTES 


STATUS 


OPERATION PERFORMED 


C 


AC 


111 
U 

z 

Ul 

E 

lu ►; 

>- lU 

oe Q. 
o o 

1- 
li 

5^ 

Q ~ 

Z 

o 
o 
111 

V) 


ADD 
ADDC 
ANL 
ORL 
XRL 
INC 












X 
X 


X 
X 


[A1-[A1+[IR11 

Add contents of scratchpad byte addressed by RO or R1 to Accumulator 
[A1-[A1+[[R)1+IC] 

Add contents of scratchpad byte addressed by RO or R1, plus Carry, to Accumulator 
[A)-[A]A[[RI1 

AND contents of scratchpad byte addressed by RO or R1 with Accumulator 
[A1-(A1V([R11 

OR contents of scratchpad byte addressed by RO or R1 with Accumulator 
[Al-[A1V-[[R1I 

Exclusive OR contents of scratch(>ad byte addressed by RO or R1 with Accumulator 
[[R11-[[RJ1 + 1 

Increment the contents of the scratchpad byte addressed by RO or Rl 


111 

5 
111 


MOV 
MOV 
















[REGl — DATA 

Load immediate data into Accumulator, or Register RO. Rl. R2. R3, R4. R5. R6 or R7 
[[RU-DATA 

Load immediate data into scratchpad byte addressed by RO or Rl 


a. 
-1 


JMP 
JMPP 

SEL 
SEL 


ADDR 
@A 

MBO 
MB1 














[PC10I — ADDR 

Jump to instruction in current 2K block having label ADDR 
[PC1-[PCH][A]. [PCL]-( [PCHHA]) 

Load into the eight low order Program Counter bits the contents of the program memory byte 
addressed by the Accumulator and the four hglh order Program Counter bits. 
With the next JMP or CALL instruction, reset the high order bit of PC to 0. thus selecting first 2K 
program memory bytes. 

With the next JMP or CALL instruction, set high order bit of PC to 1. thus selecting second 2K 
program memory bytes. 


Z 

oe 
1- 

Ul 

oc 

Q 

z 
< 

-1 
-1 
< 

O 

Ul 

Z 
H 
3 

§ 
CO 

3 

(/> 


CALL 
RET 
RETR 


ADDR 










X 


X 


STACK - STATUS + [PC), (SPl-[SP]+1. [PCl-ADDR 

Call subroutine at specified address. 
[PCI — STACK. [SPl — [SPl-1 

Return from subroutine without restoring status 
[ PC] + STATUS -STACK. [SP]-[SPl-1 

Return from subroutine and restore status 



ADAM OSBORNE & ASSOCIATES. INCORPORATED 







Table 6-2. A Summary of 8048 Microcomputer Instruction Set (Continued) 


TYPE 


MNEMONIC 


OPERAND(SI 


8021 


8041 


8048 
8049 


BYTES 


STATUS 


OPERATION PERFORMED 


C 


AC 




ADD 


A,#DATA 


X 


X 


X 


2 


X 


X 


IA].-[A] + DATA 


UI 


ADDC 


A,#DATA 


X 


X 


X 


^ 2 


X 


X 


Add immediate data to Accumulator 
[A]>-[Al + DATA+ [CI 


UJ 

-Q. 
O 
UI 


ANL 


A,#DATA 


X 


X 


X 


2 






Add immediate data plus Carry to Accumulator 
[A]— [A] A DATA 


5 


















AND immediate data with Accumulator contents 


O 


ORL 


A,#DATA 


X 


X 


X 


2 






lA] — [AlVDATA 


UJ 


XRL 


A,#DATA 


X 


X 


X 


2 






OR immediate data with Accumulator contents 
[A]-[Al¥DATA 
Exclusive OR immediate data with Accumulator contents 




DJNZ 


RN,ADDR8 








2 






[RN] — [RNl-1. If [RNl ^0. [PCLl— ADDR8 
Decrement Register RO, R1. R2, R3. R4. R5. R6 or R7. If the result is not 0. branch to ADDR8 on 




JBb 


ADDR8 








2 






the current program memory page. 
[PCLl— ADDR8 
Jump on current page if Accumulator bit b is 1. b must be 0, 1. 2. 3, 4. 5. 6 or 7 




JC 


ADDR8 








2 






[PCLl — ADDR8 




JFO 


ADDR8 








2 






jdump on current page if Carry is 1 
[PCLl — ADDR8 




JF1 


ADDR8 








2 






Jump on current page if flag FO is 1 
[PCLl — ADDR8 


z 


JNC 


ADDR8 








2 






Jump on current page if flag F1 is 1 
[PCLl — ADPR8 


o 

Q 


JNI 


ADDR8 








2 






Jump on current page if Carry is 
[PCLl — ADDR8 


z 
o 
o 


JNIBF 


-ADDR8 








2 






Jump on current page if interrupt request input is 
[PCLl— ADDR8 


z 
o 

Q. 


JNTO 


ADDR8 








2 






- Jump if IBF flag is 
[PCLl — ADDR8 


-> 


JNTl 
JNZ 
JOBF 
JTF 

JTO 
JT1 
JZ 


ADDR8 
ADDR8 
ADDR8 
ADDR8 

ADDR8 
ADDR8 
ADDR8 








2 
2 
2 
2 

2 
2 
2 






' ~ Jump on current page if TO input is 
[PCLl— ADDR8 

Jump on current page if T1 input is 
[PCLl — ADDR8 

Jump on current page if Accumulator contents is nonzero 
[PCLl— ADDR8 

Jump if DBF flag is 1 
[PCLl — ADDR8 

Jump on current page if timer has timed out, that is, if timer flag is 1. The tinner flag is reset. to 

by this instruction. 
[PCLl — ADDR8 

Jump on current page if TO input is 1 
[PCLl — ADDR8 

Jump t>n current page if T1 input is 1 
[PCLl — ADbR8 

Jump on current page if Accumulator contents are zero 



Table 6-2. A Summary of 8048 Microcomputer Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERANDISI 


8021 


8041 


8048 
8049 


BYTES 


STATUS 




nocDA-rmivi ocacrsoAMcn 










C 


AC 


wri t-iiJ-«iiwiv f-k-iii <./nivibk# 


UJ 

> 


MOV 


A.RN 








1 






[A]-[RN1 


Si 


















Move the contents of a general purpose register to the Accumulator 


MOV 


RN.A 








1 






[RNl-EA] 


2 lU 


















Move the Accumulator contents to a general purpose register 


lU » 

UJ 


XCH 


A.RN 








1 






[A] (RNl 


















Exchange the Accumulator contents with the contents of a gerxeral purpose register 




ADD 


A.RN 








1 


X 


X 


[A] — [A1+ (RNI 


oc 


















Add the contents of a general purpose register to the Accumulator 


Ul 


ADDC 


A.RN 








1 


X 


X 


[A]-[A]+[RN]+[C] 


5 S" 


















Add the contents of a general purpose register, plus Carry, to the Accumulator 


"J 1; 


ANL 


A.RN 








1 






[A]-[A1A[RN1 


E UJ 

UJ A 


















AND the contents of a general purpose register with the Accumulator 


UJ (L 

« ° 


ORL 


A.RN 








1 






[A] — [A]V[RN1 


a 


















OR the contents of a general purpose register with the Accumulator 


UJ 

oc 


XRL 


A.RN 








1 






(A]-[A]V-[RN] 
Exclusive -OR the contents of a general purpose register with the Accumulator 




CLR 


A 








1 






[Al-0 
Zero the Accumulator 




GPL 


A 








1 






[A]-[A] 
Complement the Accumulator 




DAA 










1 






Decimal adjust Accumulator contents 




DEC 


REG 








1 






[REG]— [REGl-1 
Decrement the contents of the Acrumulator or general purpose register. 




INC 


REG 








1 






The 8021 can only decrement Accumulator contents. 
[REGl — [REGl + 1 


UJ 

(- 
< 

K 
UJ 

a. 
o 

oc 

UJ 

h- 
M 

5 

UJ 

oc 


















Increment the contents of the Accumulator or general purpose register 


RL 
RLC 
RR 


A 
A 
A 








1 

1 
1 


X 




Rotate Accumulator left 










^^nl 


h- 


f- 


f- 


1- 


h- 


t- 


h- 


-^ 


Rotate Accumulator left through Carry 




i^rt" 






^ 


t- 


-r^ 


K— 


1- 


h- 


h- ■ 


— ' 


1— J" 

Rotate Accumulator right 














1 


^ 


—4 


% 


-4 


-1 


-4 


-i H 











ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 6-2. A SummatY of 8048 Microcomputer Instruction Set (Continued) 



OPERAND(S) 



8048 
8049 



STATUS 



OPERATION PERFORMED 



SEL 
SEL 



BBC 
RBI 



Rotate Accumulator right through Carry 



f^^&:^^^^^ 



Select register bank 
Select register bank 1 

Swap Accumulator nibbles 



(Al 



.DIS 
EN 
DIS 
EN 



TCNTI 
TCNTI 

I 

I 



Disable timer interrupt 
Enable timer interrupt 
Disable external interrupt 
Enable external interrupts 



ENTO 
MOV 

MOV 

STOP 
STRT 
STRT 



■CLK 
A,T 

T,A 

TCNT 
CNT 

T 



Enable timer output on TO until next system reset 
[A1-[T1 

Read timer/counter 
[Tl-[A] 

Load timer/counter 
Stop timer/counter 
Start counter 
Start timer 



CLR 
CPL 
MOV 

MOV 



S 
S 

A,PSW 

PSW,A 



Clear PSW bit C, TO or F1. 8021 can only clear Carry. 

Complement PSW bit C, FOor F1. 8021 can only complement Carry. 

[Al — [PSWl 

Move Program Status Word contents to the Accumulator 
IPSWI— lAl 

Move Accumulator contents to the Program Status Word 

No Operation 



The following symbols are used in Table 6-3: 

bbb Three bits designating which bit of the Accumulator is to be tested. 

ee Two bits designating an 8243 Expander port: 



00 ■ 


■ P4 


01 • 


■ P5 


10 ■ 


- P6 


11 ■ 


■ P7 



k One bit selecting a memory or register bank: 

MBO or RBO 

1 MB1 or RBI 

MM Eight bits of immediate data 

nnn Three bits designating one of the eight general purpose registers 

pp Two bits designating one of the on-chip I/O ports: 

00 - BUS 

01 - PI 
10 - P2 

qq Two bits designating either I/O Port 1 or I/O Port 2: 

01 - PI 

10 - P2 
r One bit selecting a pointer register: 

- RO 

1 - R1 

XXX The high-order three bits of a program memory address 
XX Th|e low-order eight bits of a program memory address 



6-40 







Table 6-3. 8048 Series Instruction Set Object Codes 






INSTRUCTION 


OBJECT CODE 


BYTES 


MACHINE 
CYCLES 


INSTRUCTION 


OBJECT CODE 


BYTES 


MACHINE 
CYCLES 


ADO 


A.RN 


OllOlnnn 






JOBF ADDR8 


86 XX 


2 


2 


ADD 


A.<fm 


OllOOOOr 






JTF ADDRu 


16 XX 


2 


2' 


ADD 


A.#DATA 


03 MM 




2 


JTO ADDR8 


36 XX 


2 


2 


ADDC 


A,RN 


Onilnnn 






JT1 ADDR8 


56 XX 


2 


2 


ADDC 


A.®R 


omooor 






JZ ADDR8 


C6 XX 


2 


2 


ADDC 


A.#DATA 


13 MM 




2 


MOV A.#DATA 


23 MM 




2 


ANL 


A.RN 


0101 1nnn 






MOV A.PSW 


C7 




1 


ANL 


A.iin 


OlOIOOOr 






MOV A.RN 


lininnn 




1 


ANL 


A.#DATA 


53 MM 




2 


MOV AAin 


iniOOOr 




1 


ANL 


PORT,#DATA 


1001 lOpp 
MM 




2 


MOV A.T 
MOV PSW.A 


42 
D7 




1 
1 


ANLD 


EP.A 


100111ee 




2 


MOV RN.A 


lOIOInnn 




1 


CALL 


ADDR 


■xxxlOlOO 
XX 




2 


MOV RN.#DATA 


101 linn 
MM 




2 


CLR 


A 


27 






MOV m,A 


lOIOOOOr 




1 


CLR 


C 


97 






MOV iCR.ttOAJA 


lOIIOOOr 




2 


CLR 


F1 


A5 








MM 






CLR 


FO 


85 






MOV T,A 


62 




1 


CPL 


A 


37 






MOVD A.EP 


00001 lee 




2 


CPL 


C 


A7 






MOVD EP.A 


OOrillee 




2 


CPL 


FO 


95 






MOVP A.?«A 


A3 




2 


CPL 


F1 


B5 






M0VP3 A,«A 


E3 




2_ 


dA 


A 


57 






MOVX A.iOH 


lOOOOOOr 




2 


DEC 


A 


07 






MOVX m.A 


lOOIOOOr 




2 


DEC 


RN 


llOOInnn 






NOP 


00 




1 


OIS 


1 


15 






ORL A.RN 


OlOOInnn 




1 


DIS 


TCNTI 


35 






ORL A.i«R 


OlOOOOOr 




1 


DJNZ 


. RN.ADDRS 


•IllOlrrr 






ORL A. #DATA 


43 MM 




2 






XX 






ORL PORT.#DATA 


lOOOIOpp 




2 


EN 


1 


05 








MM 






EN 


TCNTI 


25 






ORLD EP.A 


lOOOIIee 




2 


ENTO 


CLK 


75 






OUT DBB.A 


02 




1 


IN 


A.PN 


OOOOIOqq 






OUTL BUS.A 


02 




2 


IN 


A.DBB 


22 






OUTL PN.A 


OOinOqq 




2 


INC 


a' 


17 






RET 


83 ■ 




2 


INC 


RN 


0001 Innn 






RETR 


93 




2 


INC 


'fR 


OOOIOOOr 






RL A 


E7 




1 


INS 


a.bus 


03 




2 


RLC A 


F7 




1 


JBb 


ADDR8 


bbblOOlO 
XX 




2 


RR A 
RRC A 


77 
67 




1 
l' 


JC 


ADDR8 


F6 XX 




2 


SEL MBk 


IllkOIOI 




1 


JFO 


ADDR8 


B6 XX 




2 


SEL RBk 


llOkOIOI 




1 


JF1 


ADDR8 


76 XX 




2 


STOP TCNT 


65 




1 


JMP 


ADDR 


xxxOOlOO 
XX 




2 


STRT CNT 
STRT T 


45 
55 




1 
1 


JMPP 


iCA 


B3 




2 


SWAP A 


47 




1 


JNC 


ADDR8 


E6 XX 




2 


XCH A.RN 


OOlOlnnn 




1 


JNI 


ADDR8 


86 XX 


2 


2 


xcH A. m 


OOlOOOOr 




1 


JNIBF 


ADDR8 


D6 XX 


2 


2 


XCHD A. m 


OOllOOOr 




1 


JNTO 


ADDR8 


26 XX 


2 


2 


XRL A.RN 


1101 Innn 


' 


1 


JNT1 


ADDR8 


46 XX 


2 


2 


XRL A."fl 


llOIOOOr 




1 


JNZ 


ADDR8 


96 XX 


2 


2 


XRL A. # DATA 


D3 MM 




2 



THE 8041 SLAVE MICROCOMPUTER 

This device is also referred to in Intel literature as a Universal Programmable Interface (UPI); it represents a sim- 
ple variation of the 8048 microcomputer. 

The 8741 is a slave variation of the 8748 microcomputer. 

This discussion of the 8041 and 8741 slave microcomputers explains differences as compared to the 8048 and 
8748; you should therefore read the following pages after reading the 8048 and 8748 descriptions. 



6-41 



AN 8041 FUNCTIONAL OVERVIEW 

The principal difference between the 8048 and the 8041 is the fact that the 8041 Data Bus and I/O Port are 
used exclusively to communicate with a master microprocessor. The 8041 generates no external Address or 
Data Bus, so on-chip 8041 program memory and scratchpad data memory cannot be expanded. 

External interrupt logic, which is available on the 8048, is not available on an 8041; the 8041 uses this logic as 
a handshaking interrupt for data input from the master microprocessor. 

8048 and 8041 logic are compared functionally in Figure 6-15. 



P10- P17 
\l 1/ 



,D0 - D7 



8048, but 

not 8041 

Program Counter , 

may be output 

on P23-P20 

plus D7-D0 



P20 - P27 



Interrupt request (8048) 

or chip select (8041) 

Systern reset' 

PROM/Expander strobe 

CPU/Memory Separate 

External Crystal < 

Clock (8048 and 8041) and 
address latch (8048 only) 

Program memory enable output (8048) 
,or Address select input (8041) 
Single Step- 
Read strobe-« 

Write strobe-" 

Test input (8048 or 8041) 
Clock output (8048 only)" 
Test or event counter input - 




<^ 



(^ 



C:^ 



INT or CS 



RESET 

PROG 

EA 

XTAL1 

XTAL2 

ALE or SYNC 

PSEN or AO 

SS 

RD 

WR 

TO 

T1 



C 



C^ 



C=C> 



Program Counter 
8048 = 12 bits 
8041 = 10 bits 



^ 



1024 X 8 Bits 

8048 or 
8041 = ROM 

8748 or 
8741 =EPRQM 



c 



:> 



Program 
Status Word 



Arithmetic And 
Logic Unit, 
Control Unit 

and Instruction 
Register 



c 



:;> 



c=^ 



Accumulator 



64 X 8 Bits 
RAM 



C^ 



Counter/ Timer 



Figure 6-15. A Comparison of 8048 and 8041 Functional Logic 



6-42 



z 
c 
o 
m 
tf> 
o 

< 
o 
< 



Communications between an 8041 and a master microprocessor are very limited. Data must be transferred byte- 
by-byte under program control, with nearly all handshaking protocol being implemented via program logic. You must 
therefore define the protocol within the logic of your 8041 and master microprocessor programs. A rigid protocol is 
absolutely necessary, since the 8041 offers no protection against data transfer contentions. 

8041 DATA BUS LOGIC 

8041 Data Bus logic may be illustrated conceptually as follows: 



Master 
Microprocessor 



c 







c 



c 





^ 



8041 LOGIC 



Buffer 
Status register 



Connected 

as follows: 

F1 - Bit 3 

FO - Bit 2 

IBF - Bit 1 

OBF - Bit 



:; 



::}<» 



IBF 
OBF 



In reality, the Data Out buffer and the Data In buffer are a single piece of logic; however, operations occur (to 
some extent) as though there were two separate buffers. 

A master microprocessor will access an 8041 as two I/O ports or two memory locations. These locations are iden- 
tified via chip select (CS) and address (AO) input signals as follows: 



CS AO 



Read from Data Out 
I buffer 

Write to Data In buffer 
I and reset 

^F1 Buffer status to 
'Read from Buffer 
I Status register 
.Write to Data In buffer 
land set 
L F1 Buffer status to 1 



6-43 



"Read" and "Write" above refer to master microprocessor operations. 

The 8041 accesses the Data Bus buffer register as I/O Port 0. The Status register is inaccessible to the 8041 as an 
addressable I/O port; however, there are specific 8041 instructions that access the FO and F1 Buffer Status bits. 

The four Buffer Status register bits may be defined as follows: 

OBF is the output bufferfull flag. This flag is automatically set to 1 when the 8041 outputs data 



8041 
BUFFER 
STATUS 
REGISTER 



to the Data Out buffer. When the master microprocessor reads the contents of the Data Out 
buffer, the OBF flag is reset to 0. 

IBF is the input buffer full flag. This flag is set to 1 when the master microprocessor writes data 

into the Data In buffer. This flag is reset to when the 8041 subsequently reads data from the Data In buffer. 

FO is a general-purpose flag which can be set or reset by the 8041 . The master microprocessor can sample FO by read- 
ing Buffer Status register contents. 

F1 is another general-purpose flag which can be modified by the 8041. F1 is also set or reset to the level of AO 
whenever the master microprocessor writes data into the Data In buffer. The master microprocessor can sample F1 by 
reading Buffer Status register contents. 

When the master microprocessor reads buffer status, flags appear on the Data Bus lines as follows: 



D7 

> Undefined 



D4 

D3^^ F1 

02 FO 

D1 IBF 

DO OBF 

Whenever the 8041 outputs data to I/O Port 0. the data is stored in the Data Out buffer and the OBF status flag is set to 
1 ; when the master microprocessor subsequently reads the contents of the Data Out buffer, the OBF flag is reset to 0. 

When themaster microprocessor writes to the 8041, the data is loaded into the Data In buffer, the IBF status is set to 1 
and an interrupt request is generated within the 8041 ; this interrupt request replaces the external interrupt logic of the 
8048. The IBF status is cleared when the 8041 subsequently reads the contents of the Data In buffer. 

The FO flag is set or reset by the 8041 using appropriate instructions. There is no predefined manner in which this flag 
is interpreted; your program logic can use this flag in any way. 

The F1 flag is set to the level of the AO signal input whenever the master microprocessor writes a control byte into the 
Data In buffer. In reality, there is no difference between a control byte and a data byte; that is to say, there is no pre- 
defined way in which the 8041 will interpret the contents of the Data In buffer based on the F1 flag level. 

The master microprocessor reads data which has been output by the 8041; the master microprocessor cannot read 
back data which it wrote to the 8041. 

The 8041 inputs from I/O Port data that was written by the master microprocessor; the 8041 cannot read back data 
which it previously output to 1/0 Port 0. 

8041 I/O PORTS ONE AND TWO 

Physically, 8041 I/O Ports 1 and 2 have logic which is identical to the 8048. Thus the pseudo-bidirectional I/O port 
characteristics described for the 8048 I/O Ports 1 and 2 apply also to the 8041 I/O Ports 1 and 2. 

Note that the 8041 does not generate an external Address Bus, therefore I/O Port 2 pins P20 - P23 never output ad- 
dress information. 

8041 AND 8741 PROGRAMMABLE REGISTERS 

The 8041 and 8741 have a 1 0-bit Program Counter. The 8048 and 8748 have a 1 2-bit Program Counter. These are the 
only differences between the 8041 series and 8048 series programmable registers. 

8041 AND 8741 ADDRESSING MODES 

The 8041 and 8741 can address only on-chip memory. This includes the 1024 bytes of on-chip program memory and 
64 bytes of on-chip scratchpad data memory. 8041 and 8741 addressing modes are identical to the 8048 and 8748 
on-chip memory addressing modes. Of course, the 8048 and 8748 external memory addressing modes will not apply 
to the 8041 or the 8741. 



6-44 



8041 AND 8741 STATUS 

The 8041 and 8741 slave microcomputers have two Status registers. First, there is the Buffer Status register, 
which is part of the Data Bus logic. We have already described this 4-bit Status register. The 8041 and 8741 
also have the 8-bit Program Status Word described for the 8048 series microcomputers. 8041 and 8048 Pro- 
gram Status Words are identical. 

8041 AND 8741 SLAVE MICROCOMPUTER OPERATING MODES 

The 8041 and 8741 can be operated in Internal Execution mode and Debug mode; in addition, the 8741 can be 
operated in Single Stepping mode. Programming mode and Verification mode. Neither the 8041 nor the 8741 
can be operated in External Memory Access mode. 

8041 AND 8741 PINS AND SIGNALS 

There are a few differences between 8041 and 8741 pins and signals, as compared to the 8048 and 8748. 
Figure 6-16 defines 8041 and 8741 pins and signals: the four changed signals are shaded. 



o 

m 

CO 

O 

< 

< 
© 




PIN NAME 
DBO - DB7 

P10- P17 
P20 - P27 

SYNC 
RD 

Wr 

AO 

cs 

EA 
TO 
T1 



RESET 

vss 
vcc 
Vdd 

PROG 



8041 
8741 




XTAL1, XTAL2 



DESCRIPTION 

Bidirectional I/O port, Data Bus and 

low-order eight Address Bus lines 

I/O Port 1 

I/O Port 2, P20 - P23 also serves as four 

high-order Address Bus lines 

External clock signal 

Data memory read control 

Data memory write control 

Address select 

Chip select 

External program memory access 

Single step control 

Test input and 

Program/Verify mode select 

Test input, optional event counter input 

System reset and EPROM address latch 

Ground 

+ 5V 

+ 25V to program 8741. + 5V standby 

for 8041 RAM 

+ 25V input to program 8741. Control 

output for 4-bit I/O 

External crystal connections 



TYPE , 
Bidirectional, tristate 

Quasibidirectional 
Quasibidirectional 

Output , 

Output 

Output 

Input 

Input 

Input 

Input 

Bidirectional 

Input 
Input 



Bidirectional 



Figure 6-16. 8041 and 8741 Microconnputer Pins and Signals 



6-45 



CS and AO are the device select inputs which we have already described. 

SYNC is an external synchronizing signal which is output once per machine cycle. 

TO cannot be connected to the internal system clock; other uses of TO are the same for the 8041/8741 and the 
8048/8748. 

All other signals are identical to the 8048 and 8748 as previously described. Note, however, that no addresses are out- 
put on the DBO - DB7 pins or the P20 - P23 pins. 

8041 SERIES TIMING AND INSTRUCTION EXECUTION 

The 8041/8741 clocl< signals and instruction execution timing logic is identical to the 8048/8748. Of course, the 8041 
and 8741 have no external memory reference instructions, therefore timing associated with these instructions will not 
apply. 

8741 SINGLE STEPPING AND PROGRAMMING MODE 

Single Stepping and Programming modes of operation are available only with the 8741; the 8041 cannot be 
operated in these modes. 

There are, of necessity, some differences between 8741 and 8748 Single Stepping and Programming modes; 
this is because the 8741 has no ALE signal and no output Address Bus. 

In Single Stepping mode, the 8741 is stopped by applying a low SS input when SYNC is low. 

The 8741 responds by stopping during the next instruction fetch. At this time, SYNC is maintained high. The address 
of the next instruction to be accessed appears at I/O Port 1 and the low-order two bits of I/O Port 2. This condition is 
maintained until SS is input high again. Timing may be illustrated as follows: 



SYNC 




There are also some minor differences between 8741 and 8748 Programming modes. The ten-step 8741 pro- 
gramming sequence is therefore given below. Differences as compared to the 8748 are shaded. 



Step 1) Initially -f5V is input at Vqd, CS, TO and EA. RESET and lA^ are held at ground. Under these conditions you 
insert the 8741 into the programming socket. You must make certain to insert the 8741 correctly. If you 
insert the 8741 incorrectly you will destroy it. 

Step 2) TO is pulled to ground; this selects Programming mode. 

Step 3) +25V is applied to EA. This activates Programming mode. 

Step 4) A 10-bit memory address is applied via DBO - DB7 and P20 - P21. Remember, there are 1024 bytes of pro- 
gram memory on the 8741 device. The low-order eight address bits are input via DBO - DB7 while the two 
high-order address bits are input via P20 and P21. 



Step 5) +5V is applied at RESET. This latches the address. 

Step 6) The data to be written into the addressed programmed memory byte is input at DBO - DB7. 

Step 7) In order to write the data into the addressed program memory byte apply -I-25V to Vdd- then ground PROG, 
then apply a -f25V pulse at PROG; the -i-25V pulse at PROG must last at least 50 milliseconds. 

Step 8) Now reduce Vpo to -I-5V. Programming is complete and verification is about to begin. 

Step 9) In order to verify the data just written, apply -I-5V to the TO input. This selects Verify mode. 

Step 10) As soon as Verify mode has been selected, the data just written is output on DBO - DB7. You must read and 
verify this data using appropriate external circuitry. Verification is now complete. 



6-46 



o 

< 
o 
< 



8041 INPUT/OUTPUT PROGRAMMING 

The only differences between 8041/8741 and 8048/8748 input/output programming are those which result 
from the unique 8041 I/O Port logic — which we have described. 

8041 COUNTER/TIMER OPERATIONS 

8041 series and 8048 series counter/timer operations are identical. 

8041 INTERRUPT LOGIC 

The entire external interrupt logic of the 8048 has been converted in the 8041/8741 Data Bus handshaking in- 
terrupt logic. This interrupt request occurs every time a master microprocessor writes to either of the 
8041/8741 addressable locations. 

In order to generate external interrupt logic at an 8041 or 8741 you must use the counter/timer. By loading the 
counter/timer with an initial value of FF-j 5 and operating the counter/timer in Counter mode, the first high-to-low input 
transition on J1 will generate a Timer interrupt request. Of course, i| you are using the counter/timer in this way, you 
cannot use it for any of its normal functions. ' ; 

PROGRAMMING 8048-8041 DATA TRANSFERS 

The only complexity associated with programming an 8041 involves data transfers between the 8041 and a 
master microcomputer. Programming these data transfers is not straightforward. 

We described earlier how there are separate data paths for data entering or leaving the 8041 via the Data Bus buffer. 
Nevertheless, if a master- microcomputer attempts to write to the 8041/8741 while the 8041/8741 is 
simultaneously outputting to I/O Port 0, then there will be an undefined result. This is unfortunate, since there are 
no signals or indicators of any kind allowing the master microcomputer to lock out the 8041/8741; nor can the 
8041/8741 lock out the master microcomputer. Lock out logic iT|ust be implemented by you, via your program 
logic. Program logic must also make sure that data written by "^■)' master microcomputer has been read by the 
8041/8741 before the master microcomputer writes any new data; similarly, the 8041/8741 must make sure that any 
data it has output to I/O Port has been read by the master microcomputer before the 8041/8741 attempts to output 
new data to I/O Port 0. 

Let us look at the programming steps required for error free data transfers between the 8041/8741 and a 
master microcomputer. Programming examples assume an 8048 is the master microprocessor because the 8048 is 
described in this chapter and has an instruction set that is similar to the 8041. In reality, the master microprocessor is 
likely to be an 8085-type device. 

The master microcomputer can make sure that it does not overwrite data by testing both the IBF and the OBF flags; 
that is to say, the master microcomputer will, not attempt to write data to the 8041/8741 if prior data it wrote is waiting 
to be read by the 8041/8741, or if data output by the 8041/8741 is waiting to be read by the master microcomputer. 
The following master microcomputer output instruction sequence will suffice: 

MOV 0,ADDR-f 1 ;LOAD 8041 ADDRESS INTO 8048 REGISTER RO 



MOVX 


A,@0 


RRC 


A 


JC 


NEXT 


RRC 


A 


JC 


READ 


DEC 






LOAD STATUS 

TEST LOW ORDER (OBF) FLAG 

IF IT IS 1. DO NOT WRITE NEW DATA 

TEST NEXT BIT (IBF) FLAG 

IF IT IS 1, DATA IS WAITING TO BE READ 

OK TO OUTPUT 



6-47 



But this scheme does not prevent the master microcomputer and the 8041/8741 from simultaneously accessing the 
Data Bus buffer. This must be guaranteed by 8041/8741 lock out logic. The 8041/8741 can use programming logic or 
interrupt logic to lock out the master microcomputer. Using programming logic, the 8041/8741 will use the FO flag to 
identify those time intervals when the master microcomputer is free to access the Data Bus buffer. Now any 8048 
master microcomputer instruction sequence that accesses the 8041/8741 will first read 8041/8741 status and test the 
FO flag. If this flag is "false", no data transfer must occur. Continuing our master microprocessor instruction sequence, 
this may be illustrated as follows: 



MOV 



0,ADDR+1 ;LOAD 8041 ADDRESS INTO 8048 REGISTER RO 



TEST MOVX A.@0 iLOAD STATUS 

TEST LOW ORDER (OBF) FLAG 

IF IT IS 1. DO NOT WRITE NEW DATA 

TEST NEXT BIT (IBF) FLAG , 

IF IT IS 1, DATA IS WAITING TO BE READ 

TEST FO FLAG 

IF FO IS 0, MASTER IS LOCKED OUT 

FO IS 1 SO IT IS OK TO OUTPUT DATA 

LOAD DATA TO BE OUTPUT INTO ACCUMULATOR 

OUTPUT DATA TO 8041 

READ RRC A JEST FO FLAG 

IF FO IS 0. MASTER IS LOCKED OUT 
FO IS 1 SO IT IS OK TO READ DATA 
INPUT DATA 
STORE IN SCRATCHPAD 

The instructions above assume that scratchpad register Rl addresses the scratchpad byte out of which written data is 
fetched, or into which read data is stored. 

If there is heavy traffic between an 8041/8741 and a master microcomputer, then the 8041/8741 should use interrupt 
logic to identify times when a master microcomputer can either output data to the 8041/8741 or input data from the 
8041/8741. To do this, one or two 8041/8741 I/O port pins must be set aside as interrupt request generation lines. 
Now the master microcomputer will not access the 8041 /8741 except within an interrupt service routine which is initi- 
ated by an interrupt request arising from one of the two dedicated 8041/8741 I/O port pins. 

Data transfers from the 8041/8741 to the master microcomputer are easy to program. When the 8041/8741 writes to 
I/O Port 0, the OBF flag is set to 1 ; this flag is reset to when a master microcomputer reads data. Thus, the 8041/8741 
simply tests the OBF status before outputting data; here are appropriate instructions: 

CLR FO ;ZERO FO TO LOCK OUT THE MASTER MICROPROCESSOR 

JOBF NEXT ;TEST OBF FLAG 

OUT DBB,A ;IF IT IS ZERO, OUTPUT NEXT DATA BYTE 

CPL FO ;SET FO TO ALLOW MASTER MICROPROCESSOR ACCESS 



MOVX 


A.@0 


RRC 


A 


JC 


NEXT 


RRC 


A 


JC 


READ 


RRC 


A 


JNC 


TEST 


DEC 





MOV 


A.@1 


MOVX 


@0,A 


JMP 


OUT 


RRC 


A 


JNC 


TEST 


DEC 





MOVX 


A.@0 


MOV 


@1.A 


JMP 


OUT 



NEXT 



6-48 



The 8041/8741can respond to data arriving from the master microcomputer by using polling logic or interrupt logic. If 
polling logic is used, then the 8041/8741 must test the IBF flag before reading any data that the master microcomputer 
has output, in order to determine whether the master microprocessor has output data or a control code, the 8041/8741 
must also check the F1 flag. Here is an appropriate instruction sequence: 

CLR FO :ZERO FO TO LOCK OUT THE MASTER MICROPROCESSOR 

JNIBF I^EXT JEST FOR DATA WAITING TO BE READ 
JF1 CONT :DATA IS READY TO BE READ. TEST 

; FOR DATA BYTE OR CONTROL BYTE 
IN A,DBB ;READ DATA 

CPL FO ;SET FO TO ALLOW MASTER MICROPROCESSOR ACCESS 



CONT 



IN 
CPL 



A,DBB 
FO 



;READ CONTROL CODE 

;SET FO TO ALLOW MASTER MICROPROCESSOR ACCESS 



o 

m 

(0 

o 

< 

< 
@ 



NEXT 

If 8041/8741 data input logic is interrupt driven, then external interrupts must be left enabled. Now as soon as the 
master microcomputer outputs data to the 8041/8741, an interrupt request will occur, followed by a Call 3 instruction 
being executed. Beginning at memory location 3, the following instruction sequence will initiate the data input inter- 
rupt service routine within the 8041/8741 : 

3 
DTIN 



QRG 
JMP 



;JUMP TO DATA INPUT ROUTINE 



DTIN 



CLR 


FO 


JF1 


CONT 


IN 


A.DBB 



ZERO FO TO LOCK OUT MASTER MICROPROCESSOR 
TEST FOR DATA TYPE 
READ DATA 



CONT 



IN 



A,DBB ;READ, CONTROL CODE 



CPL 
RET 



FO 



;SET FO TO ALLOW MASTER MICROPROCESSOR ACCESS 
;RETURN FROM INTERRUPT SERVICE ROUTINE 



Themastermicroprocessor must not write to the 8041/8741 while data that the 8041/8741 has output is waiting to be 
read; similarly, the 8041/8741 cannot output data |o the master microprocessor while data from the master 
microprocessor is wgiting to be read by the 8041/8741. In each case, prior data will be overwritten and lost. In order to 
prevent this frorp happening, you rnust have appropriate lock out logic. FO is used for this purposp above. 

THE 8041/8741 INSTRUCTION SET 

, ft ■ ■ ^ ,, , ■} {. i ; ..■ 

The 8041/8741 instruction set differs from the 8048/8748 in minor ways only. Tables 6-2 and ^-3 therefore 
summarize the Instruction set for both the 8048 series and 8041 series microcomputers^ 



6-49 



All 8021 I/O Port 
pins have unique 
characteristics 



8048 but not 8021 

Program Counter 

may be output 

on P23 - P20 

plus D7 - DO. 



Interrupt request 

System reset 

PROM/Expander strobe 

CPU/Memory Separate 

External Crystal 

Address latch and clock 

Program Memory 
Enable 

Single Step 

Read strobe 

Write strobe 

Test input or timer output 

Test or event counter Input 



P10-P17 



DO -07 
becomes 
POO - P07 



I P20 - P27 
becomes 
P20 - P23 




<^ 



ts 



!5E 



<:=:> 



CO 



INT 



c 



<^ 



c 



CO 



Program Counter 
8048=12 bits 
8021 = 10 bits 



Program 
Status Word 



c 



CO 



Accumulator 



CO 



Counter/Timer 



^ 



1024 X 8 Bits 
ROiyl 



^ 



Arithmetic and 

Logic Unit, 

Control Unjl 

and Instruction 

Register 



:> 



64 X 8 Bits 

RAM 

8021 has one 

set of registers 

only 



I I All 8021 I/O port pins have unique characteristics 

I ' I These signals are not present in an 8021 



8021 T1 characteristics are unique 



Figure 6-17. A Comparison of 8048 and 8021 Functional Logic 



6-50 



o 

m 

(0 

O 

< 
o 
< 

@ 



THE 8021 SINGLE-CHIP MICROCOMPUTER 

The 8021 is a low-cost subset of the 8048 single-chip microcomputer. Unlike the 8041, the 8021 is hot 
designed to operate as a slave microcomputer. The 8021 is intended for high-volume, low-cost applications 
with limited microcomputer logic requirements. The only easy way in which an 8021 can be expanded is by adding 
an 8243 Input/Output Expander. There is no simple way to increase either 8021 program memory or data memory, over 
and above that which is internal to the 8021. 

This discussion of the 8021 single-chip microcomputer explains differences as compared to the 8048 and 8748; 
you should therefore read the following pages after reading the 8048 and 8748 descriptions. 

AN 8021 FUNCTIONAL OVERVIEW 

The principal difference between the 8048 and the 8021 is the fact that the 8021 has no Data Bus, and I/O Port 
is simply another I/O port. Thus, the only way in whicn an 8021 can communicate with logic beyond the chip itself 
is via its I/O ports, which have no accompanying handshaking control signals. In contrast, the 8041 has I/O Port logic 
designed for two-way communication between the 8041 and a master microprocessor. The 8021 cannot distinguish 
between a master microprocessor or any other extei^nal logic. 

The 8021 has no external interrupt logic and only one Test input, 

Only two control signals are output by the 8021: a synchronizing clock signal and an 8243 Input/Output Expander 
control strobe. 

With these redijced capabilities, the 8021 is packaged bs a 28-pin DIP, in contrast to other members of the 8048 
series, which are packaged as 40-pin DIPs. 

The 8021 can be driven by a crystal oscillator with a maximum 3 MHz frequency. This is half the maximum fre- 
quency of the 8048 and 8041, but equivalent to the maxiirium frequency of the -8 parts. This 3 MHz crystal generates 
10-microsecond machine cycles. Thus, all 8021 instructions execute in either 10 or 20 microseconds. 

Functionally, 8048 and 8021 logic are compared in Figure 6-17. 8021 pins and signals are illustrated in Figure 
6-18. 

8021 I/O PORT PINS 

8021 I/O port piris are referred to as quasi-bidirectional, a term we ajso use to describe 8048 I/O port pins. 8048 
and 8021 I/O poi-t pin logic is identical. 

THE T1 PIN 

When you order an 8021 microcomputer, you can specify one of two configurations for the T1 pin. Electrically, 
these may be illustrated as follows: 



Option A (Zero cross-over sensing) 



CPU 



— o<J-o<^ 




Option B (Pull-up resistor) 



CPU 



External 
logic 




— o<l-o<^ 



Option A allows you to detect the zero cross-over point on slow-moving input signals. Option B, with the pull-up, is 
designed to sense fast changes such as contact switches. 



6-51 




PIN NAME 

POO - P07 

P10-P17 

P20 - P23 

ALE 

PSEN 

T1 



RESET 
XTAL1, XTAL2 

vss 
Vcc 



RESET 
XTAL2 
XTAL1 



DESCRIPTION 

I/O Port 

I/O Port 1 

I/O Port 2 

Ciocksignal 

8243 Control 

Test input, optional 

event counter 

System reset 

External crystal connections 

Ground 

Power 



TYPE 

Quasibidirectional 

Quasibidirectional 

Quasibidirectional 

Output 

Output 

Input 

Input 



Figure 6-18. 8021 Microcomputer Pins and Signals 



THE 8021 RESET INPUT 

When the 8021 is reset, the same internal operations occur as described for the 8048; the Program Counter and 
Program Status Word are cleared and 1 is output to I/O port pins. However, 8021 reset logic has been modified so 
that the 8021 can operate with noisy power supplies. You have one of two options, which may be illustrated as 
follows: 



Option A (Reset when power falls below 1.5V) 



Option B (Operate as long as power will drive chip) 



RESET 



1 



][ 



-OVcc 



RESET 



ImF 
10V 



^l- 

imF 

10V 



OVcc 



In the case of Option A, you connect the diode between reset and ground to force a reset whenever power drops below 
1.5V. Thus, operations will stop while power falls below 1.5V, but when normal power returns operations will restart. 
Since chip operations continue only as long as povver remains high enough to maintain the contents of chip read/write 
locations, this circuit guards against execution with faulty data. By removing the diode, as illustrated in Option B, this 
reset feature is eliminated ahd the 8021 will operate as long as power is sufficient to drive logic internal to the chip. 



6-52 



THE 8021 CLOCK INPUTS 

A crystal Resistor/Capacitor or inductor circuit can be connected to the XTL1 and XTL2 pins to provide the 
needed internal clock signal. The maximum external crystal frequency allowed is 3 MHz. This generates 10-microse- 
cond machine cycles. All instructions execute in 1 or 2 machine cycles. 

THE 8021 TIMER/COUNTER 

o ' 

H Logic associated with the 8021 timer/counter is identical to that which we have described for the 8048. The 

tt ' contents of the Accumulator can be moved to the Counter/Timer register, which is subsequently incremented once ev- 

2 . ery 32 crystal oscillations in Timer mode, or once every high-to-low transition of a T1 input in Counter mode. However, 

o there is no interrupt logic on the 8021, which means that a time-out will not cause an interrupt request to occur. You 

^ must therefore test for a time-out under program control using the JTF (Branch-on-Timer Flag) instruction. 

w' 8021 SCRATCHPAD MEMORY AND PROGRAMMING 

< In addition to the lack of interrupt logic, the 8021 has no Status register and data memory is simplified. 

Instead of having a Status register, the 8021 has a 3-bit Stack Pointer and a single Carry status flag. 

< Data memory consists of eight general purpose registers in scratchpad bytes 0-7, plus a 16-byte Stack which uses 

«8 scratchpad bytes 8-1 7i6- This stack allows subroutines to be nested to a level of 8. The 8021 does not have the second 

2 set of eight registers located in scratchpad bytes 18i6 * 1f^16- ^s is available on the 8048 and the 8041. 

cc 

g The 8021 instruction set is a subset of the 8048 instruction set. In Table 6-1, 8021 instructions are identified. 

CO 

O 

1 THE 8243 INPUT/OUTPUT EXPANDER 

< 

^ This support device expands I/O Port 2 of an 8041 or 8048 series microcomputer to four individually addressable 4-bit 

I/O ports. The 8243 Input/Output Expander is particularly useful in numerical applications where data is transferred in 
4-bit nibbles. 

Figure 6-19 illustrates that part of our general microcomputer system logic which has been implemented on the 8243 
Input/Output Expander. 

The 8243 Input/Output Expander is packaged as a 24-pin DIP. It uses a single -I-5V power supply. All inputs and out- 
puts are TTL-compatible. The device is implemented using N-channel MOS technology. 

8243 INPUT/OUTPUT EXPANDER PINS AND SIGNALS 

The 8243 Input/Output Expander pins and signals are illustrated in Figure 6-20. Functional internal architecture is il- 
lustrated in Figure 6-21. 

P20 - P23 represent the 4-bit bidirectional I/O port or bus connection between the 8243 Input/Output Expander and 
the 8048 series microcomputer. P20 - P23 must be connected to the low-order four pins of the microcomputer I/O Port 
2. Figure 6-22 illustrates the 8243-8048 interface. 

P40 - P43, P50 - P53, P60 - P63 and P70 - P73 provide four bidirectional I/O ports, referred to as Ports 4, 5, 6 and 
7, respectively. These are 4-bit ports via which data is transferred to or from external logic. 

Data being output via one of these four ports is latched and held in a low impedance state. 

Data input is buffered. During a read operation 8243 I/O port pins are sampled — while the read is being executed; 
then I/O port pins are floated. 

CS is the single chip select signal for the 8243 device. CS must be low for the device to be selected. There is no 
specifically defined manner in which CS has to be created; in Figure 6-22 it is shown being decoded off the four high- 
order pins of I/O Port 2. 

PROG is the single control strobe output by the 8048 series microcomputer to time 8243 events. On the falling 
edge of PROG, data input via P20 - P23 is decoded as an I/O port select and operation specification. Resulting 8243 
operations are strobed by the rising edge of PROG. 

There is no Reset input to the 8243. The device is reset when power is first applied, or when |8243 RESET | 

power input at the Vcc P'" drops below -H volt. Following Reset, Port 2 is in Input mode while 

Ports 4, 5, 6 and 7 are floated. The 8243 device will exit the Reset mode on the first high-to-low transition of PROG. 



6-53 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



il 



Interrupt Priority 
Arbitration 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Bus Interface 
Logic 



Accumulator 
Register(s) 



Data Counter<s) 



Stack Pointer 



Program Counter 



Direct Memory 

Access Control 

Logic 



System Bus 



I 



I 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 

Interface Logic 



I/O Ports 
Interface Logic 



Read Only 
Memory 



I/O Ports 



RAM Addressing 

and 
Interface Logic 



Read/Write 
Memory 



Figure 6-19. Logic of the 8243 Input/Output Expander 



6-54 



o 

GO 
CO 
O 

< 

Q 

< 




PIN NAME 

P20 - P23 
P40 - P43 
P50 - P54 
P60 - P64 
P70 - P74 
PROG 
CS 
Vcc, GND 



DESCRIPTION 

Bidirectional I/O Port to CPU 
I/O Port 4 
I/O Port 5 
I/O Port 6 
I/O Port 7 

Address/Data Strobe 
Chip Select 
Power, Ground 



TYPE 

Bidirectional, tristate 
Bidirectional, tristate 
Bidirectional, tristate 
Bidirectional, tristate 
Bidirectional, tristate 
Input 
Input 



Figure 6-20. 8243 Input/Output Expander Pins and Signals 

8243 INPUT/OUTPUT EXPANDER OPERATIONS 

8048 and 8041 series microcomputers have four instructions designed specifically to access an 8243 In- 
put/Output Expander. These instructions are: 

MOVD PN.A 
MOVD A.PN 
ORLD PN.A 
ANLD PN,A 

These are the operations performed: 

1) You can output the low-order four Accumulator bits to I/O Expander Port 4, 5, 6 or 7. Following a write opera- 
tion the four port lines are held in a low impedance state. External logic does not receive any type of "data ready" 
signal after data has been output; however, as illustrated in Figure 6-22, you can easily create such a signal by 
combining PROG and device select logic. 

2) You can input data from Port 4, 5, 6 or 7 of the 8243 device to the four low-order Accumulator bits. Again Figure 
6-22 shows how you can create a strobe signal which tells external logic when to apply data to an I/O port of the 
8243 device. 

3) You can output data from the low-order four Accumulator bits to one of the four 8243 device ports, but instead of 
simply writing to the port, you can AND or OR with data already in the port output latch. That is to say, you per- 
form a Boolean operation between the four low-order Accumulator bits and the data most recently output to the 
8243 port. 

You cannot perform a Boolean operation between the low-order four Accumulator bits and data input to an 
8243 port; the input data is buffered, not latched. You must read the input data to the Accumulator and mask it there. 

8243 device Ports 4, 5, 6 and 7 have been designed to operate continuously as input ports or output ports. If 
you switch a port from input to output, or from output to input, then the first 4-bit data unit written or read will 
be erroneous and should be discarded. 



6-55 



cs 



PROG 



Timing 

and 
Control 



Port 2 



P20 - P23 



IVIultiplexer 



iz 



AND/OR 
LOGIC 



c 



c=> 



c 



c 



;> 



c 



:> 



Output 
Latch 



Input 
Buffer 



P40 - P43 



Port 4 



:> 



Output 
Latch 



Input 
Buffer 



P50 - P53 



Port 5 



:> 



Output 
Latch 



Input 
Buffer 



P60 - P63 



^ 



Port 6 



:> 



Output 
Latch 



Input 
Buffer 



P70 - P73 



Port 7 



Figure 6-21. Functional Diagram of the 8243 Input/Output Expander 



6-56 



8048 
8035 



8748 



PROG 



C 



P20 - P23 



P24 
P27 



^ 



:> 



Device 
Select 



P22 

P23 i— ^ 



I— t>o— » 



^>> 



i>- 



CS 8243 



PROG 



P40 - P43 



P50 - P53 
P60 - P63 
P70 - P73 



I 



5V 



D Q 

7474 

CLK 

CLR 





■READ 



CLR 
J Q1 



K 74107 
CLK 



PRE 



I 



-WRITE 



5V 



CS 



PROG 



P22, P23 



READ 



WRITE 





Figure 6-22. An 8243/8048 Configuration with External Logic Read and Write Strobes 



6-57 



PROG 



^ 



P20 - P23 Float I Instruction 



Float 



Data Out 



PNO - PN3 



Old output data 




Float 



New output data 



8243 

device 

decodes 

instruction 



Figure 6-23. Timing for Data Output to an 8243 Port Via 
an MOVD, ORLD or ANLD Instruction 



PROG 



^ 



P20 - P23 Float I Instruction 



PNO - PN3 



Old input data 




Float 



Data-in 



New input data 




Float 



Figure 6-24. Timing for Data Input from an 8243 Port 

Timing for 8243 port accesses is illustrated in Figures 6-23 and 6-24. 

In each case an instruction is output via P20 - P23 of the 8048 microcomputer on the high-to-low transition of 
PROG. The instruction is decoded as follows: 



P20 


P21 


8243 Port Selec 


ted 


P22 


P23 


Function Defined 








Port 4 










Read from Port 





1 


Port 5 







1 


Write to Port 


1 
1 




1 


Port 6 
Port? 




1 
1 




1 


OR with Port 
AND with Port 



The actual I/O operation within the 8243 device is strobed by the subsequent low-to-high transition of PROG. 

Observe that external logic must transmit data to an 8243 I/O port on the high-to-low transition of PROG. External logic 
must read data output after the low-to-high transition of PROG. These signals to external logic are shown in Figure 
6-22. Let us take a more careful look at this figure. 

The 8243 device sele^ CS is derived in some fashion from the four high-order lines of the 8048 I/O Pqn2. The manner 
in which we decode CS from these four lines is not relevant; however, the fact that we are generating CS in this fashion 
means that any 8243 access instruction must be bracketed by instructions that select and then deselect the 8243 
device. 

It is not a good idea to leave the 8243 device selected when you are not accessing it; therefore do not leave high-order 
bits of I/O Port 2 in a condition that would select the 8243 device while the device is supposed to be idle. 



6-58 



The PROG signal connecting the 8048 to the 8243 requires no explanation. The signal is output by the 8048 with tim- 
ing required by the 8243. 

The READ and WRitE strobes created in Figure 6-22 identify the time at which external logic must either read data 
from an I/O port, or write data to an I/O port; howeyer, the I/O port is not itself identified. The READ and WRITE strobes 
would have to be qualified by P20 and P21 on the high-to-low transition of PROG in order to create READ and WRITE 
strobes specific to any given I/O port. Here, for example, is the logic which would make READ and WRITE specific to I/O 
Port 5: 



z 
oc 
o 
m 

(A 

O 

<' 
o 

< 



PROG 



-£» 




READ- 



•READ 5 



WRITE " 



■ WRITE 5 



Referring to the timing in Figure 6-22, let us first look at the READ strobe. This signal must go true on the high-to-low 
transition of PROG — but only if P22 and P23 are both low. READ can stay high until the device is deselected, provid- 
ing external logic uses the low-to-high transition of READ or timing immediately thereafter, in order to place data at the 
required I/O port — whence it can be read by the 8048. We obtained the required waveform by using the complement 
of CS as a CLEAR input to the READ 7474 flip-flop. Thus while the 8243 device is not selected READ will be low. The 
NOR of P22 and P23 becomes the D input to the READ flip-flop; this input will be hig h only when P22 and P23 are both 
low — and that specifies a Read operation. On the high-to-low transition of PROG, PROG goes low-to-high, and that 
clocks the READ flip-flop Q output high. READ subsequently stays high until CS goes high again, at which point the 
READ flip-flop is cleared and READ goes low. 

A 74107 master-slave flip-flop creates the WRITE pulse. The high-to-low transition of PROG marks the instant at which 
P22 and P23 must be decoded to determine that a non-read operation is in progress, but the actual low-to-high transi- 
tion WRITE must not occur until the subsequent low-to-high transition of PROG. 

The 74107 modifies the 01 output on the trailing edgeof CLK, based on the JK inputs at the leading edgeof CLK; thus 
WRITE logic requirements are met. 



6-59 



DATA SHEETS 

This section contains specific electrical and timing data for the following devices: 

8048/8748/8035 ) 

8049/8039 > One-Chip Microcomputers 

m 8041/8021 ' 

< 8243 I/O Expander 

EC 

o 

0. 

oe 
o 
u 

z 



@ 



6-D1 



8048/8748/8035 



ABSOLUTE MAXIMUM RATINGS* 

Ambient Temperature Under Bias 0°C to 70°C 

Storage Temperature -65°C to +150°C 

Voltage On Any Pin Witli Respect 

to Ground -0.5V to +7V 

Power Dissipation 1.5 Watt 



■COMMENT: 

Stresses above those listed under "Absolute Maximum Ratings" 
may cause permanent damage to the device. This is a stress rating 
only and functional operation ol the device at these or any other 
conditions above those indicated in the operational sections ol this 
specilication is not implied. 



D.C. AND OPERATING CHARACTERISTICS T^ = 0°c to 70°c, Vcc = Vqd = +5V ±io%*, Vss= ov 



Symbol 


Parameter 


Limits 


Unit 


Test Conditions 


Min. 


Typ. 


Max. 


V,L 


Inpilt Low Voltage 

(All ExfceptXTAL1,XTAL2) 


-.5 




.8 


V 




V,H 


Input High Voltage 


2.0 




Vcc 


V 






(All Except XTAL1,XTAL2,RESET) 




V,H1 


Input High Voltage (RESET.XTALI) 


3.0 




Vcc 


V 




Vol 


Output Low Voltage 

(BUS, RD.WR, PSEN, ALE) 






.45 


V 


'oL = 2-0"^A 


VOLI 


Output Low Voltage 

(All Other Outputs Except PROG) 






.45 


V 


Iql = 1.6mA 


V0L2 


Output Low Voltage (PROG) 






.45 


V 


lOL = 1.0mA 


VoH 


Output High Voltage 

(BUS, RD, WR, PSEN, ALE) 


2.4 






V 


loH = lOOAiA 


VOHI 


Output High Voltage 
(All Other Outputs) 


2.4 






V 


loH =50aiA 


'IL 


input Leakage Current 
(T1,EA, INT) 






±10 


/JA 


Vss<V|N<Vcc 


'oL 


Output Leakage Current (BUS, TO) 
(High Impedance State) 






-10 


/ja 


VcC>V|N>Vss +.45 


'dd 


Vqd Supply Current 




10 


20 


mA 




'dd+ Ice 


Total Supply Current 




65 


135 


mA 





A.C. CHARACTERISTICS T^ = o°c to 7C 


°c, Vcc 


= Vdd = +5V ±10%*, Vss 


= OV 




Symbol 


Parameter 


8048/8748 
8035/8035 L 


8748-8 
8035-8 


Unit 


Conditions (Note 1) 




Min. 


Max. 


Min. 


Max. 




tUL 


ALE Pulse Width 


400 




600 




ns 




tAL 


Address Setup to ALE 


150 




150 




ns 




tLA 


Address Hold from ALE 


80 




80 




ns 




tec 


Control Pulse Width (PSEN, RD,WR) 


900 




1500 




ris 




tow 


Data Setup before WR 


500 




640 




ns 




twD 


Data Hold After WR 


120 




120 




hs 


Cl = 20pF 


tcY . 


Cycle Time 


2.5 


15.0 


4.17 


15.0 


MS 


6 MHz XTAL 
(3.6MHz XTAL for -8) 


tDR 


Data Hold 





200 





200 


ns 




tRD 


PSEN, RDto Data In 




500 




750 


ns 




tAW 


Address Setup to WR 


230 




260 




ns 




tAD 


Address Setup to Data In 




950 




1450 


ns 




. tAFC 


Address Float to RD, PSEN 












ns 





•Standard 8748 and 8035 ±5%, ±10% available. Notel: Control Outputs: Cl = 80 pF 

'bus Outputs: CL=150pF, tcY = 25ms 

Data sheets on pages 6-D2 through 6-D14 are reprinted by pernnission of Intel Corporation, Copyright 1978. 



6-D2 



8048/8748/8035 

A.C. CHARACTERISTICS 

Ta = 0°C to 70° C, Vcc = 5V±10% 



Symbol 


. Parameter 


Min. 


Max. 


Unit 


Test Conditions 


tcp 


Port Control Setup Before Falling 


110 




ns 






Edge of PROG 




tpc 


Port Control Hold After Falling 


140 




ns 




.. 


Edge of PROG 




tPR 


PROG to Time P2 Input Must Be Valid 


810 




ns 




top 


Output Data Setup Time 


220 




ns 




tpD 


Output Data Hold Time 


65 




ns 




tPF 


Input Data Hold Time 


110 




ns 




tpp 


PROG Pulse Width 


1510 




ns 




tPL 


Port 2 I/O Data Setup 


400 




ns 




tLP 


Port 2 I/O Data Hold 


150 




ns 





o 

< 
a 

< 

@ 



WAVEFORMS 



PORT 2 TIMING 



.r~^ 



EXPANDER 
PORT 



— A. 



EXPANDER 
PORT 



DC 



y — V 



y. 



>: 



PORT 20-3 DATA 



>: 



PORT 20-3 DATA 



PORT CONTROL 



PORT CONTROL 



>: 



OUTPUT DATA 



>: 



:c 



:c 



■v. 



/ 



6-D3 



8048/8748/8035 



WAVEFORMS 



Instruction Fetch From External Program Memory 



J 



I 



—^ 'afc ■* -Vx- 



BUS FLOATINgV f V^ FLOATING V V^ FLOATING Y 



INSTRUCTION 



Read From External Data Memory 



J 



j- tec -j 






BUS FLOATING 



FLOATING 



NAdDRES^/^ VdaTaN^ FLOATING 



I 



Write to External Data Memory 

ALE 



|— «cc- 



* — ^r H — '"'' 



L 



BUS FLOATIN(^ADDRESsYfLOATINgY data Y FLOATING 



WARNING: 

An attempt to program a missocketed 8748 will result in severe 
damage to the part. An indication of a properly socketed part is the 
appearance of the ALE clock output. The lack of this clock may 
be used to disable the programmer. 



6-D4 



8048/8748/8035 



o 

GQ 
CO 
O 

< 
Q 

< 

@ 



Programming Options 

The 8748 EPROM can be programmed by either of two 
Intel products: 

1. PROMPT-48 Microcomputer Design Aid, or 

2. Universal PROM Programmer (UPP-101 or UPP-102) 
peripheral of the Intellec® Development System with a 
UPP-848 Personality Card. 



8748 Erasure Characteristics 

The erasure characteristics of the 8748 are such that 
erasure begins to occur when exposed to light with wave- 
lengths shorter than approximately 4000 Angstroms (A). 
It should be noted that sunlight and certain types of floure- 
scent lamps have wavelengths in the 3000-4000A range. 



Data show that constant exposure to room level floure- 
scent lighting could erase the typical 8748 in approx- 
mately 3 years while it would take approximately 1 week 
to cause erasure when exposed to direct sunlight. If the 
8748 is to be exposed to these types of lighting conditions 
for extended periods of time, opaque labels are available 
from Intel which should be placed over the 8748 window 
to prevent unintentional erasure. 

The recommended erasure procedure for the 8748 is expo- 
sure to shortwave ultraviolet light which has a wavelength 
of 2537 Angstroms (A). The integrated dose (i.e., UV 
intensity X exposure time) for erasure should be a mini- 
mum of IBW-sec/cm^ . The erasure time with this dosage 
is approximately 15 to 20 minutes using an ultraviolet lamp 
with a 12000;uW/cm2 power rating. The 8748 should be 
placed within one inch from the lamp tubes during erasure. 
Some lamps have a filter on their tubes and this filter 
should be removed before erasure. 



WAVEFORMS 

Combination ProgramA/erify Mode (EPROM's Only) 

PROGRAM 



\ 



\ / 



y 



/ ADDRESS \/ 
' ~" ~\ (0-7) VALID A 



DATA TO BE 
PROGRAMMED VALID 



LAST 
ADDRESS 



X 



ADDRESS (8-9) VALID 



7 



^ 



\ 



-tvoDH 

I twT- 



\ 



^ _y 



H 



\_ _ / V DATA \ / NEXT ADDR \j^ 

r~ 'K A VALID / - - \ VALID / ^ 



X 



NEXT 
ADDRESS 



Verify Mode (ROM/EPROM) 



/ 



\ 



-V 



y V 



0B0-DB7 



-< 



ADDRESS 
10-7) VALID 



XDATA OUT \ /^ 

VAUD- / -— \ 



NEXT 
ADDRESS 



X NEXT DATA \^ 
OUT VALID r~' 



X 



ADDRESS (8-9) VALID 



X 



NEXT ADDRESS VALID 



1. PROG MUST FLOAT IF EA IS LOW (i.e., i* 25V), OR IF TO > 5V FOR THE 8741. 
FOR THE 8041 PROG MUST ALWAYS FLOAT. 

2. Veah FOR 8041- 11.4V MIN., 12.6V MAX. 



3. THE FOLLOWING CONDITIONS MUST BE MET: 

R=TTL'r 
AO - TTL 'C 
THIS CAN BE DON'E USING 10K RESISTORS TO Vcc, Vss RESPECTIVELY. 

4. Xi AND X2 DRIVEN BY 3 MHz CLOCK WILL GIVE 5 wsec tcv. THIS IS GOOD 
FOR -8 PARTS AS WELL AS NON -8 PARTS. 



6-D5 



8048/8748/8035 



AC TIMING SPECIFICATION FOR PROGRAMMING 

Ta = 25''C ± 5°C, Vcc = 5V ± 5%. Vdd = 25V ± IV 



Symbol 


Parameter 


MIn. 


Max. 


Unit 


Test Conditions 


tAW 


Address Setup Time to RESET t 


4tcy 








tWA 


Address Hold Time After RESET t 


4tcy 








tow 


Data. in Setup Time to PROG 1 


4tcy 








two 


Data in Hold Time After PROG 1 


4tcy 








tPH 


RESET Hold Time to Verify 


4tcy 








tVDDW 


Vdd 


4tcy 








tvDDH 


Vdd Hold Time After PROG 1 











tPW 


Program Pulse Width 


50 


60 


MS 




tTW 


Test Setup Time for Program Mode 


4tcy 








tWT 


Test Hold Time After Program Mode 


4tcy 








too 


Test tj to Data Out Delay 




4icy 






tww 


RESET Pulse Width to Latch Address 


4tcy 








tr. tf 


Vdd and PROG Rise and Fall Times 


0.5 


2.0 


MS 




tCY 


CPU Operation Cycle Time 


5.0 




MS 




tRE 


RESET Setup Time Before EA t 


4tcy 









Note: If Test is high too can be triggered by RESET t. 



DC SPECIFICATION FOR PROGRAMMING 

Ta = 25° C ± S^C, Vcc = 5V ± 5%, Vdd = 25V ± IV 



Symbol 


Parameter 


Min. 


Max. 


Unit 


Test Conditions 


Vdoh 


Vdd Program Voltage High Level 


24.0 


26.0 


V 




Vddl 


Vdd Voltage Low Level 


4.75 


5.25 


V 




VPH 


PROG Program Voltage High Level 


21.5 


24.5 


V 




VPL 


PROG Voltage Low Level 




0.2- 


V 




Veah 


EA Program or Verify Voltage High Level 


21.5 


24.5 


V 




Veal 


EA Voltage Low Level 




5.25 


V 




Idd 


Vdd High Voltage Supply Current 




30.0 


mA 




IPROG 


PROG High Voltage Supply Current 




16.0 


mA 




lEA 


EA High Voltage Supply Current 




1.0 


mA 





6-D6 



8049/8039 

ABSOLUTE MAXIMUM RATINGS* 

Ambient Temperature Under Bias CCtoTO'C 

Storage Temperature -esoCto+ISCC 

Voltage on Any Pin With 

Respect to Ground -O.SV to +77 

Power Dissipation 1.5 Watt 

D.C. AND OPERATING CHARACTERISTICS 



o 

CD 
(0 
O 

< 
o 

< 



'COMMENT: Stresses above those listed undot "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional 
operation of the device at these or any other conditions 
above those indicated in the operational sections of this 
specification is not implied. Exposure to absolute 
maximum rating conditions for extended periods may 
affect device reliability. 

Ta = 0°C to 70°a Vcc = Vdd = +5V ±10%, Vss = ov 



Symbol 


Parameter 


Limits 


Unit 


Test Conditions 


Min. 


Typ. 


Max. 


V|L 


Input Low Voltage 

(All Except XTA LI, XTAL2) 


-0.5 




0.8 


V 




V,H 


Input High Voltage 


2.0 




Vcc 


V 






(All Except XTA LI, XTAL2, RESET) 




V|H1 


Input High Voltage (RESET, XTAL1) 


3.0 




Vcc 


V 




Vol 


Output Low Voltage 

(BUS, RD.WR, PSEN,ALE) 






0.45 


V 


Iql = 2.0mA 


VOLI 


Output Low Voltage 

(All Other Outputs Except PROG) 






0.45 


V 


Iql = 1-6mA 


VOH 


Output High Voltage 
(BUS, RD.WR, PSEN, ALE) 


2.4 






V 


lOH = lOO^iA 


Vqhi 


Output High Voltage 
(Another Outputs) 


2.4 






V 


loH = 50a(A 


l|L 


Input Leakage Current 
(T1,EA, INT) 






±10 


AiA 


Vss<V,N<Vcc. 


lOL 


Output Leakage Current (Bus, TO) 
(High Impedance State) 






-10 


A<A 


Vcc>V|N>Vss+0.45 


'dd 


Power Down Supply Current 




20 


50 


mA 


Ta = 25° C 


•dd+'cc 


Total Supply Current 




75 


140 


mA 


Ta = 25°C 



A.C. CHARACTERISTICS Ta = o°c to 7o"c, Vcc = Vqd = +5V ±io%, Vss = ov 





Parameter 


8049/8039 


Unit 


Conditions 


Symbol 


Min. 


Max. 


tLL 


ALE Pulse Width 


400 




ns 




tAL 


Address Setup to ALE 


150 




ns 




tLA 


Address Hold from ALE 


80 




ns 




'cc 


Control Pulse Width (PSEN, RD.WR) 


900 




ns 




tow 


Data Set- Up Before WR 


500 




ns 




tWD 


Data Hold After WR 


120 




ns 


Cl = 20 pF 


tcY 


Cycle Time 


2.5 


15.0 


MS 


6MHzXTAL 


tDR 


Data Hold 





200 


ns 




tRD 


PSEN, RD to Data In 




500 


ns 




Uw 


Address Setup to WR 


230 




ns 




tAD 


Address Setup to Data In 




950 


ns 




^AFC 


Address Float to RD, PSEN 







ns 





A.C. TEST CONDITIONS Control Outputs: Cl = 80 pF 



BUS Outputs: Cl=150pF 



tcY = 2.5/is 



6-D7 



8049/8039 



WAVEFORMS 

Instruction Fetch From External Program Memory 



ALE 



PSEN 



. t^Y- 



BUS FLOATING 



ADDRESS'' 






I 



•<cc- 



Y FLOATING V \^ FLOATING ^ 



INSTRUCTION 



Read From External Data Memory 

ALE I 



L 



(FLOATING 



— to^ 



BUS FLOATING VaDDRESS^ ^ X'^'^^^'^X 



1*^0* 



Write To External Data Memory 

J 



ALE 




BUS FLOATIN(^AODRESSyr-LnAritv(^V data Y 



6-D8 



o 

EQ 
(A 
O 

< 

o 
< 

@ 



8041/8741 

ABSOLUTE MAXIMUM RATINGS* 

Ambient Temperature Under Bias 0''Cto70°C 

Storage Temperature -65°Cto+150°C 

Voltage on Any Pin With 

Respect to Ground O.SVto+yV 

Power Dissipation 1.5 Watt 

D.C. AND OPERATING CHARACTERISTICS 

Ta = O'C to 70*C, Vcc = Vdd = +5V ±5%, Vgs = OV 



'COMMENT: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifi- 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 





Parameter 


Limits 


Unit 




Symbol 


MIn. 


Typ. 


Max. 


Test Conditions 


ViL 


Input Low Voltage(AII 
Except Xi, X2) 


-0.5 




0.8 


V 




VlH 


Input High Voltage (All 


2.0 




Vcc 


V 






Except Xi, X2 RESET) 




\/|H2 


Input High Voltage (Xi, 
RESET) 


3.0 




Vcc 


V 




Vol 


Output Low Voltage (D0-D7, 
Sync) 






0.45 


V 


lOL = 2.0 mA 


V0L2 


Output Low Voltage (All 
Other Outputs Except Prog) 






0.45 


V 


lOL = 1.6 mA 


VOH 


Output High Voltage (D0-D7) 


2.4 






V 


loH = -400/iA 


VOHI 


Output High Voltage (All 
Other Outputs) 


2.4 






V 


loH = -50/iA 


IlL 


Input Leakage Current 

(To, Ti.RD, WR, CS. Ao, EA) 






±10 


^A 


Vss < ViN < Vcc 


lOL 


Output Leakage Current 
(D0-D7, High Z State) 






±10 


mA 


Vss + 0.45 < ViN < Vcc 


Idd 


Vdd Supply Current 




10 


25 


mA 




'cc + Idd 


Total Supply Current 




65 


135 


mA 




V0L3 


Output Low Voltage (Prog) 






0.45 


V 


lOL = 1.0 mA 


Ilii 


Low Input Source Current 
P10-P17 P20-P27 






0.4 


mA 


ViL = 0.8V 


IU2 


Low Input Source Current 
RESET, SS 






0.2 


mA 


ViL = 0.8V 



A.C. CHARACTERISTICS 

Ta = O'C to 70'C, Vcc = Vdd = +5V ±5%, Vss = OV 
DBB Read: 



Symbol 


Parameter 


8741 


8041 


Units 


Test Conditions 


Min. 


Max. 


MIn. 


Max. 


tAR 


CS, Ao Setup to RD i 


60 









ns 




tRA 


CS, Ao Hold After RD t 


30 









ns 




tRR 


RD Pulse Width 


300 


2xtGY 


250 




ns 


tcY = 2.5 us 


Ud 


CS, Ao to Data Out Delay 




370 




150 


ns 




Ird 


RD i to Data Out Delay 




200 




150 


ns 




tDF 


RD t to Data Float Delay 


10 




10 




ns 






140 




100 


ns 




tRV 


Recovery Time Between Reads 
And/Or Write 


1 




1 




i^s 




tCY 


Cycle Time 


2.5 




2.5 




MS 


6 MHz Crystal 



6-D9 



8041/8741 



DBB Write: 


Symbol 


Parameter 


8741 


8041 


Units 


Test Conditions 


Min. 


Max. 


Min. 


Max. 


tAW 


CS, Ao Setup to WR 1 


60 









ns 




twA 


CS, Ao Hold After WR t 


30 









ns 




tww 


WR Pulse Width 


300 


2xtcY 


250 




ns 


tcY = 2.5 jiS 


tow 


Data Setup to WR t 


250 




150 




ns 




two 


Data Hold After WRt 


30 









ns 





A.C. TEST CONDITIONS 

D7-D0 Outputs RL = 2.2ktoVss 
4.3k to Vcc 
Cl = 100 pF 



WAVEFORMS 

Read Operation — Data Bus Buffer Register 



C5 OR Ao Y 


" 


K 




\ 


(SYSTEMS 
ADDRESS BUS) 










.. 




























/ 






m 




lA 




(READ CONTROL) 




^-•ro^ 






•* tDF — ► 


>— 








-< 






DATA BUS 




AL 






(OUTPUTI 









Write Operation — Data Bus Buffer Register 



'-^C 



X 



-I - 

1 



./' 



IWRITE CONTROL) 



V-< — ■ DATA VALID- "Y 



6-D10 



8041/8741 



8748 Erasure Characteristics 

The erasure characteristics of the 8748 are such that 
erasure begins to occur when exposed to light with 
wavelengths shorter than approximately 4000 Ang- 
stroms (A). It should be noted that sunlight and certain 
types of fluorescent lamps have wavelengths in the 
3000-4000A range. Data show that constant exposure to 
room level fluorescent lighting could erase the typical 
8748 in approximately 3 years while it would take ap- 
proximately one week to cause erasure when exposed 
to direct sunlight. If the 8748 is to be exposed to these 
types of lighting conditions for extended periods of 



time, opaque labels are available from Intel which 
should be placed over the 8748 window to prevent 
unintentional erasure. 

The recommended erasure procedure for the 8748 is ex- 
posure to shortwave ultraviolet light which has a wave- 
length of 2537 A. The integrated dose (i.e., UV Intensity 
X exposure time) for erasure should be a minimum of 15 
W-sec/cm2. The erasure time with this dosage is approx- 
imately 15 to 20 minutes using an ultraviolet lamp with a 
12,000 fjW/cm^ power rating. The 8748 should be placed 
within one inch of the lamp tubes during erasure. Some 
lamps have a filter on their tubes which should be 
removed before erasure. 



A.C. TIMING SPECIFICATION FOR PROGRAMMING 

Ta = 25''C ±5°C, Vcc = 5V ±5%, Vqd = 25V ± IV 



O 

< 

a 

< 



Symbol 


Parameter 


Min. 


Max. 


Unit 


Test Conditions 


tAW 


Address Setup Time to RESET t 


4fcy 








tWA 


Address Hold Time After RESET I 


4tcy 








tow 


Data in Setup Time to PROG t 


4tcy 








two 


Data in Hold Time After PROG 1 


4tcy 








tPH 


RESET Hold Time to Verify 


4tcy 








tVDDW 


VoD 


4tcy 








tVDDH 


Vdd Hold Time After PROG i 











tPW 


Program Pulse Width 


50 


60 


MS 




tTW 


Test Setup Time for Program Mode 


4tcy 








tWT 


Test Hold Time After Program Mode 


4tcy 








too 


Test to Data Out Delay 




4tcy 






tww 


RESET Pulse Width to Latch Address 


4tcy 








tr, tf 


Vdd and PROG Rise and Fail Times 


0.5 


2.0 


MS 




tCY 


CPU Operation Cycle Time 


5.0 




MS 




tRE 


RESET Setup Time Before EA t 


4tcy 









Note: If TEST is high, fpQ can be triggered by RESET 1. 

D.C. SPECIFICATION FOR PROGRAMMING 

Ta = 25»C ±5°C, Vcc = 5V ±5%, Vdd = 25V ±1V 



Symbol 


Parameter 


MIn. 


Max. 


Unit 


Test Conditions 


Vdoh 


Vdd Program Voltage High Level 


24.0 


26.0 


V 




Vddl 


Vdd Voltage Low Level 


4.75, 


5.25 


V 




VPH 


PROG Program Voltage High Level 


21.5 


24.5 


V 




VPL 


PROG Voltage Low Level 




0.2 


V 




Veah 


EA Program or Verify Voltage High Level 


21.5 


24.5 


V 




Veal 


EA Voltage Low Level 




5.25 


V 




Idd 


Vdd High Voltage Supply Current 




30.0 


mA 




IPROG 


PROG High Voltage Supply Current 




16.0 


mA 




lEA 


EA High Voltage Supply Current 




1.0 


mA 





6-D11 



8041/8741 

WAVEFORMS 

Combination Program/Verify Mode (EPROMs Only) 



r V 



/ 



/ ADDRESS \/" 
'.">. (0-71 VALID A 



ADDRESS \/ DATA TO BE 

(0-71 VALID A PROGRAMMED VALID 



PjO-Pl 



LAST 
ADDRESS 



X 



ADDRESS (8-9) VALID 



7 



A. 



\ 



-•VODH 

I twT- 



•> VERIFY- 



^ y 

- — »oo — "4 
"\_ / V DATA \_ / NEXTADDR \/ 



:^^_.. 



X 



NEXT 
ADDRESS 



A. 



Verify Mode (ROM/EPROM) 



VERIFY MODE (ROM/EPROM) 








TO.RESET \ 


/ V 


/ \ 


DB0-OB7 \- -/ 


ADDRESS \/ DATA OUT \_ 
(0-7) VALID ^ VALID /"" ~ 


-<_ 


NEXT Y NEXT DATA \^ 
ADDRESS A OUT VALID /" "" — — — 






X 


ADDRESS (8-9) VALID 


JC 


NEXT ADDRESS VALID 



6-D12 



8243 



ABSOLUTE MAXIMUM RATINGS' 



Ambient Temperature Under Bias 0°C to yO^C 

Storage Temperature -65°C to +150°C 

Voltage on Any Pin 

With Respect to Ground -0.5V to +7V 

Power Dissipation 1 Watt 



'COMMENT: Stresses above those listed under "Absolute 
Maximum Ratings" may cause permanent damage to the 
device. This is a stress rating only and functional opera- 
tion of the device at these or any other conditions above 
those indicated in the operational sections of this specifh 
cation is not implied. Exposure to absolute maximum 
rating conditions for extended periods may affect device 
reliability. 



o 

CO 

w 
o 

< 
Q 

< 

© 



D.C. AND OPERATING CHARACTERISTICS 

Ta = 0°C to yCC, Vcc = 5V ±10% 



Symbol 


Parameter 


MIn. 


Typ. 


Max. 


Units 


Test Conditions 


V|L 


Input Low Voltage 


-0.5 




0.8 


V 




V|H 


Input High Voltage 


2.0 




Vcc+0.5 


V 




VOLI 


Output Low Voltage Ports 4-7 






0.45 


V 


Iqu = 5 mA* 


V0L2 


Output Low Voltage Port 7 






1 


V 


Iql = 20 mA 


Vqhi 


Output High Voltage Ports 4-7 


2.4 






V 


Ioh=240a/A 


I.LI 


Input Leakage Ports 4-7 


-10 




20 


HA 


Vin=VcctoOV 


'lL2 


Input Leakage Port 2, CS, PROG 


-10 




10 


AiA 


Vin=VcctoOV 


VoL3 


Output Low Voltage Port 2 






.45 


V 


loL= 0.6 mA 


•cc 


Vcc Supply Current 




10 


20 


mA 




VoH2 


Output Voltage Port 2 


2.4 








IOH=100/iA 


lOL 


Sum of all Iql from 16 Outputs 






100 


mA 


5 mA Each Pin 



*See following graph for additional sink current capability. 

A.C. CHARACTERISTICS 

Ta = 0°C to 70°C, Vcc = 5V ± 1 0% 



Symbol 


Parameter 


Min. 


Max. 


Units 


Test Conditions 


tA 


Code Valid Before PROG 


100 




ns 


80 pF Load 


tB 


Code Valid After PROG 


60 




ns 


20 pF Load 


tc 


Data Valid Before PROG 


200 




ns 


80 pF Load 


to 


Data Valid After PROG 


20 




ns 


20 pF Load 


tH 


Floating After PROG 





150 


ns 


20 pF Load 


tK 


PROG Negative Pulse Width 


900 




ns 




tcs 


CS Valid Before/After PROG 


50 




ns 




tpo 


Ports 4-7 Valid After PROG 




700 


ns 


100 pF Load 


tLPI 


Ports 4-7 Valid Before/After PROG 


100 




ns 




tACC 


Port 2 Valid After PROG 




750 


ns 


80 pF Load 



6-D13 



8243 
WAVEFORMS 



\ 



A 



"V V V V 

X INSTRUCTION V FLOAT V DATA X 

J\ A 1 A A 



\y' OUTPUT \X 

-J\ ""° A 



PREVIOUS OUTPUT VALID 



• * *P0 *- 



X 



OUTPUT 
VALID 



-*-t 



INPUT VALID 



X 



■♦-tcs -*- 



y 



6-D14 



Chapter 7 
ZILOG Z80 



(^ Zilog Z80 microcomputer devices have been designed as 8080A enhancements. In fact, the same individuals 

[^ responsible for designing the 8080A CPU at Intel designed the Z80 devices at Zilog. The 8085, described in 

^ Chapter 5, is Intel's 8080A enhancement. 

(A The Z80 instruction set includes all 8080A instructions as a subset. In deference to rational necessity, 

< however, neither the Z80 CPU, nor any of its support devices attempt to maintain pin-for-pin compatibility with 
o3 8080A counterparts. Compatibility is limited to instruction sets and general functional capabilities. A program 
^ that has been written to drive an 8080A microcomputer system will ajso drive the Z80 system — within cer- 
g tain limits; for example, a ROM device that has been created to implement object programs for an 8080A 
m microcomputer system can be physically removed and used in a Z80 system. 

_ But Z80-8080A compatibility does extend ||omewhat further, since most support devices that have been 

< designed for the 8080A CPU will also work with a Z80 CPU; therefore in many cases you vyill be able to upgrade 
^ an 8080A microcomputer system to a Z80, confining hardware rpodifications to the CPU and its immediate in- 
gjj terface only. 

It is interesting to note that the Z80 pins and signal interface is far closer than the 8085 to the three-chip 8080A 
configuration illustrated in 8p80A chapter: Also, whereas the Z8Q instruction set is greatly expanded as compared to 
the 8080A, the 8085 instruction set contains just two new instructions. However, both the Z80 and the 8085 have 
resolved the two most distressing problems associated with the 8080A^^^the three-chip 8080A CPU has in both cases 
been reduced to one chip, and the three 8080A power supplies have in both cases been reduced to a single +5V power 
supply. 

ZILOG, INC., manufacturers of the Z80, are located at: 

10460 Bubb Road 
Cupertino, California 95014 

The official second source for Zilog products is: 

MDSTEK, INC. 
1215 West Crosby Road 
Carrollton, Texas 75006 

N-Channel MOS technology is used for all Z80 devices. 



Z80 LSI 
TECHNOLOGY 



THE Z80 CPU 

Functions implemented on the Z80 CPU are illustrated in Figure 7-1. They represent "typical" CPU logic, 
equivalent to the three devices: 8080A CPU, 8224 Clock and 8228 System Controller. 

A SUMMARY OF Z80/8080A DIFFERENCES 

We are going to summarize Z80/8080A differences before describing differences in detail. If you know the 
8080A well, read on; if you do not, come back to this summary after reading the rest of the Z80 CPU descrip- 
tion. We will also contrast the Z80 and the 8085, where relevant. 

..■'.. ■ ' 

For the programmer, the Z80 provides more registers and addressing modes than the 8080A, plus a much larger 
instruction set. 

Significant hardware features are a single power supply (+5V), a single system clock signal, an additional inter- 
rupt and logic to refresh dynamic memories. 



7-1 



Clock Logic 



Logic to Handle 
Interrupt Requests 

from 
External Devices 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Interrupt Priority 
Arbitration 



Bus Interface 
Logic 



Accumulator 
Registeris} 



Data Counter<s) 



Stack Pointer 



Program Counter 



Direct Memory 

Access Control 

Logic 



System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 

Interface Logic 



I/O Ports 
Interface Logic 



RAM Addressing 

and 
Interface Logic 



Read Only 
Memory . 



I/O Ports 



Read/Write 
Memory 



Figure 7-1 . Logic Functions of the Z80 CPU 

The 8085 also has a single power supply and a single system clock signal. The 8085 has three additional interrupts, but 
laci<s logic to refresh dynamic memories. 

Is the Z80 CPU indeed the logical next 8080A evolution? 

Hardware aspects of the 8080A represent its weakest features, as compared to principal current competitors. 

Specifically, the fact that the 8080A is really a three-chip CPU is its biggest singl^ problem; three chips are always 
going to cost more than one. Next, the fact that the 8080A requires three power supplies (+5V, -5V and + 1 2V) is a very 
negative feature for many users and the desirability of going to a single power supply is self-evident; the Z80 requires a 
single +5V power supply. This is also true of the 8085. 

The problems associated with condensing logic from three chips onto one chip are not so straightforward. Figure 7-2 il- 
lustrates the standard three-chip 8080A CPU. Let us assume that the three devices are to be condensed into a single 
chip. Asterisks (*) have been placed by the signals which must be maintained if the single chip is to be hardware com- 
patible with the three chips it replaces. Forty-three signals are asterisked, therefore the standard 40-pin DIP cannot be 
used. The problem is compounded by the fact that not all 8080A systems use an 8228 System Controller. Some 8080A 
systems use an 821 2 bidirectional I/O port to create control signals. A few of the earliest 8080 systems use neither the 
8228 System Controller, nor an 821 2 I/O port; rather external logic decodes the Data Bus when SYNC is true in order to 
generate control signals; for example, that is how the TMS5501 works. We must therefore conclude that any attempt 



7-2 



cc 
o 

CD 
V> 

o 

< 

Q 
< 

@ 



to reduce three chips to one will create a product that is not pin compatible with the 8080A; and, indeed, the Z80 is not 
pin compatible. What Zilog has done is include as many hardware enhancements as possible within the confines of a 
40-pin DIP that must be philosophically similar to the BOBOA, without attempting any form of pin compatibility. Figure 
7-2 identifies the correlation between ZBO signals and BOBOA signals. Notice that there is a significant similarity. 

Figure 5-3 is equivalent to Figure 7-2, comparing B0B5 and BOBOA signals. ZBO signals are far closer to the BOBOA 
three-chip set than the B0B5. 

Here is a summary of the hardware differences: 

1) The ZBO has reduced three power supplies to a single -f 5V power supply. 

2) Clock logic is entirely within the ZBO. 

3) The complex, two clock signals of the BOBOA have been replaced by a single clock signal. 

4) Automatic dynamic memory refresh logic has been included within the CPU. 

5) Read and write control signal philosophy has changed. The BOBOA uses separate memory read, memory write, I/O 
read and I/O write signals. The ZBO uses a general read and a general write, coupled with a memory select and an 
I/O select. This means that if a ZBO CPU is to replace an BOBOA CPU then additional logic will be required beyond 
the ZBO CPU., You will either have to combine the four ZBO control signals to generate BOBOA equivalents, or you 
will have to change the select and strobe logic for every I/O device. We will discuss this in more detail later. 

6) Address and Data Bus float timing associated with DMA operations have changed. The BOBOA floats these busses 
at the beginning of the third or fourth time period within the machine cycle during which a bus request occurs; 
this initiates a Hold state. The ZBO has a more straightforward scheme; a Bus Request input signal causes the Data 
and Address Busses to float at the beginning of the machine cycle; floating busses are acknowledged with a Bus 
Acknowledge output signal. 

7) The ZBO has an additional interrupt request. In addition to. the RESET and normal BOBOA interrupt request, the ZBO 
has a nonmaskable interrupt which is typically used to execute a short program that prepares for power failure, 
once a power failure has been detected. 

Now consider internal organization of the Z80 in terms of instruction set compatibility and enhancement. 

As illustrated by Table 7-3 the BOBOA instruction set is, indeed, a subset of the ZBO instruction set. Unfortunately, the 
ZBO uses completely new source program instruction mnemonics, therefore BOBOA instructions cannot immediately be 
identified. Technical Design Labs, Inc., has an BOBO-like ZBO assembly language. 



BUSRQ SYSTEM DMA REQ 



SYSTEM IMT. REQ. 




■*• AO *\ 



I ADDRESS BUS* 





5^ 




->■ 


S228 

BIDIRECTIONAL . 
BUS DRIVER • 


Ti ' 


dl 




L 


ti 






31 




t^ 




j: 




tl ' 


._— — __: 


ir 


lORQMI 


^ 




24 


MREQ BD 






2f 


MREQ WR 


' 


CONTROL , 


2S 


lOnORO 


^ 




27 




.fc. 




Ml Z80 •quiva(«nt, or r>tw lignalt. 

* Signal! rtproducad by th« Z80. 

* Signal* which muit bt duplicatad by i 
hardwara rtptacamant product. 



R?5n \ Thaia ara Z80 signal* 
HALT > with no e080A 
NMI } countarpart 



Figure 7-2. The Standard 8080A Three-Chip System and Z80 Signal Equivalents 



7-3 



There are very few unused object codes in the 8080A instruction set. The Z80 has therefore taken what few unused ob- 
ject codes there are, and used thenn to specify that an additional byte of object code follows: 

11011101-^ — Spare 8080A object code 

-^ — Specifies new Z80 object code follows 

This results in most new Z80 instructions having 16-bit object codes; but simultaneously it means that a very large 
number of new instructions can be added. 

Any enhancement of the 8080A can include major changes within the CPU; providing the 8080A registers and status 
flags remain as a subset of the new design, instruction compatibility remains. These are the principal enhancements 
made by the Z80: 

1) The standard general purpose registers and status flags have been duplicated. This makes it very easy to handle 
single-level interrupts, since general purpose register and Accumulator contents no longer need to be saved on the 
Stack; instead, the program may simply switch to the alternate register set. 

2) Two Index registers have been added. This means that additional Z80 instructions can use indexed memory ad- 
dressing. 

2) An Interrupt Vector register allows external logic the option of responding to an interrupt acknowledge by issuing 
the equivalent of a Call instruction — which vectors program execution to a memory address which is dedicated 
to the acknowledged external logic. 

4) A single Block Move instruction allows the contents of any number of contiguous memory bytes to be moved from 
one area of memory to another, or between an area of memory and a single I/O port. You can also scan a block of 
memory for a defined value by executing a Block Compare instruction. 

5) Instructions have been added to test or alter the condition of individual register and memory bits. 

In contrast to the extensive enhancements of the Z80, the 8085 registers and status architecture are identical to the 
8080A. There are only two additional instructions in the 8085 instruction set; however, the 8085, like the Z80, allows 
Call instructions to be used when acknowledging an interrupt — a particularly useful enhancement. 

While on the surface the Z80 instruction set appears to be very powerful, note that instruction sets are very 
subjective; right and wrong, good and bad are not easily defined. Let us look at some nonobvious features of the 
Z80 instruction set. 

First of all, the execution speed advantage that results from the new Z80 instructions is reduced by the fact that many 
of these instructions require two bytes of object code. Some examples of Z80 instructions and equivalent 8080A in- 
struction sequences with equivalent cycle times are given in Table 7-1. 

Table 7-1. Comparisons of Z80 and 8080A 
Instruction Execution Cycles 



Z80 


8080A 1 


Instructions 


Cycles 


Instructions 


Cycles 


LD R.dX + d) 


19 


LXI H,d 


10 






DAD IX 


10 






MOV R;M 


7 
27 


LD RP,ADDR 


20 


LHLD ADDR 


16 






MOV C.L 


5 






MOV B,H 


5 
26 


SET B.(HL) 


15 


MOV A.M 


.. 7 






OR! MASK 


7 






MOV M.A 


7 
21 



Also, a novice programmer may find the Z80 instruction set bewilderingly complex. At a time when the majority of po- 
tential microcomputer users are terrified by simple assembly language instruction sets, it is possible that users will 
react negatively to an instruction set whose complexity (if not power) rivals that of many large minicomputers. 

Many of the new Z80 instructions use direct, indexed memory addressing to perform operations which are otherwise 
identical to existing 8080A instructions. Now the Z80 has two new 1 6-bit Index registers whose contents are added to 



7-4 



an 8-bit displacement provided by the instruction code; this is the scheme adopted by the Motorola MC6800. This 
scheme is inherently weaker than having a 1 6-bit. instruction-provided displacement, as implemented by the Signetics 
2650. When the Index register is larger than the displacement, the Index register, in effect, becomes a base register. 
When the Index register has the same size, or is smaller than the displacement, it is truly an Index register as described 
in "Volume 1 — Basic Concepts". The Signetics 2650 implementation is more powerful. 

Z80 PROGRAMMABLE REGISTERS 

We will now start looking at the Z80 CPU in detail, beginning with its programmable registers. 

The Z80 has two sets of 8-bit programmable registers, and two Program Status Words. At any time one set of 
programmable registers and one Program Status Word will be active and accessible. 

In addition, the Z80 has a 16-bit Program Counter, a 16-bit Stack Pointer, two 16-bit Index registers, an 8-bit 
Interrupt Vector and an 8-bit Memory Refresh register. 

Figure 7-3 illustrates the Z80 registers. Within this figure, the 8080A registers' subset is shaded. 



< 

Q 

< 

@ 





r 


^ 


( These two 8-bit registers 
■i < are sometimes treated > ' 
\ as a 16-bit unit 




^ 




^i 


PSW 


Program Status Words 

Primary Accumulators 

Secondary Accumulators/Data Counter 

Secondary Accumulators/Data Counter 

Secondary Accumulators/Data Counter 

Stack Pointer 

Program Counter 

Index Register X 

Index Register Y 

Interrupt Vector 

Memory Refresh Counter 


PSW 


iV 1 




\ 


A 


A' 


) 






am mmm. 


C 


B' 


C 




mmmim 


E 


D' 


E' 


wmwmsMi 


L 


H' 


L' 


msmmMi:SPJMmM$Mm 








PC 




IX 


lY 




. 


IV 




R 




Shaded regist 


ers represent t 


ie 8080A subset.- 







Figure 7-3. Z80 Programmable Registers 

The Z80 uses its Program Status Word, its A, B, C, D. E, H, and L registers, plus the Stack Pointer and the Pro- 
gram Counter exactly as the 8080A uses these locations; therefore no additional discussion of these registers 
is needed. 

The Program Status Word, plus registers A, B, C, D, E, H and L are duplicated. Single Z80 instructions allow you to 
switch access from one register set to another, or to exchange the contents of selected registers. At any time, one or 
the other set of registers, but not both, is accessible. 

There are two 16-bit Index registers, marked IX and lY. These are more accurately looked upon as base registers, as 
will become apparent when we examine Z80 addressing modes. 

The Interrupt Vector register performs a function similar to the ICW2 byte of the 8259 PICU device (described 
in the 8080A chapter). Z80 interrupt acknowledge logic gives you the option of initiating an interrupt service routine 
with a Call instruction, where the high order address byte for the call is provided by the Interrupt Vector register. The 
8085 also provides this capability. 

The Memory Refresh Counter register represents a feature of microcomputer systems which has been over- 
looked by everyone except Fairchild and Zilog. Dynamic memory devices will not hold their contents for very long, 
irrespective of whether power is off or on. A dynamic memory must therefore be accessed at millisecond intervals. 
Dynamic memory devices compensate for this short-coming by being very cheap — and dynamic refresh circuitry is 
very simple. Using a technique akin to direct memory access, dynamic refresh circuitry will periodically access dynamic 
memories, rewriting the contents of individual memory words on each access. About the only logic needed by dynamic 
refresh is a counter via which it keeps track of its progress through the dynamic memory; that is the purpose of the Z80 
Memory Refresh Counter register. The Z80 also has a special DMA refresh control signal; therefore the Z80 provides 
much of the dynamic refresh logic needed by dynamic memory devices. 



7-5 



Z80 ADDRESSING MODES 

Z80 instructions use all of the 8080A addressing modes; the Z80 also has these two enhancements: 

1) A number of memory reference instructions use the IX and lY registers for indexed, or base relative ad- 



2) 



dressing. 

There are some two-byte program relative Jump instructions. 



A memory reference instruction that uses the IX or lY register will include a single data displace- 
ment byte. The 8-bit value provided by the instruction object code is added to the 16-bit value 
provided by the identified Index register in order to compute the effective memory address: 



Z80 

INDEXED 

ADDRESSING 



IXorlY 




^ Op Code > 

^ Displacement ) 



Effective Address = ppqq + dd 



Memory 

Reference 

instruction 



p, q and d represent any hexadecinnal digits; 
dd represents an 8-bit, signed binary value. 



This is standard microcomputer indexed addressing and is less powerful than having the memory 

reference instruction provide a 16-bit base address or displacement; for a discussion of these addressing modes see 

"Volume 1 — Basic Concepts", Chapter 6. 

The program relative, two-byte Jump instructions provided by the Z80 provide standard two-byte, program relative ad- 
dressing. A single, 8-bit displacement is provided by the Jump instruction's object code; this 8-bit displacement is ad- 
ded, as a signed binary value, to the contents of the Program Counter — after the Program Counter has been incre- 
mented to point to the sequential instruction: 

PROGRAM Memory 
MEMORY Address 







ppqq-2 
ppqq-1 

ppqq 

ppqq + 1 / 
ppqq + 2 y 








Program Counter 








XX 


^,.-•4- ppqq i 


Displacement—^^ 


dd 






W^^^ ^ 






^^ ppqq + 2 + dd 







The next instruction object code will be fetched from memory location ppqq-f2+dd. p, q, and d represent any hex- 
adecimal digits, dd represents a signed binary, 8-bit value. 

For a discussion of program relative addressing, see "Volume 1 - Basic Concepts" 

The Z80 addressing enhancements are of significant value when comparing the Z80 to the 8080A. 

The value of the Index register comes not so much from having an additional addressing option, but rather IX and lY 
allow an efficient programmer to husband his CPU register space more effectively. Look upon IX and lY as performing 
memory addressing tasks which the 8080A would have to perform using the BC and DE registers. By freeing up the BC 
and DE. registers for data manipulation, you can significantly reduce the number of memory reference instructions ex- 
ecuted by the Z80. 



7-6 



The two-byte program relative Jump instruction is useful because in most programs 80% of the Jump instructions 
branch to a memory location that is within 1 28 bytes of the Jump. That is the rationale for most microcomputers offer- 
ing two-byte as well as three-byte Jump instructions. 

Z80 STATUS 

Q The Z80 and 8080A both use the Program Status Word in order to store status flags. These are the Z80 status 

^ flags: 

g Carry (C) 

DL Zero (Z) 

o Sign (S) 

2 Parity/Overflow (P/0) 

~- Auxiliary Carry (A^) 

w Subtract (N) 

5 Statuses are recorded in the Program Status Word by the Z80, as compared to the 8080A, as follows: 



7654 3210- ^ Bit No. 

|S|z|x|^|x|85|Nfc]'^ Z80 Program Status Word 



a 7 6 5 4 3 2 1 ^ 'Bit No. 

O 



|S|z|x|^|x|P|x[c|— < 8080A Program Status Word 



O 

< The Parity/Overflow and Subtract statuses differ from the 8080A. All other statuses are the same. Note that 

§ the Z80, like the 8080A, uses borrow philosophy for the Carry status when performing subtract operations. That is 

gj to say, during a subtract operation, the Carry status takes the reciprocal value of any Carry out of the high-order bit. For 

details see the 8080A Carry status descriptions given in the 8080A chapter. 

The 8080A has a Parity status but no Overflow status. The Z80 uses a single status flag for both operations, which 
makes a lot of sense. The Z80 Overflow status is absolutely standard, therefore only has meaning when signed binary 
arithmetic is being performed — at which time the Parity status has no meaning. Within the Z80, therefore, this single 
status is used by arithmetic operations to record overflow and by other operations to record parity. For a complete dis- 
cussion of the Overflow status see "Volume 1 — Basic Concepts". 

The Subtract status is used by the DAA instruction for BCD operations, to differentiate between decimal addition or 
subtraction. The Subtract and Auxiliary Carry statuses cannot be used as conditions for program branching (condi- 
tional Jump, Call or Return instructions). 

Z80 CPU PINS AND SIGNALS 

The Z80 CPU pins and signals are illustrated in Figure 7-4. Figure 7-2 provides the direct comparison between 
Z80 CPU signals and the standard 8080A, 8228, 8224 three-chip systems. 

Let us first look at the Data and Address Busses. 

The 16 address lines AO - A15 output memory and I/O device addresses. The address lines are tristate; they may 
be floated by the Z80 CPU, giving external logic control of the Address Bus. There is no difference between Z80 and 
8080A Address Bus lines. 

The Data Bus lines DO - D7 transmit bidirectional data into or out of the Z80 CPU. Like the Address Bus lines, the 
Data Bus lines are tristate. The Z80 Data Bus lines do differ from the 8080A equivalent. The 8080A Data Bus is 
multiplexed; status output on the Data Bus by the 8080A during the T2 clock period of very machine cycle is strobed 
by the SYNC pulse. The Z80 does not multiplex the Data Bus in this way. The Z80 Data Bus lines operate at normal TTL 
levels, whereas the 8080A Data Bus lines do not. 



Control signals are described next; these may be divided into system control, CPU control 
and Bus control. First we will describe the System control signals. 

Ml identifies the instruction fetch machine cycle of an instruction's execution. Its function 
is similar, but not identical to the 8080 A SY NC pulse. The Z80 PIO device uses the low M1 
pulse as a reset signal if it occurs without lORQ or RD simultaneously low. 



Z80 SYSTEM 

CONTROL 

SIGNALS 



MREQ identifies any memory access operation in progress: it is a tristate control signaL 



lORQ identifies any I/O operation in progress. When lORQ is low, AO - A7 contain a vali d I/O port address. lORQ is 
also used as an interrupt acknowledge; an interrupt is acknowledged by M1 and lORQ being output low — a uni- 
que combination, since Ml is otherwise low only during an instruction fetch, which cannot address an I/O device. 



7-7 



RD is a tri state sig nal w hich indicates that the CPU wishes to read data from either memory or an I/O device, as 
identified MREQ or lORQ. 

WR is a tri state c ontr ol sig nal which indicates that the C PU w ishes to write data to memory or an I/O device as in- 
dicated by MREQ and lORQ. Some Z80 I/O devices have no WR input. These devices assume a Write operation when 
lORQ is low and RD is high. RD low specifies a Read operation. 

The various ways in which the three control signals, Ml, lORQ, and RD, may be interpreted are summarized in Table 
7-5, which occurs in the description of the Z80 PIO device. 



RFSH is a control signal used to refresh dynamic memories. When RFSH is output low, the current MREQ signal 
should be used to refresh dynamic memory, as addressed by the lower seven bits of the Address Bus, AO - A6. 

Next we will describe CPU control signals. 



All 
A12 
«i13 
A14 
A15 
<t> 

D4 

D3 

D5 

D6 
+ 5V 

D2 

D7 

DO 

D1 

INT 

NMI 

HALT 

MREQ 

lORQ 

PIN NAME 
AO- A15 
D0-D7 

Ml 

MREQ 

lORQ 





1 40 

2 39 

3 38 

4 37 

5 36 




















n* 


6 35 






7 34 

8 33 

9 32 

10 Z80 31 

11 CPU 30 

12 29 

13 28 

14 27 

15 26 
ifi 2B 










































17 24 

18 23 
•19 22 


















20 21 





BUSRQ 
BUSAK 
+ 5V, GND 



BUSRQ 

WATT 

BUSAK 

WR 

RD 



DESCRIPTION 

Address Bus 

Data Bus 

Identifies instruction fetch mactitne cycle 

Memory request — Indicates that CPU 

is performing memory access 

1/0 request — indicates I/O operation 

in progress 

CPU read from memory or I/O device 

CPU write to memory or I/O device 

Refresh dynamic memories 

CPU Halt executed 

Wait state request 

Interrupt request 

Nonmaskable interrupt request 

Reset and initialize CPU 

Request for control of Address. Data 

and Control Busses 

Bus acknowledge 

CPU clock 

Power and Ground 



TYPE 

Tristate, Output 

Tristate. Bidrectionai 

Output 

Tristate. Output 

Tristate. Output 

Tristate. Output 

Tristate. Output 

Output 

Output 

Input 

Input 

Input 

Input 

Input 

Output 
Input 



Figure 7-4. Z80 CPU Signals and Pin Assignments 



7-8 



o 

< 

Q 
< 



HALT is output low following execution of a Halt instruction. The CPU now enters a Halt state 
during which it continuously re-executes a NOP instruction in order to maintain memory refresh 
activity. A Halt can only be terminated with an interrupt. 



Z80 CPU 

CONTROL 

SIGNALS 



WAIT is equivalent to the 8080A READY input. External logic which cannot respon d to a CPU 
access request within the allowed time interval extends the time interval by pulling the WAIT input low. In response to 
WAIT low, the Z80 enters a Wait state during which the CPU inserts an integral number of clock periods; taken 
together, these clock periods constitute a Wait state. 

INT and NMI are two interrupt request inputs. The difference between these two signals is that NMI has higher 
priority and cannot be disabled. 

There are two Bus control signals. 



RESET is a standard reset control input. When the Z80 is reset, this is what happens: 
The Program Counter, iV and R registers' contents are all set to zero. 
Interrupt requests via INT are disabled. 
All tristate bus signals are floated. 



Z80 BUS 

CONTROL 

SIGNALS 



BUSRQ and BUSAK are bus request and acknowledge signals. In order to perform any kin d of DM A operation, ex- 
ternal logic must acquire control of the microcomputer System Bus. This is done by inputting BUSRQ low; at the con- 
clusion of the current machine cycle, the Z80 CPU will float all tristate bus lines and will acknowledge the bus request 
by outputting BUSAK low. 



Z80 - 8080A SIGNAL COMPATIBILITY 

If you are designing a new product around the Z80 CPU, then questions of Z80 



8080A signal compatibility 



are irrelevant; you will design for the CPU on hand. 

If you are replacing an 8080A with a Z80, then it would be helpful to have some type of lookup table which 
directly relates 8080A signals to Z80 signals. Unfortunately, such a lookup table cannot easily be created. The 

problem is that the Z80 is an implementation' of three devices; the 8080A CPU, the 8224 Clock, and 8228 System Con- 
troller; but there are very many 8080A configurations that do not include an 8228 System Controller. 

Possibly the most important conceptual difference between the Z80 and 8080A involves read and write control signals. 
The 8228 System Controller develops four discrete control signals for memory read, memory write, I/O read and 
I/O write. The Z80 has a general read and a general write, coupled with an I/O select and a memory select. By 

adding logic, it would be easy enough to generate the four discrete 8080A signals from the two Z80 signal pairs; here 
is one elementary possibility: 



Z80- 
Signals 



8080A Equivalent 
Signals 



MREQ 



RD 



MREQ 



WR 



lORQ 



lORQ 



WR 




MEMR 



MEMW 



I/OR 



l/OW 



7-9 



If your design allows it, however, it would be wiser to extend the Z80 philosophy to the various support devices sur- 
rounding the CPU. Recall from our discussion of 8080A support devices in Chapter 4 that every device requires sepa- 
rate device select and device access logic. For some arbitrary read operation, timing might be illustrated as follows: 



Select 



Read 
Strobe 



With an 808 0A scheme, select l ogi c is dec oded from Address Bus lines, while strobe logic depen ds on one of th e fou r 
control lines I/OR, l/OW, MEMR or MEMW. Using the Z80 philosophy^he memory select (MREQ) or I/O select (lORQ) 
control lines become part of the device select logic, while the read (RD) or write (WR) controls generate the strobe. 



The Z80 has no interrupt acknowledge signal; rather it combines lORQ with Ml as follows: 

lORQ 



r> 



INTA 
Ml 

Some Z80 support devices also check for a "Return-from-lnterrupt" instruction object code appearing on the Data Bus 
during an instruction fetch (when Ml and RD will both be low). This condition is used to reset interrupt priorities 
among Z80 support devices. 



The 8080A HOLD and HLDA signals are functionally reproduced by the Z80 BUSRQ and BUSAK signals. 

The 8080A SYNC pulse has no direct Z80 equivalent. Ml is pulsed low during an instruction fetch, or an interrupt 
acknowledge, but it is not pulsed low during the initial time periods of an instruction's second or subsequent machine 
cycles. Frequently the complement of Ml can be used instead of SYNC to drive those 8080A peripheral devices 
that require the SYNC pulse. * 

The Z80 has no signals equivalent to 8080A INTE, WAIT or $2. There is also no signal equivalent to the 8228 
BUSEN. 

If for any reason externa! logic must know when interrupts have been disabled internally by the CPU, then theZSO will 
be at a loss to provide any signal equivalent to the 8080A control signals. Remember INTE in an 8080A system tells ex- 
ternal logic when the CPU has enabled or disabled all interrupts;since externa! logic can do nothing about interrupts 
being disabled, and requesting an interrupt at this time does neither good nor harm, knowing that the condition exists 
is generally irrelevant. 



The single Z80 WAIT input serves the function of the 8080A READY input. Irrespective of when the WAIT is requested, 
a Wait clock period will only be inserted between T2 and T3; moreover, as we will see shortly, there are certain Z80 in- 
structions which automatically insert a Wait state, without waiting for ext ernal demand. You would need relatively 
complex logic to decode instruction object codes, clock signal and the WAIT input if yourZBO system is to generate the 
equivalent of an 8080A WAIT output. In all probability, it would be simpler to find an alternative scheme that did not 
require a signal equivalent to the 8080A WAIT output. 

The Z80 simply has no second clock equivalent to 8080A 02. Any device that needs clock signal $2 cannot easily be 
used in Z80 configurations. 



The 8228 BUS EN inpu t is used by external logic to float the System Bus. In a Z80 system, CPU logic floats the System 
Bus; therefore BUSEN becomes irrelevant. 



The 8080A CPU has no signals equivalent to Z80 RFSH, HALT and NMI. 



RFSH applies to dynamic memory refresh only; it is irrelevant within the context of a Z80 - 8080A signal comparison. 
NMI, being a nonmaskable interrupt request, also has no 8080A equivalent logic. 



The Z80 HALT output needs some discussion. One of the more confusing aspects of the 8080A is the interac- 
tion of Wait, Halt and Hold states. Let us look at these three states , comparing the Z80 and 8080A configura- 
tions and in the process we will see the purpose of the Z80 HALT output. 

The purpose of the Wait state is to elongate a memory reference machine cycle in deference to slow external memory 
or I/O devices. The Wait state consists of one or more Wait clock periods inserted between T2 and T3 of a machine cy- 
cle. The 8080A and the Z80 handle Wait states in exactly the same way, except for the fact that the Z80 has no Wait 
acknowledge output and under certain circumstances will automatically insert Wait clock periods. 



7-10 



The purpose of the Hold condition is to allow external logic to acquire control of the System Bus and perform Direct 
Memory Access operations. Again both the Z80 and the 8080A have very similar Hold states. The only significant 
difference is that the Z80 initiates a Hold state at the conclusion of a machine cycle, whereas the 8080A initiates the 
Hold state during time period T3 or T4. The 8228 System Controller also needs a high BUSEN input in order to float its 
Data and Control Busses while the Z80 has no equivalent need. . 

The big difference between the Z80 and the 8080A comes within the Halt state. When the 8080A executes a Halt in- 
struction, it goes into a Halt state, which differs from a Hold state. There are some complex interactions between Hold, 
Halt, Wait and interrupts within 8080A systems. None of these complications exists in the Z80 system, since the Z80 
has no Halt state. After executing a Halt instruction, the Z80 outputs HALT low, then proceeds to continuously execute 
a NOP instruction. This allows dynamic memory refresh logic to continue operating. If you are replacing an 8080A 
with a Z80, you must give careful attention to the Halt state. This is one condition where unexpected incom- 
patibilities can arise. 



a 
o 

m 

CO 

O 

< 
o 
< 



Z80 TIMING AND INSTRUCTION EXECUTION 

Z8O timing is conceptually similar to. but far simpler than 8080A timing. Like the 8080A, the Z80 divides its in- 
structions into machine cycles and clock periods. However, all Z80 machine cycles consist of either three or four 
clock periods. Some instructions always insert Wait clock periods, in which case five or six clock periods may be pre- 
sent in a machine cycle. Recall that 8080A machine cycles may. have three,, four or five clock periods. 

The 8080A may require from one to five machine cycles in order to execute an instruction; Z80 instructions execute in 
one to six machine cycles. If we shade optional machine cycles and clock periods, Z80 and 8080A instruction time sub- 
divisions may be compared and illustrated as follows: 



MCI 


MC2 


MC3 


MC4 


MC5 


^1 


^2 


^3 


^4 


T5 


^1 


^2 


^3 


U 


^5 


^1 


h 


^3 


Ti 


T5 


^1 


■^2 


^3 


^4 


T5 


^1 


T2 


^3 


^4 4 



8080A 



MCI 



MC2 



MC3 



MC4 



MC5 



MC6 



^ 



Z80 



'2 ^ ^ ^3 



T^ T. 



^hU 



^^3^. 



\vT3 



\V^3 



EZ3 




^-r 



During input 

or output 

machine cycle 

only 



7-11 



Z80 clock signals are also far simpler than the 8080A equivalent. Where the 8080A uses two clock signals the Z80 
uses one. Clock logic may be compared as follows; 





Tl 


T2 


T3 


T4 


TS 


<t>] 


ry 


n 


n 


n 


n 


<P2 




_r\_ 






* 


' \ 


r-y 


/ \ 


r-\ 


/ V 



8080A 



280 



INSTRUCTION FETCH EXECUTION SEQUENCES 

As compared to the 8080A, Z80 instruction timing is marvelously simple. Gone is the SYNC pulse and the decod- 
ing of Data Bus for status. Every instruction's timing' degenerates into an instruction fetch, optiorially followed by 
memory or I/O read or write. Add to this a few variations for Wait state, interrupt acknowledge and bus floating and you 
are, done. ' " 

Let us begin by looking at an instruction fetch. Timing is illustrated in Figure 7-5. Look at the instruction fetch timing 
in the 8080A chapter to obtain an immediate comparison pf'the Z80 and the 8080A, 




RFSH 



Figure 7-5. Z80 Instruction Fetch Sequence 

Referring to Figure 7-5, note that the instruction fetch cycle is identified by Ml output low during Ti and T2 (®). 
Since there is no status on the Data Bus to worry about, the Program Counter contents are output immediately on the 
Address Bus and stay stable for the duration of T-) and T2. 



Since an instruction fetch is also a memory operation, MREQ and RD controls a re both output^low. This occurs half-way 
through T-], at which time the Address Bus will stabilize. The falling edges of MREQ and RD can therefore be used to 
select a memory device and strobe data out. The CPU polls data on the Data Bus at the rising edge of the T3 clock ( ). 



7-12 



< 

Q 

< 

@ 



Clock perods T3 and T4 of the instruction fetch machine cycle are used by the Z80 CPU for internal operations. 
These cloci< periods are also used to refresh dynamic memory. As soon as the Program Counter contents are taken off 
the Address Bus ((2)). the refresh address from the Refresh register is output on lines AO - A6 of the Address Bus. This 
address stays on the Address Bus until the conclusion of T4 ((3)). 

Since a memory refresh is a memory access operation, MREQ is again output low; however, it is accompanied by RFSH 
rather than RD low. Thus memory reference logic does not attempt to read data during a refresh cycle. 

A MEMORY READ OPERATION 

Memory interface logic responds to an instruction fetch and a memory read in exactly the same way. There are, 
however, a few differeces between memory read and instrucjtion fetch tirning. Memory read timing is illustrated 
in Figure 7-6. The principal difference to note is thatduririg a memory read operation, the data is sampled on the falling 
edge of the T3 clock pulse, wherea^ during an instruction fetch it is sampled on the rising edge of this clock pulse. Also 
a normal memory read machine cycle will consist of three c|ock periods, while the normal instruction fetch consists of 
four (jlock periods. Remernbenalsp that theZSO identifies'an instruction fetch machine cycle by outputting Ml low dur- 
ing the first two clock periods of the instruction fetch machine cycle. ^ 



* _J 






\^emory Read C 
T2 




L 


Tl 




T3 


k ^ 


\ 


y^ s 


^ 






AO - A15 


y MEMORY ADDR 


i 


k: 






, 








MREQ 


\ 


,_r^ 










I ,_ 


RD 
DATA BUS 


\ 


\ r^ 








1 


(00-07) 






L_f 





Figure 7-6. Z80 Memory Read Timing 




s 



DATA BUS 
(DO - D7) 



Tl 



Memory Write Cycle 



T2 



\ , 1 



T3 



MEMORY ADDR 



B 



\. 



DATA OUT 



e 



• Figure 7-7. Z80 Memory Write Timing 

MEMORY WRITE OPERATION 

Figure 7-7 illustrates memory write timing for the Z80. The only differences between memory read and memory 
write tjming are the obvious ones: WR is pulsed low for a write, and can be used as a strobe by memory interface 
logic to read' data off the Data Bus. 



7-13 



THE WAIT STATE 

Like the 808QA, the Z80 pllqws a Wait state to occur between clock periods T2 and T3 of a machine cycle. The 

Wait state frees external logic or memory from having to operate at CPU speed. 



The Z80 CPU samples th^ WAIT input on the falling edge of <I> during T2. Providing WAIT is low on the falling edge of 
4> durin g T2. W ajt clock periods will be inser|ed. The numb er of W ait clock periods inserted depends strictly on how 
long the WAlt inpqt is held low. As soon as the Z80 detects WAIT high on the falling edge of <l>. it will initiate T3 on 
the next rising edge of $. 



Note th^t the single Z8,0 VV^^IT signal replaces the READY and WAIT 8080A signals. As this would imply, no sig- 
nal is output telling external logic the ZSOtjas entered the Wait state, In the event that external logic needs to know 
whetl^er or not a Wait' state has been entered, these are the rules: 



1) The Z80 will sample WAIT on the falling' edge of <l> in T2. 

2) If WAIT is low, then the Z80 will continue to sample the WAIT input for all subsequent Wait state clock periods. 



3) The Z80 will not sample the WAIT input during any clock period other than T2 or a Wait state. 
Figure 7-8 illustrates Z80 Wait state timing. 



Ml Cycle 




-:"j—v:-:"s. 



j—^ 



Figure 7-8. Z80 Wait State Timing 

INPUT OR OUTPUT GENERATION 

Timing for Z80 input and output generation is given in Figures 7-9 and 7-10. 

The important point to note is thatZilog has acknowledged the infrequency with which typical I/O logic can operate at 
CPU speed. One Wait clock period is therefore automatically inserted between T2 and T3 fo r all in pMt or output 
machine c ycles. Otherwise timing differs from mennpry read and write operations only in that lORQ is'output low 
i-ather than MREQ. - 

Note that there is absolutely nothing to prevent you from selecting I/O devices within the memory space. This is some- 
thing we did consistently in the SOSQA chapter when describing 8080A support devices. But if you adopt this design 
policy, remerriber that your I/O logic must execute at CPU speed, unless you insert Wait states. 



7-14 



z 
oc 
o 
m 

(A 

o 

< 
o 

< 



Forced 
Wait 
State 



AO ~A7 
lORQ 

"rd 

DATA BUS 
WAIT 

WR 
DATA BUS 



. — \ : — V 



PORT ADDRESS 



zrzz. 



T3 



\_-^ — \_ 



-Gn> 



) 



Read 
Cycle 



Write 
Cycle 



Figure 7-9. Z80 Input or Output Cycles 



Forced 
Wait 
State 









T2 
1 


T„ 




T« 


T3 


I 




<J> 


r ■■ 


\ 


\ 










\ 








AO ~ A7 


i 


PORT ADDRESS \ 






I 






1 










lORQ 




r~ 










/ 




fiTH 












/ 




LliL) 




RD 





\ 


r— 


— 











11/ 


r~ 








WAIT 


U l_-_ 






/ 




OUT 






~\ 






























WR 




\ 


/ 























READ 
CYCLE 



WRITE 
CYCLE 



Figure 7-10. Z80 Input or Output Cycles with Wait States 

BUS REQUESTS 

The Z80 does not have a Hold state as described for the 8080A, but Z80 bu s reques t logic i s equiva lent. The Z80 will 
float Address, Data and tristate Control Bus lines upon sensing a lo w BUSR Q signal. BUSRQ is sampled by the 
■ Z80 CPU on the rising edge of the last c lock pu lse of any machine cycle. If BUSRQ is sa mpled lo w, then tristate lines are 
floated by the CPU, which also outp uts BUSAK low. The Z80 CPU continues to sample BUSRQ on the rising edge of ev- 
ery clock pulse. As soon as BUSRQ is sensed high, floating will cease on the next clock pulse. This timing is illustrated 
in Figure 7-1 1. 



7-15 



One significant difference between the Z80 and 8080A results from differences between the IHold and bus 
floating states. As the logic we have described for the Z80 would imply, it will only float the System Bus in between 
machine cycles. The 8080A, on the other hand, will enter a Hold state variably during T3 or T4 of the machine cycle, 
depending on the type of operation in progress. It is therefore possible for the Z80 to float its bus three clock periods 
later than an 8080A in a similar configuration. 




Figure 7-1 1 . Z80 Bus Timing 





Last M Cycle _ j 








<t> 


of Inst 


ruction 1 

Last T State 




Tl 


T2 


Forced W 


ait State 


T3 


.\ 


\ 




\ 


\ 


\ 


On 


\ 










INT 


\ 


[ 










\ 









AO -A15 






I 


PC 




j 


]f REFRESH 












, 




/ 


*■;• 


Ml 






\ 


J 








/ 


MREQ 












/ 


\_ 


lORQ 










\ 


J 




/ /~Tr 














A {.I! 


J 


WAIT 












L/L . 




















RD 

















Figure 7-12. Z80 Response to a Maskable Interrupt Request 

Note also that if you are using the dynamic memory refresh logic of the Z80, then during long bus floats, external 
logic must refresh dynamic memory. The simplest way around this problem in a Z80 system is to ensure that DMA 
operations acquire the System Bus for many short periods of time, rather than for a single long access. 

EXTERNAL INTERRUPTS 

The Z80 has two interrupt request input signals, one of which cannot be disabled. 

Timing for the lower priority interrupt request acknowledge sequence differs significantly from the single 
8080A interrupt i^equest, and is illustrated in Figure 7-12. 

The interrupt request signal INT is sampled by the Z80 CPU on the rising edge of the last clock pulse of any instruc- 
tion's execution. . 



7-16 



z 

E 

o 

CD 
CO 
O 

< 
< 
@ 



An interrupt request will be denied if interrupts have been disabled under program control, or if tfie BUSRQ signal is 
also low. Thus a DMA access will have priority over maskable interrupts. 



The Z80 CPU acknowledges an interrupt request by outputting Ml and lORQ low. This occurs in a special interrupt 
acknowledge machine cycle, as illustrated in Figure 7-12. Note that this machine cycle has two Wait states inserted so 
that external logic will have time for any type of daisy chained priority interrupt scheme to be implemented. 



When lORQ is output low while M1 is low, external logic must interpret this signal combination as requiring an 
interrupt vector to be placed on the Data Bus by the acknowledged external interrupt requesting source. This 
interrupt vector can take one of three forms; the form depends on which of the three modes you have selected for 
the Z80 under program control. 

In Mode 0, the interrupt vector will be interpreted as a single-byte object code, representing the first instruction to be 
executed following the interrupt acknowledge. This is equivalent to the standard RST instruction response used by 
the 8080A. Whenever you are replacing an 8080A with a Z80, therefore, the Z80 must operate in interrupt response 
Mode 0. 

Z80 interrupt response logic in Mode 1 automatically assumes that the first instruction executed following the in- 
terrupt response will be a Restart, branching to memory location 0038i 9. If the Z80 is in Mode 1 , no interrupt vec- 
tor is needed. 

Z80 Mode 2 interrupt response has no8080A equivalent. When you operate the Z80 in Mode 2, you must create a 
table of 16-bit interrupt address vectors, which can reside anywhere in addressable memory. These 16-bit ad- 
dresses identify the first executable instruction of interrupt service routines. When an interrupt is acknowledged by the 
CPU in Mode 2, the acknowledged external logic must place an interrupt response vector on the Data Bus. The 
Z80 CPU will combine the IV register contents with the interrupt acknowledge vector to form a 1 6-bit address, 
which accesses the interrupt address vector table. Since 1 6-bit addresses must lie at even memory address bound- 
aries, only seven of the eight bits provided by the acknowledged external logic will be used to create the table address; 
the low order bit will be set to 0. Thus the table of 16-bit interrupt address vectors will be accessed as follows: 



Interrupt response 
IV Register vector from external logic 

III! 



INTERRUPT 
ADDRESS 
VECTORS 




16-bit address points to first 

of tv/o bytes in Interrupt Address Vector 



JJ 



JJ 



KK 



KK 



LL 



LL 



MM 



MM 



NN 



NN 



The Z80 CPU will execute a Call to the memory location obtained from the interrupt address vector table. 

Let us clarify this logic with a simple example. Suppose that you have 64 possible external interrupts; each interrupt 
has its own interrupt service routine, therefore 64 starting addresses will be stored in 128 bytes of memory. Let us ar- 
bitrarily assume that these 128 bytes are stored in a table with memon/ addresses OFOO15 through 0F7Fi6- Now in 



7-17 



order to use Mode 2, you must initially load the value OFi q into the Z80 IV register. Subsequently an external interrupt 
request is acknowledged and the acknowledged external logic returns on the Data Bus the vector 2E15; this is what 
will happen: 



IV Register 
OF 



Interrupt response 
from external logic 

00101110 



OF i 2E 




Push previous 
contents onto 
Stack 



2080, g to Program Counter. 
First post-interrupt instruction 
object code fetched 
from here 



MEMORY 


Memory 
Address 


JJ 


0F28 


JJ 


0F29 


KK 


0F2A 


KK 


0F2B 


LL 


0F2C 


LL 


0F2D 


80 


0F2E 


20 


0F2fK 


NN 


0F30 > 


NN 


0F31 


PP 


OF32 


PP 


OF33 y 


1 1 


-^ 




207F ^ 




2080 '^ 




2081 




2082 




2083 



If two Wait states are insufficient for external logic to arbitrate interrupt priorities and place 
the required vect or on th e Data Bus, then additional Wait states can be inserted in the usual 
way by inputting WAIT low. Timing is illustrated in Figure 7-13. 



Z80 WAIT 

STATES 

DURING 

INTERRUPT 

ACKNOWLEDGE 




Figure 7-13. Wait States During Z80 Response to a Maskable Interrupt Request 



7-18 



o 

EQ 

o 

< 
a 

< 

© 



The nonmaskable interrupt differs from the masl<able interrupt in two significant ways. 

First of all the nonmaskable interrupt has priority over both the maskable interrupt and bus re- 
quests. 

Next, the nonmaskable interrupt operates in Mode 1 only. Following the interrupt acknowledge, an RST instruction will 
always be executed, with a Call to memory location 0066-| 5- No other RST instruction can be executed and no interrupt 
vector should be placed on the Data Bus; if a vector is placed on the Data Bus, it will be ignored. 

Nonmaskable interrupt timing is illustrated in Figure 7-14. 



'!> 


Last M 














Tl 





Last T Time 


Tl 


T2 ^3 


T4 


\ 


\ 




\ 


\ 


\ 


\ : 




\ 1 
















NMI 


: ^ 


J 
































AO - A15 






I 


PC 


I 


REFRESH 


I 
























Ml 






1_ 


J 












MREQ 








\ 


J L_ 


r- 














RD 








\ 


J 












RFSH 










J 









Figure 7-14. Z80 Response to a Nonmaskable Interrupt Request 

THE HALT INSTRUCTION 

When a Halt instruction is executed by the Z80 CPU, a sequence of NOP instructions is executed until an interrupt re- 
quest is received. Both maskable and nonmaskable interrupt request lines are sampled on the rising edge of O during 
T4 of every NOP instruction's machine cycle. 

The Halt state will terminate when any interrupt request is detected, at which time the appropriate interrupt 
acknowledge sequence will be initiated, as illustrated in Figures 7-13 and 7-14. 

Note that the Z80 executes the sequence of NOP instructions during a Halt so that it can continue to generate dynamic 
memory refresh signals. 

Halt instruction timing is illustrated in Figure 7-15. 













<t> 


T4 


Tl 


IV 


1 1 — 

T3 


T4 


Tl 


T? 


' \ 


\ 


\ 


\ \ 


\ 


\ 






r^ ^ 




HALT 




\ 


^^w— 












/ 


NMI 


T 





r 


"^ 


r— 










HALT INSTRUCTION 










IS RECEIVED 










DURING THIS 










MEMORY CYCLE 









Figure 7-15. Z80 Halt Instruction Timing 



7-19 



The following abbreviations are used in this chapter: 



A,F,B,C,D,E.H.L 


The 8-bit registers. A is the Accumulator and F is the Program' Status Word. 


AF'.BCDE'.HL' 


The alternative register pairs 




addr 


A 16-bit memory address 




x(b) 


Bit b of 8-bit register or memory location x 




cond 


Condition for program branching. Conditions are: 

NZ - Non-Zero (Z=0) 

Z - Zero(Z=1) 

NC - Non-carry (C=0) 

C - Carry (C = 1) 

PO - Parity Odd (P=0) 

PE - Parity Even (P = 1) 

P - Sign Positive (S=0) 

M - Sign Negative (S = 1) 




data 


An 8-bit binary data unit 




dataie 


A 16-bit binary data unit 




disp 


An 8-bit signed binary address displacement 




xx(HI) 


The high-order 8 bits of a 16-bit quantity xx 




IV 


Interrupt vector register (8 bits) 




IX.IY 


The index registers (16 bits each) 




xy 


Either one of the Index registers (IX or lY) 




LSB 


Least Significant Bit (Bit 0)" 




label 


A 16-bit instruction memory address 




xx(LO) 


The low-order 8 bits of a 16-bit quantity xx 




MSB ■ 


Most Significant Bit (Bit 7) 




PC 


Program Counter 




port 


An 8-bit I/O port address 




P."" 


Any of the following register pairs: 
BC 
DE 
HL 
AF 




R 


The Refresh register (8 bits) 




reg 


Any of the following registers: 
A 
B 
C 
D 




rp 


E 
H 
L 

Any of the following register pairs: 
BC 
DE 
HL 
SP 




SP 


Stack Pointer (16 bits) 





7-20 



o 



Statuses The Z80 has the following status flags: 

C - Carry status 

Z - Zero status 

S - Sign status 

P/0 - Parity/Overflow status 

Aq - Auxiliary Carry status 

N - Subtract status 

The following symbols are used in the status columns: 

X - flag is affected by operation 

(blank) - flag is not affected by operation 

^ 1 - flag is set by operation 

— - flag is reset by operation 

uj ? - flag is unknown after operation 

< P - flag shows parity status 

5 - flag shows overflow status 

to I - flag shows interrupt enabled/disabled status 

** [ ] Contents of location enclosed within brackets. If a register designation is enclosed within the 

^j brackets, then the designated register's contents are specified. If an I/O port number is enclosed 

z within the brackets, then the I/O port contents are specified. If a memory address is enclosed within 

o the brackets, then the contents of the addressed memory location are specified. 

o [[ ]] Implied memory addressing; the contents of the memory location designated by the contents of a 

5 register. 

Q A Logical AND 

^ V Logical OR 

•V- Logical Exclusive-OR 

^- Data is transferred in the direction of the arrow 

" ► Data is exchanged between the two locations designated on either side of the arrow. 

The fixed part of an assembly language instruction is shown in UPPER CASE. 

The variable part (immediate data, I/O device number, register name, label or address) is shown in lower case. 



7-21 



•Address Bus: A0-A7: [Cl 
A8-A15: [B] 



Table 7-2. A Summary of the Z80 Instruction Set 











STATUS 




TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 




OPERATION PERFORMED 






















C 


z- 


s 


P/O 


Ac 


N 






IN 


A.port 


2 














[A] -[port] 
Input to Accumulator from directly addressed I/O port. 
Address Bus: A0-A7: port 
A8-A15: [A] 




IN 


reg,{C) 


2 




X 


X 


P 


X 


0. 


[regl-[[C]] 
Input to register from I/O port addressed by the contents of C* 
If second byte is 70^g only the flags will be affected. 




INIR 




2 




1 


? 


.7 


? 


1 


Repeat until [B]=0: 

[[HLll-HC]] 

[B]-[B1-1 

[HL]-[HL]+1 
Transfer a block of data from I/O port addressed by contents of C to memory location ad- 
dressed by contents of HL, going from low addresses to high. Contents of B serve as a count of 
bytes remaining to be transferred.* 




INDR 




2 




1 


7 


7 


7 


1 


Repeat until [Bl-0: 

[[HL]]-[[C]1 

[Bl-[B]-1 

[HL]— [HU-1 
Transfer a block of data from I/O port addressed by contents of C to memory location ad- 
dressed by contents of HL, going from high addresses to low. Contents of B serve as a count of 


5 




















bytes remaining to be transferred.* 




INI 




2 




X 


? 


7 


7 


1 


l[HL]l-[[C]] 

[B]-[B]-1 

[HL]-[HL] + 1 
Transfer a byte of data from I/O port addressed by contents of C to memory location addressed 
by contents of HL. Decrement byte count and increment destination address.* 




IND 




2 




X 


? 


7 


7 


1 


[[HL]]'-[[C]] 

[B1-[B]-1 

[HL]— [HL]-1 
Transfer a byte of data from I/O port addressed by contents of C to memory location addressed 
by contents of HL Decrement both byte count and destination address.* 




OUT 


port,A ■ 


2 














[portl-[Al 
Output from Accumulator to directly addressed I/O port. 
Address Bus: A0-A7: port 
A8-A15: [A] 




OUT 


(C).reg 


2 














[[C]]-[regJ 
Output from register to I/O port addressed by the contents of C* 




OTIR 


- ■ 


2 




1 


7 


7 


7 


I 


Repeat until [B]=0: 

[(C]]-[[HL]] 

[B]-[Bl-1 

[HL]-[HL]+1 
Transfer a block of data from memory location addressed by contents of HL to I/O port ad- 
dressed by contents of C, going from low memory to high. Contents of B serve as a count of 
bytes remaining to be transferred.* 



ADAM OSBORNE & ASSOCIATES. INCORPORATED 



•Address Bus: A0-A7: [C] 
A8-A15; [B] 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERANDIS) 


BYTES 


STATUS 


OPERATION PERFORMED 


C 


Z 


s 


P/0 


Ac 


N 


1 

3 
_C 

C 

o 
o 

o 


OTDR 

OUTl 
OUTD 




2 

2 
2 




1 

X 
X 


? 

7 

? 


7 

7 

7 


7 

7 
7 


1 

1 
1 


Repeat until [BlK): 

([C]]-[[HLl] 

[B]-[B1-1 

[HLl— [HLl-1 
Transfer a block of data from memory location addressed by contents of HL to I/O port ad- 
dressed by contents of C, going from high memory to low. Contents of B serve as a count of 
bytes remaining to be transferred.* 

[[C]]-[[HLl] 

IB]-[B1-1 

[HLl-[HL] + 1 
Transfer a byte of data from memory location addressed by contents of HL to I/O port ad- 
dressed by contents of C. Decrement byte count and increment source address.* 

[[Cll-[[HLll 

[B]-[B]-1 

[HL]^[HLl-1 
Transfer a byte of data from memory location addressed by contents of HL to I/O port ad- 
dressed by contents of C. Decrement both byte count and source address.* 


lU 

u 

z 

lU 

e 

lU 

u. 

lU 
K 

>- 
cc 
o 

lU 

> 

E 

< 
£ 

OL 


LD 
LD 
LD 

LD 
LD 
LD 

LD 
LD 
LD 
LD 
. LD 
LD 


A,(addr) 

HL,(addr) 

rp,(addr) 
xy,(addr) 

(addr),A 

(addr).HL 

(addr),rp 
(addr),xy 

A,(BC) 
A.(DE) 
reg.lHL) 

(BC),A 
(DE),A 
(HLlreg 

reg,(xy + disp) 

(xy + dispj.rog 


3 
3 
4 

3 
3 
4 

1 

1 
1 

1 , 
3 
3 














[A]*-[addr] 

Load Accumulator from directly addressed memory location. 
[Hi— [addr+11. [Ll— laddrl 

Load HL from directly addressed memory. 
[rp(HI)]— [addr+1], [rp(LO)]— [addrl or 
[xy<HI)]— [addr+1], [xy(LO)]— laddrl 

Load register pair or Index register from directly addressed menrxjry. 
[addr]-[A] 

Store Accumulator contents in directly addressed memory location, 
laddr+n— [Hi, [addrl-[Ll 

. Store contents of HL to directly addressed memory location. 
[addr+ 1]— [rp(HI)l, laddrl— [rp(LO)l or 
[addr+ 11-Ixy(HI)l, [addrl-[xy(LO)l 

-Store contents of register pair or Index register to directly addressed memory. 
[Al-[[BC]lorlAl-I[DEl] 

Load Accumulator from memory location addressed by the contents of the specified register pair. 

[regl-[[HL]l 

Load register from memory location addressed by contents of HL. 
[[BClI-[Alor[[DEll-[Al 

Store Accumulator to memory location addressed by the contents of the specified register pair. 
[[HLll-Eregl 

Store register contents to memory location addressed by the contents of HL 
[regl— [[xyl + disp] 

Load register from memory location using base relative addressing, 
[[xyl + disp]— I regl 

Store register to memory location addressed relative to contents of Index register. 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 











STATUS 




TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 




OPERATION PERFORMED 


C 


Z 


s 


P/O 


Ac 


N 




LDIR 




2 

















Repeat until [BCl-0: 

[[DE]]>-[[HL]] 

[DE]-tDE]+1 

[HL>-[HL] + 1 

[BC]*-[BC]-1 
Transfer a block of data from the memory location addressed by the contents of HL to the 
memory location addressed by the contents of DE, going from low addresses to high. Contents 
of BC serve as a count of bytes to be transferred. 




LDDR 




2 














. 


Repeat until [BCl=0: 
[[DE]]-[[HL]] 
[DE]-(DE]-1 
[HL]-[HL]-1 
[BC]-(BC]-1 
Transfer a block of data from the memory location addressed by the contents of HL to the 
^.-iiOTiemory location addressed by the contents of DE, going from high addresses to low. Contents 


X 

u 




















of BC serve as a count of bytes to be transferred. 


< 


LDI 




2 








X 








[[DE]]-[[HL]] 


UJ 




















[DEi— [DE] + 1 


2 




















[HLl— [HU+1 


< 




















■IBCI— [BC]-1 


UJ 




















Transfer one byte of data from the memory location addressed by the-contents of HL to the 


OT 

z 




















- memory location addressed by the contents of DE. Increment source and destination addresses 




















- --and decrement byte count. 


cc 


LDD 




2 








X 








[[DE]]-[[HL]] 


O 




















[DE]-tDE]-1 


o 

-1 




















[HL]— [HLl-1 


CD 




















[BC]— [BCl-1 
Transfer one byte of data from the memory location addressed by the contents of HL to the 
memory location addressed by the contents of DE. Decrement source and destination addresses 
and byte count. 




CPIR 




2 




X 


X 


X 


X 


1 


Repeat until [A] = [[HL]] or [BC]=0: 

[A] - [[HL]] (only flags are affected) 

[HL]*-[HL]+1 

[BC]— [BC]- 1 
Compare contents- of Accumulator with those of memory block addressed by contents of HL, 
going from low addresses to high. Stop when a match is found or when the byte count becomes 




CPDR 




2 




X 


X 


X 


X 


1 


zero. 
Repeat until [A]^[[HL]] or [BC]=0-. 
[A] - [[HL]] (only flags are affected) 
[HL]— [HL]-1 
[BC]— [BC]-1 

Compare contents of Accumulator with those of memory block addressed by contents of HL, 

going from high addresses to low. Stop when a match is found or when the byte count becomes 

zero. 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 















STATUS 






TYPE. 


MNEMONIC 


OPERAND(S) 


BYTES 












OPERATION PERFORMED 


C 


z 


S 


P/0 


Ac 


N 


a 


CPI 




2 




X 


X 


X 


X 


1 


lAl - [[HLUtonV flags are attected) 


11 




















[HLl— [HLl + 1 


£l 




















[BCl— [BCl-1 


feg 




















Compare contents of Accumulator with those of memory location addressed by contents of JHL. 


|a. 




















Increment address and decrement byte count. 


Si 
•- o 

o < 
o "" 

1 CA 


CPD 




2 




X 


X 


X 


X 


1 


[Al - [[HLll (only flags are affected) 




















[HL]-[HL1-1 




















[BC]— [BC]-1 


ca 




















Compare contents of Accumulator with those of memory location addressed by contents of HL 
[}ecrement address and byte count. 




ADD 


(HL) 
(xy + disp) 


1 
3 


X 


X 


X 





X 





[Al— [A1+ [[HL]] or [A]— [A]+ [[xv] + displ 
Add to Accumulator using Implied addressing or tiase relative addressing. . 




ADC 


(HL) 


1 


X 


X 


X 


.0.^. 


X 





[A]-[A]+ [[HL]] + Cor [A]t-[A]+ [[xy] + disp] + C 


lU 

O 




(xy + disp) 


3 














Add with Carry using implied addressing or base relative addressing. 


z 

Ul 
E 
lU 


SUB 


(HL) 


1 


X 


X 


X 





X 


1 


[A]-[Al- [[HL]]or [A]-[A]- [[xyl + disp] 




(xy + disp) 


3 














Subtract from Accumulator using implied addressing or base relative addressing. 


UJ 
K 


SBC 


(HL) 


1 


X 


X 


X 





X 


1 


[A]'-[A]-[[HLl-Cor [A]-[AI- [[xy) + disp]-C 


■ > 




(xy + disp) 


3 














Subtract with Carry using implied addressing or base relative addressing. 


o 


AND 


(HL) 


1 





X 


X 


p 


1 





["a]-[A1 a [[HL]] or [A]-[A] A [[xy] + displ 


Ul 




(xy + disp) 


3 














AND with Accumulator using implied addressing or base relative addressing 


s 


OR 


(HL) 


1 





X 


X 


p 


1 





[A]-[ A] V [[HL]] or [Al-[A] V ([xy] + disp] 


>- 

K 




(xy + disp) 


3 














OR with Accumulator using implied addressing or base relative addressing. 


< 

a 


XOR 


(HU 


1 





X 


X 


p 


1 





[A]*-[A]-¥[[HL]lor [A]-[A]V-[[xy] + disp] 


z 
o 




(xy + disp) 


3 














Exclusive-OR with Accumulator using implied addressing or base relative addressing. 


o 

Ul 


CP 


(HL) 


1 


X 


X 


X 





X 


1 


[Al-[[HL]]or [Al- [[xy] + disp] 


w 


INC 


(xy + disp) 


3 














Compare with Accumulator using implied addressing or base relative addressing. Only the flags 
are affected. 






(HL) 


1 




X 


X 





X 





[[HL]]-[[HL]] + 1 or [[xY] + disp]-[[xy] +disp] + 1 






(xy + disp) 


3 














Increment using implied addressing or base relative addressing. 




DEC 


(HL) 
(xy + disp) 


1 
3 




X 


X 





X 


1 


[[HL]1-[[HL]]- 1 or [[xv] + displ-[[xy] + disp]- 1 
Decrement using implied addressing or bass relative addressing. 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 



OPERAND(S) 



OPERATION PERFORMED.: 



RRC 



(HU 
(xy + disp) 



(HU 
(xy + disp) 



(HU 
(xy + disp) 



(HU 
(xy + disp) 



(HU 
(xy + disp) 



(HU 
(xy + disp) 



(HU 
(xy + disp) 



reg.data 

rp,data16 

xy,data16 

(HU,data 

(xy + disp),data 



EK^ 



7 •^- 



f= 



[[HL]]or [[xyl + disp] 
Rotate contents of.memory location (implied or base relative addressing) left with branch Carry. 



Roti 



P 



[[HLllor [t xyl + disp] 
Rotate contents of memory location left through Carry. 



^ o | * ^| c ] 



tCHUlor [[xyl+disp] 
Rotate contents of memory location right with branch Carry. 



^ 



[[HLllor t[xy] + displ 
Rotate contents of memory location right through Cany. 



m — HiH 

jh Cany. 



|cT^ — 17 *a 

[[HLllor [[xyl + displ 
Shift contents of memory location left and clear LSB (Arithmetic Shift). 



^ 



-► ofr — ►fcl 



[[HLllor [[xyl+displ 
Shift contents of memory location right and preserve MSB (Arithmetic Shift). 



'-K 



]— H3 



[[HLllor [[xyl + displ 
Shift contents of memory location right and clear MSB (Logical Shift). 



[regl<— data 

Load immediate intoregister. 
• [rpl— ^ata16 or [xyl— dataie 

Load 16 bits of immediate data Into register pair or Index register. 
[[HLll— data or [[xyl + displ— data 
Load immediate into memory location using implied or base relative addressing. 



© ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 7-2. A SummatY of the Z80 Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUS 


OPERATION PERFORMED 


C 


z 


s 


P/0 


Ac 


N 


0. 

S 

3 
-> 


JP 
JR 
JP 


label 

disp 

(HL) 
Ixy) 


3 • 

2 

1 
2 














[PC] -label 

Jump to instruction at address represented by label. 
[PCI— (PC] + 2 + disp 

1. Jump relative to present contents of Program Counter. 
[PC]-[HLjor [PCl— [xy] 

Jump to address contained in HL or Index register. 


Is 
g i 


CALL 

CALL 
RET 

hET 


* 
label 

cond.label 

cond 


3 

3 

t 

1 














.[[SP]-1]-[PaHI)J 
[[SP]-2l-[PaL0)] 
[SP]— [SPl-2 
[PCl— label 

Jump to subroutine starting at address represented by label. 
Jump to subroutine if condition is satisfied; otherwise, continue in sequence. 
[PC(LO)]-[[SP)] 
[PaHi)]-[[SP)+1] 
(SPl— [SPl + 2 

Return from subroutine. 
Return from subroutine if condition is satisfied; otherwise, continue in sequence. 


S 

E 
111 
0. 
O 
111 

o 
111 

S 


■ ADD 
ADC 
SUB 
SBC 
AND 
OR 
XOR 
CP 


data 
data 
data 
data 
data 
data 
data 
data 


2 
2 
2 
2 
2 
2 
2 
2 


X 
X 
X 
X 



X 


X 
X 
X 
X 
X 
X 
X 
X 


X 
X 
X 
X 
X 
X 
X 
X 


o 





P 
p 
p 




X 
X 
X 
X 

1 

1 
1 

X 





1 
1 





1 


[A]-[Al + data 

Add immediate to Accumulator. 
[Al— [A] + data + C 

Add immediate with Carry. 
[Al-[A]-data 

Subtract immediate from Accumulator. 
[A]— [Al-data-,C 

Subtract immediate with Carry. 
[A]— [AlAdata 

AND immediate with Accumulator. 
[Al— [AlVdata 

OR Immediate with Accumulator. 
[A]-[Al-V-data 

Exclusive-OR immediate with Accumulator. 
[A] -data 

Compare immediate data with Accumulator contents; only the flags are affected. 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 











STATUS 




TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 




OPERATION PERFORMED 


C 


2 


s 


P/O 


Ac 


N 




JP 


cond.label 


3 














If cond, then [PC] — label 
Jump to instruction at address represented by label if the condition is true. 


Z 

o 


JR 


Cdisp 


2 














If C=1,then [PC]— [PC]+2 + disp 




















Jump relative to contents of Program Counter if Carry flag is set. 


5 

2 


JR 


NCdisp 


2 














If C=0, then [PC]<-[PC] +2 + disp 


O 




















Jump relative to contents of Program Counter if Caw/ flag Is reset. 


o 

2 


JR 


Z.disp 


2 














If Z=1, then [PC]— [PC] + 2 + disp 


O 




















Jump relative to contents of Program Counter if Zero flag is set. 


Q. 


JR 


NZ.disp 


2 














If Z=0, then [ PC]— [ PC] + 2 + disp 


3 


DJNZ 


disp 


2 














Jump relative to contents of Program Counter if Zero flag is reset. 
[Bl-[B]-1 
If [B]jfeO, then [PC]— [PCl + 2 + disp 

Decrement contents of B and Jump relative to contents of Program Counter if result Is not 0. 




LD 


dst.src 


1 














[dst]— [src] 
Move contents of source register to destination register. Register designations src and dst may 
each be A, B, C, D, E, H or L. 




LD 


A.IV 


2 




X 


X 


1 








[A]-[IV] 
Move contents of Interrupt Vector register to Accumulator. 




LD 


A,R 


2 




X 


X 


1 








[A]-[R] 


1 




















Move contents of Refresh register to Accumulator. 


LD 


IV,A 


2 














[IV]-[A] 


oc 




















Load Interrupt Vector register from Accumulator. 


1- 


LD 


R,A 


2 














[R]-[A] 


5 




















Load Refresh register from Accumulator. 


UJ 

CC 


LD 


SP.HL 
















[SP]-[HL] 


Ul 




















Move contents of HL to Stack Pointer. 


1- 


LD 


SP.xy 
















[SP]-[xy] 






















Move contents of Index register to Stack Pointer. 


E 


EX 
EX 
EXX 


DE,HL 
AF.AF 
















[DE]— >[HLl 

Exchange contents of DE and HL. 
[AF]. >[AF] 

Exchange program status and alternate program status. 
/[BC1\ /[BC]\ 

[DE]|— ([DE] 
\[HL]/ \[HL']/ 

Exchange register pairs and altemate register pairs. 



ADAM OSBORNE & ASSOCIATES. INCORPORATED 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERANDIS) 


BYTES 


STATUS 


OPERATION PERFORMED 


C 


z 


s 


P/0 


Ac 


N 


i 

lU 

0. 

o 

ce 
IS 

M 

5 

111 

ce 
ce 

« 

5 
111 

ce 


ADD 
ADC 
. SUB 
SBC 
AND 
OR 
XOR 
CP 
ADD 
ADC 
SBC 
ADD 
ADD 


reg 
reg 
reg 
reg 
reg 
reg 
reg 
reg 
HL.rp 
HUrp 
HUrp 
IX.PP 
IY,rr 


1 
1 

1 
1 
1 
1 
1 
1 
1 
2 
2 
2 
2 


X 
X 
X 
X 



X 
X 
X 
X 
X 
X 


X 
X 
X 
X 
X 
X 
X 
X 

X 
X 


X 
X 
X 
X 
X 
X 
X 
X 

X 
X 







P 
p 
p 







X 
X 
X 
X 

1 

1 
1 

X 

7 
7 
7 

7 
7 




1 
1 




1 




1 





[A]-[Al+[regl 

Add contents of register to Accumulator. 
[Al— [A]+(regl + C 

Add contents of register and Cany to Accumulator. 
[Al-[Aj- [reg] 

Subtract contents of register from Accumulator. 
[A]-[A]-[reg]-C 

Subtract contents of register and Cany from Accumulator. 
[Al-EAl A [regl 

AND contents of register with contents of Accumulator. 
[A]-[AlV[reg] 

OR contents of register with contents of Accumulator. 
[A]-[AlV[regl 

Exclusive-OR contents of register with contents of Accumulator. 
[Al-[regl 

Compare contents of register with contents of Accumulator. Only the flags are affected. 
[HL]«-[HU+(rp] 

16-bit add register pair contents to contents of HL 
[HL]-[HU+[rp] + C 

16-bit add with Cany register pair contents to contents of HL 
[HLl— [HLl- [rp]-C 

16-bit subtract with Carry register pair contents from contents of HL 
[1X1— [1X1+ [pp] 

16-bit add register pair contents to contents of Index register IX (pp=BC, DE, IX, SP) 
[lYl-[IY]+[rrl 

16-bit add register pair contents to contents of Index register lY (rr»6C, DE, lY, SP). 


iij 

i 

o 

cc 

IS 

M 

5 
111 

ce 


DAA 
CPL 
NEG 
INC 
INC 
DEC 
DEC 


reg 

rp 
xy 
reg 

■ 
rp 

xy 


1 

1 

2 

1 

1 

2 

1 
2 


X 
X 


X 

X 
X 

X 


X 

X 
X 

X 


p 




p 


X 

1 

X 
X 

X 


1 
1 



1 


Decimal adjust Accumulator, assuming that Accumulator contents are the sum or difference of 
BCD operands. 

[Al-[7^] 

Complement Accumulator (ones complement). 
[A]-[;^l+1 

Negate Accumulator (twos complement), 
[regl— [regr+ 1 

Increment register contents, 
[rpl— [rpl+1 or [xyl— [xyl + 1 

Increment contents of register pair or Index register. 
[regl— [regl- 1 

Decrement register contents, 
[rpl— [rpl- lor [xyl— [xyl- 1 

Decrement contents of register pair or Index register. 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUS 


OPERATION PERFORMED 


C 


z 


s 


P/0 


Ac 


N 


111 

O 

E 

D 
Z 
< 
(- 
u. 

X 

w 

^ 
v> 

5 
tu 
c 


RLCA 
RLA 
RRCA 
RRA 
RLC 
RL 
RRC 
RR 

SLA 
SRA 


reg 

reg 

reg 

reg 

reg 
reg 


1 

1 

1 
1 
2 
2 
2 
2 

2 
2 


X 
X 
X 
X 
X 

k 

X 

X 

X 
X 


X 

X 

X 

X 

X 
X 


X 

X 

X 

X 

X 
X 


p 

p 

p 

p 

p 
p 































6 





r^v^^H 7 ^ oW 

[A] 
Rotate Accumulator left with branch Carry. 


1 J^ 1 7^ oW 

[A] 

Rotate Accumulator left through Carry. 


L^ 7 ► |-A-Hc| 

[A] 

Rotate Accumulator right with branch Carry. 


L^7 ► o| ^C| 1 

I A) 
Rotate Accumulator right through Cany. 


Jc|-^-i-f7 -^ ol-*J 

[reg] 
Rotate contents of register left with branch Carry. 


L-ICJ.— J7 ^ 0|^.^ 

[reg] 
Rotate contents of register left through Carry. 


1-^7 ► o|-i-Mc| 

[reg] 
Rotate contents of register right with branch Carr/. 


L^7 ► 0| »^C|— 1 

[reg] 
Rotate contents of register right through Cany. 


(cj-^ (7 -^ oJ-^-o 


[reg] 
Shift contents of register left and clear LSB (Arithmetic 9iift). 


p^7 ► o| Hc| 

[reg] 
Shift contents of register right and preserve MSB (Arithmetic Shift). 



ADAM OSBORNE & ASSOCIATES, INCORPORATED 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 











STATUS 




TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 




OPERATION PERFORMED 


C 


Z 


S 


P/0 


Ac 


N 


111 


SRL 




2 


X 


X 


X 


p 










0-^7 ► Oj ►fc] 


[regl 


5 




















Shift contents of register right and clear MSB (logical Shift). 


O 
Q _ 

5 » 


RLD 




2 




X 


X 


p 












1 ^1 


1' 


3 01 |7 4|3 0| 




< 3 




















[A] ^ ^ [[HL]] 


II 




















Rotate one BCD digit left between the Accumulator and memory location (implied addressing). 


0) u 




















Contents of the upper half of the Accumulator are not affected. 


1- 
« 

a 

Ul 

E 


RRD 


reg 


2 




X 


X 


p 








1 ^1 1 ^1 


17 4|3 01 |7 4|3 0| 






















[Al ^ ([HLll 






















Rotate one BCD digit right between the Accumulator and memory location (implied addressing). 






















Contents of the upper half of the Accumulator are not affected. 




BIT 


b.reg 


2 




X 


? 


7 


1 





Z-reg{b) 

Zero flag contains complement of the selected register bit. 


Z 

o 


BIT 


b,{HL) 


2 




X 


7 


7 


1 





Z— [[HL]](b) or Z— Hwl + clisp](b) 




b,(xy + disp) 


4 














Zero flag contains complement of selected bit of the memory location (implied addressing or 


1- 
< 




















base relative addressing). 


-1 

3 


SET 


b.reg 


2 














reg(b)-1 


Z 
< 




















Set indicated register bit. 


SET 


b,(HU 


2 














[[HL]](b)-l or nxy] + disp](b)-1 


S 




b,(xy + disp) 


4 














Set Indicated bit of memory location (implied addressing or base relative addressing). 


s 


RES 
RES 


b.reg 

b,(HU 
b,(xy + disp) 


2 

2 

4 














reg(b)— 

Reset indicated register bit. 
[[HL]](b)-Oor [Lxyl + dispKb)— 

Reset indicated bit in memory location (implied addressing or base relative addressing). 




PUSH 


pr 
xy 


1 
2 














[[SP]-1]-[pr(HI)] 
[tSP]-2]-[priL0)] 
[SP]-[SP]-2 
Put contents of register pair or Index register on top of Stack and decrement Stack Pointer. 


^ 


POP 


pr 


1 














[prtLO)]-[[SP]] 


< 




xy 


2 














tpr<HI)l-([SP] + 1] 


fe 


EX 


(SP),HL 
(SP).xy 


1 
2 














[SP]-[SP] + 2 

Put contents of top of Stack in register pair or Index register and increment Stack Pointer. 
[H]-[[SP]+1l 
[L]-[[SP]] 

Exchange contents of HL or Index register '^nd top of Stack. 



Table 7-2. A Summary of the Z80 Instruction Set (Continued) 



TYPE 


MNEMONIC 


OPERAND(S) 


BYTES 


STATUS 


OPERATION PERFORMED 


C 


z 


s 


P/0 


Ac 


N 


t- 
a. 

3 

cc 
oc 

lU 

Z 


01 

El 

RST 

RETI 

RETN 

IM 


n 


1 
2 


1 
1 
1 

2 
2 
2 














Disable interrupts. 
Enable interrupts. 
[[SP]-1]-[PaHI)] 
[[SP]-2]— [PC(LO)] 
[SP]-[SP]-2 
[PC]-(8.n)ie 

Restart at designated location. 
Return from interrupt. 
Return from nonmaskable interrupt. 
Set inten-upt mode 0, 1, or 2. 


CO 

< 


SCF 
CCF 




1 
1 


1 
X 










? 






C — 1 

Set Carry flag. 
C'-C 

Complement Carry flag. 




NOP 
HALT 




1 
1 










■ 




No operation — volatile memories are refreshed. 

CPU halts, executes NOPs to refresh volatile memories. 



Table 7-3. A Summary of Instruction Object Codes and Execution Cycles with 8080A Mnemonics 

for Identical Instructions 



o 

CQ 
W 
O 

< 

a 

< 



INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK 
PERIODS 


8080A 
MNEMONIC 


8080A 
CLOCK 
PERIODS 


ADC data 


CE w 


2 


7 


AC! data 


7 


ADC (HL) 


8E 


1 


7 


ADC M 


7 


ADC HL,rp 


ED OlxxlOlO 


2 


15 






ADC (IX-t-disp) 


DD 8E w 


3 


19 






ADC (lY + disp) 


FD 8E yy 


3 


19 






ADC reg 


10001XXX 


1 


4 


ADC reg 


4 


ADD data 


C6 yy 


2 


7 


ADI data 


7 


ADD (HL) 


86 


1 


7 


ADD M 


7 


ADD HLrp 


OOxxlOOl 


1 


11 


DAD rp 


10 


ADD (IX-fdisp) 


DD 86 yy 


3 


19 






ADD IX.pp 


DD OOxxlOOl 


2 


15 






ADD (lY + disp) 


FD 86 yy 


3 


19 






ADD IY,rr 


FD OOxxlOOl 


2 


15 






ADD reg 


10000XXX 


1 


4 


ADD reg 


4 


AND data 


E6 yy 


2 


7 


ANI data 


7 


AND (HL) 


A6 


1 


7 


ANA M 


7 


AND (IX-fdisp) 


DD A6 yy 


3 


19 






AND (lY + disp) 


FD A6 yy 


3 


19 






AND reg 


10100XXX 


\ 


4 


ANA reg 


4 


Brr b,(HL) 


CB 
OlbbbllO 


2 


12 






Brr b,(IX + displ 


DD CB yy 
OlbbbllO 


4 


20 






BIT b.(IY + disp) 


FD CB yy 
OlbbbllO 


4 


20 






BIT b.reg 


CB 
bibbbxxx 


2 


8 






CALL label 


CD ppqq 


3 


17 


CALL label 


17 


CAI 1 Clabel 


DC ppqq 


3 


10/17 


CC label 


11/17 


CALL M.label 


FC ppqq 


3 


10/17 


CM label 


11/17 


CALL NC.Iabel 


D4 ppqq 


3 


10/17 


CNC label 


11/17 


CALL NZJabel 


C4 ppqq 


3 


10/17 


CNZ label 


11/17 


CAlL P.label 


F4 ppqq 


3 


10/17 


CP label 


11/,17 


CALL PEJabel 


EC ppqq 


3 


10/17 


CPE label 


11/17 


CALL PO.Iabel 


E4 ppqq 


3 


10/17 


CPO label 


11/17 


CALL ZJabei 


CC ppqq 


3 


10/17 


CZ , label 


11/17 


CCF 


3F 


1 


4 


CMC 


4 


CP data 


FE yy 


2 


7 


CPI data 


7 


CP (HL) 


BE 


1 


7 


CMP M 


7 


CP (IX-t-disp) 


DD BE yy 


3 


19 






CP (lY-fdisp) 


FD BE yy 


3 


19 


CMP reg 


19 


CP reg 


1011 Ixxx 


1 


4 






CPD 


ED A9 


2 


16 






CPDR 


ED B9 


2 


21/16» 




• 


CPI 


ED A1 


2 


16 






CPIR 


ED 81 


2 


21/16* 




* 


CPL 


2F 


1 


4 


CMA 


4 


DAA 


27 


1 


4 


DAA 


4 


DEC (HL) 


35 


1 


11 


DCR M 


10 


DEC IX 


DD 28 


2 


10 






DEC (IX-t-disp) 


DD 35 yy 


3 


?3 






DEC lY 


FD 2B 


2 


10 






DEC (lY + disp) 


FD 35 yy 


3 


23 






DEC rp 


OOxxlOII 




6 


DCX rp 


5 


DEC reg 


OOxxxlOI 




4 


DCR reg 


S 


Dl 


F3 




4 


Dl 


4 


DJNZ disp 


10 yy 


2 


8/13 






El 


FB 




4 


El 


4 


EX AF.AF 


08 




4, 






EX DE,HL 


EB 




4 


XCHG 


4 


EX (SP),HL 


E3 




19 


XTHL 


18 


EX (SP).IX 


DD E3 


2 


23 







7-33 



Table 7-3. A Summary of Instruction Object Codes and Execution Cycles with 8080A Mnemonics 
for Identical Instructions (Continued) 



INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK 
PERIODS 


8080A 
MNEMONIC 


8080A 
CLOCK 
PERIODS 


EX (SP).IY 


FD E3 


2 


23 






EXX 


09 


1 


4 






HALT 


76 


1 


4 


HLT 


4 


IM 


ED 46 


2 


8 






IM 1 


ED 56 


2 


8 






IM 2 


ED 5E 


2 


8 






IN A.port 


DByy 


2 


10 


IN port 


10 


IN reg,(C) 


ED 
OldddOOO 


2 


11 






INC (HL) 


34 


1 


11 


INR M 


10 


INC IX 


OD 23 


2 


10 






INC (IX-t-dIsp) 


DO 34 yy 


3 


23 






INC lY 


TO 23 


2 


10 






INC (lY + disp) 


FD 34 VY 


3 


23 






INC rp 


OOxxOOII 


1 


6 


INX rp 


5 


INC reg 


(X)xxx100 


1 


4 


INR reg 


5 


IND 


ED AA 


2 


15 




* 


INOR 


ED BA 


2 


20/15 






INI 


ED A2 


2 


15 






INIR 


ED 82 


2 


20/15 






JP label 


C3 ppqq 


3 


10 


JMP label 


10 


JP Clabel 


DA ppqq 


3 


10 


JC label 


10 


JP (HU 


E9 


1 


4 


PCHL 


5 


JP (IX) 


DO E9 


2 


8 






JP (lY) 


FD E9 


2 


8 






JP M,label 


FA ppqq 


3 


10 


JM label 


10 


JP NCIabel 


02 ppqq 


3 


10 


JNC label 


10 


JP NZ.Iabel 


C2 ppqq 


3 


10 


JNZ label 


10 


JP P.label 


F2 ppqq 


3 


10 


JP label 


10 


JP PE,label 


EA ppqq 


3 


10 


JPE label 


10 


JP PO.Iabel 


E2 ppqq 


3 


10 


JPO label 


10 


JP Z,label 


CA ppqq 


3 


10 


JZ label 


10 


JR Cdisp 


38 yy 


2 


7/12 






JR disp 


18 yy 


2 


12 






JR NCdisp 


30 yy 


2 


V12 






JR NZ.disp 


20 yy 


2 


7/12 






JR Z.disp 


28 yy 


2 


7/12 






LO A,(ad<ir) 


3A ppqq 


3 


13 


LDA addr 


13 


LD A.(BC) 


OA 


1 


7 


LDAX B 


7 


LD A,(DE) 


1A 


1 


7 


LDAX 


7 


ID A,l 


ED 57 


. 2 


9 






LD A.R 


ED 5F 


2 


9 






LO (addrXA 


32 ppqq 


3 


13 


STA addr 


13 


LD (addr).BC 


ED 43 ppqq 


4 


20 






LO (addr).OE 


ED 53 ppqq 


4 


20 






LD (addr),HL 


22 ppqq 


3 


16 


SHLD addr 


16 


LD (addr),IX 


DD 22 ppqq 


4 


20 






LD (adddlY 


FD 22 ppqq 


4 


20 






LD (addr),SP 


ED 73 ppqq 


4 


20 






LD (BC),A 


02 


1 


7 


STAX B 


7 


LD (DE),A 


12 


1 


7 


STAX D 


7 


LD HL,(addr) 


2A ppqq 


3 


16 


LHLD addr 


16 


LD (HD.data 


36 yy 


2 


10 


MVI M,data 


10 


LD (HL),reg 


oinosss 


1 


7 


MOV M,reg 


7 


LD l,A 


ED 47 


2 


9 






LD IX,(addr) 


DD 2A ppqq 


4 


20 






LD IX.dataie 


DD 21 yyyy 


4 


14 






LD (IX + disp).data 


DD 36 yy yy 


4 


19 






LD (IX + disp),reg 


DD OinOsss 
YV 


3 


19, 






LD IY,(addr) 


FD 2A ppqq 


4 


20 






LD IY,data16 


FD 21 yyyy 


4 


14 







7-34 



Table 7-3. A Summary of Instruction Object Codes and Exedlition Cycles with 8080A Mnemonics 
for Identical instructions (Continued) 



INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK 
PERIODS 


8080A 
MNEMONIC 


8080A 
CLOCK 
PERIODS 


LD (lY -t- disp),data 


FD 38 WW 


4 


19 






LO (IY-t-di»p).reg 


FD OinOsss 

yy 


3 


19 






LD R,A 


ED 4F 


2 


9 






LD reg.data 


OOdddllO 

yy 


2 


7 


MVI reg.data 


7 


LD refl,(HU 


OldddllO 


1 


7 


MOV reg.M 


7 


LD reg,(IX + di$p) 


DD 
OldddllO 

yy 


3 


19 






LD reg,(IY + disp) 


FD 
OlddddllO 

yy 


3 


19 






LD reg.reg 


Oldddsss 


1 


4 


MOV rog,reg 


5 


LO rp,(addr) 


ED OlxxlOII 
ppqq 


4 


20 






LD rp,data16 


OOxxOOOl 

yyyy 


3 


'0 


LXI rp.dataie 


10 


LD SP.HL 


F9 


1 


6 


SPHL 


5 


Id SP,IX 


DD F9 


2 


10 






LD SP.IY 


FD F9 


2 


10 






LDO 


ED AS 


2 


16 






LDDR 


ED B8 


•2 


21/16* 




• 


LDI, 


ED AO 


2 


16 






LDIR 


ED B9 


■J 


21/16* 




* 


nIg 


ED 44 


2 


8 






NOP 


00 


1 


4 


NOP 


4 


OR data 


F6w 


2 


7 


ORI data 


7 


OR (HL) 


B6 


1 


7 


ORA M 


7 


OR (iX + disjl) 


DD B6 w 


3 


19 






OR (lY + disp) 


FD 86 w 


3 


19 






OR reg 


lOlibxxx 


1 


4 


ORA reg 


5 


OTDR 


ED SB 


2 


20/15* 




• 


OTIR 


ED B3 


2 


20/15* 




• 


OUT (CUeg 


ED OlsssOOl 


2 


12 






OUT port,A 


D3w. 


2 


11 


OUT port 


10 


OUTD 


ED AB 


2 


15 






OUT! 


ED A3 


2 


,15 






POP IX 
i>OP lY 


DO El 
FD El 


2 
2 


14 
.14 






POP pr 


llxxOOdI 


1 


10 


POP rp 


10 


PUSH IX 


DDES 


2 


15 






PUSH lY 


FD E5 


2 


15 






PUSH pr 


llxxOIOI 


1 


11 


PUSH rp 


11 


RES b,(HU 


CB 
lObbbllO 


2 


15 






RES b,(IX + disp) 


PDCB w 
1()bbblii} 


4 


23 






RES b,(IY + disp) 


FD CB w 
lObbbllO 


4 


23 






RES b.reg 


CB 
lObbbxxx 


2 


8 






RET 


C9 


1 


10 


RET 


10 


RET C 


D8 


1 


5/11 


RC 


5/11 


RET M 


Fd 


1 


5/11 


RM 


5/11 


RET NC ; 


DO 


1 


5/11 


RNC 


5/11 


RET NZ 


CO 


1 


5/11 


RNZ 


5/11 


RET P 


FO 


1 


5/11 


RP 


5/11 


RET PE 


E8 


1 


5/11 


RPE 


5/11 


RET PO 


EO 


1 


5/11 


RPO 


5/11 


RET Z 


C8 


1 


5/11 


RZ 


5/11 


RETI 


ED 4D 


2 


14 







7-35 



Table 7-3. A Summary of Instruction Object Codes and Execution Cycles with 8080A Mnemonics 
* , ■ for Identical Instructions (Continued) 



INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK 
PERIODS 


S080A 
MNEMONIC 


8080A 
CLOCK 
PERIODS 


REIN 


ED 45 


2 


14 






RL (HL) 


C^ 16 


2 


15 






RL (IX + disp) 


DD CB yy 16 


4 


23 






RL (lY + disp) 


FD CB yv 16 


4 


23 






RL reg 


CB 
OOOIOxxx 


2 


8 






RLA 


17 


1 


4 


RAL 


4 


RLC (HL) 


CB 06 


2 


15 






RLC (IX + disp) 


DD CB yy 06 


4 


23 






RLC (lY + disp) 


FD CB yy 06 


4 


23 






RLC reg 


CB 
OOOOOxxx 


2 


8 






RLCA 


07 


1 


4 


RLC 


4 


RLD 


ED 6F 


2 


18 






RR (HL) 


CB IE 


2 


15 






RR (IX + disp) 


DD CB.yy IE 


4 


23 






RR (lY + disp) 


FD CB yy IE 


4 


23 






RR reg 


CB 
0001 Ixxx 


2 


8 






RRA 


IF 


1 


4 


RAR 


4 


RRC (HL) 


CB OE 


2 


15 






RRC (IX + disp) 


DD CB yy OE 


4 


23 






RRC (lY + disp) 


FD CB yy OE 


4 


23 






RRC reg 


CB 
OOOOIxxx 


i 


8 






RRCA 


OF , 


1 


4 


RRC 


4 


RRD 


ED 67 


2 


18 






RST n 


llxxxlll 


1 


11 


RST n 


11 


SBC data 


DEyy 


2 


7 


SBI data 


7 


SBC (HL) 


9E 


1 


7 


SBB m 


7 


SBC HL,rp 


ED OlxxOOlO 


i 


15 






SBC (IX + disp) 


DD 9E yy 


3 


19 






SBC (lY + disp) 


FD 9E yy 


3 


19 






SBC reg 


1001 Ixxx 


1 


4 


SBB reg 


4 


SCF 


37 


1 


4 


STC 


4 


SET b,(HL) 


CB 
llbbbllb 


2 


15 






SET b,(IX + disp) 


DD CB yy 
llbbbllO 


4 


23 






SET b,(IY + disp) 


FD CB yy 
llbbbllO 


4 


23 






SET b.reg 


CB 
llbbbxkx 


2 


8 






SLA (HL) 


CB 26 


2 


15 






SLA (IX + disp) 


DD CB yy 26 


4 


23 






SLA (lY + disp) 


FD CB yy 26 


4 


23 






SLA reg 


CB OOlOOxxx 


2 


8 






SRA (HL) 


CB 2E 


2 


15 






SRA (IX + disp) 


DD CB yy 2E 


4 


23 






SRA (lY + disp) 


FD CB yy 2E 


4 


23 






SRA reg 


CB OOlOlxxx 


2 


8 






SRL (HL) 


CB 3E 


2 


15 






SRL (IX + disp) 


DD CB yy 3E 


4 


23 






SRL (lY + disp) 


FD CB yy 3E 


4 


23 






SRL reg 


CB 0011 Ixxx 


2 


8 






SUB data 


D6 yy 


2 


7 


SUI data 


7 


SUB (HL) 


96 


1 


7 


SUB IVl 


7 


SUB (IX + disp) 


DD 96 yy 


3 


19 






SUB (lY + disp) 


FD 96 yy 


3 


19 






SUB reg 


10010XXX 


1 


4 


SUB reg 


'4 


XOR data 


EE yy 


2 


7 


XRI data 


7- 


XOR (HL) 


AE 


1 


7 


XRA IVl 


7 



7-36 



Table 7-3. A Summary of Instruction Object Codes and Execution Cycles with 8080A Mnemonics 
for Identical Instructions (Continued) 



INSTRUCTION 


OBJECT CODE 


BYTES 


CLOCK 
PERIODS 


8080A 
MNEMONIC 


8080A 
CLOCK 
PERIODS 


XOR (IX + disp) 


DD AE yy 


3 


19 






XOR (lY + disp) 


FD AE yy 


3 


19 






XOR reg 


lOIOIxxx 


1 


4 


XRA reg 


4 


X represents an optional binary digit. 




bbb represents optional binary digits identifying a bit location in a register 


or memory byte. 


ddd represents optional binary digits identifying a destination register. 




sss represents optional binary digits identifying a source register. 




ppqq represents a four hexadecimal digit memory address. 




yy represents two hexadecimal data digits. 




yyyy represents four hexadecimal data digits. 




When two possible execution times are shown (i.e., 5/11), it indicates that 




the number of clock periods depends on condition flags. 




'Execution time shown is for one iteration. 





< 

Q 
< 



7-37 



THE Z80 INSTRUCTION SET 

We are going to describe the Z80 instruction set as an 8080A enhancement. Table 7-2 summarizes the ZBO in- 
struction set in the standard format used for all microcomputers in this book; unfortunately, the fact that the 
8080A instruction set is a subset of Table 7-2 is not immediately obvious, since a number of significant concep- 
tual differences exist between the Zilog and 8080A assembly language mnemonics. Table 7-3 therefore shows 
Z80 equivalents for every 8080A instruction. The few incompatibilities which exist are identified. 

Also because of Z80 innemonics, the Zilog instruction set is not easily forced into the standard instruction 
categories that we have selected for consistency. In particular, Z80 mnemonics group Memory Reference, 
Register-Register Move and Immediate instruction into a single "Load and Exchange" category. The same holds 
true for Z80 Arithmetic and Logical instructions; in Table 7-2 these become Secondary Memory Reference, 
Register-Register Operate and Immediate Operate instructions. 

INPUT/OUTPUT INSTRUCTIONS 

these are the types of input/output instructions provided by the Z80: 

1) The standard 8080A IN and OUT instructions, whereby the second byte of instruction object code provides an 
I/O port address, which appears on Address Bus lines AO - A7. 

2) Register indirect Input and Output instructions. These instructions transfer data between Register A, B, C, D, E, 
H or L, and the I/O port identified by the contents of Register C. Thus the instruction: 

LD C.PORTN ;LOAD PORT NUMBER INTO REGISTER C 



IN D.(C) ;INPUT DATA FROM PORTN TO REGISTER D 

is equivalent to: 

IN A.(PORTN) 

LD D,A 

The I/O port address, now the contents of Register C, is output on AO - A7 in the usual way. 

3) Block Transfer I/O instructions. These instructions move a block of data between the I/O port identified by 
Register C and a memory location addressed by the H and L register pair. Register B is used as a block byte counter. 
After each byte of data within the block is transferred, the contents of Register B are decremented; you can specify 
block transfer I/O instructions that will eithfer increment or decrement the memory address in Registers H and L. 
Here is a programming eJtample with the 8080A equivalent: 





ZBO 






8080A 


LD 


B.COUNT 




MVI 


B,COUNT 


LD 


C.PORTN 




LXI 


H.START 


LD 


HL.START 


LOOP: 


IN 


PORTN 


INIR 






MOV 
INX 
DCR 
JNZ 


M.A 
H 
B 
LOOP 



These instruction sequences input COUNT bytes from I/O port PORTN, and store the data in a memory buffer 
whose beginning address is START. COUNT and PORTN are symbols representing 8-bit numbers. START is an ad- 
dress label. The block transfer I/O instruction will continue executing until the B register has decremented to 0. 

4) Single Step Block Transfer I/O instructions. These are identical to the block transfer I/O instructions described in 
category 3 above, except that instruction execution ceases after one iterative step. Referring to the INIR instruction 
example, if the INIR instruction were replaced by an INI instruction, a single byte of data would be transferred from 
PORTN to the memory location addressed by START. The address START would be incremented. Register B con- 
tents would be decremented, then instruction execution would cease. 

When a block transfer or single step, block transfer I/O instruction is executed, C register contents, which identify the 
I/O port, are output on the lower eight Address Bus lines in the usual way; however, B register contents are output on 
the higher eight address lines A1 5 - A8. Therefore external logic can, if it wishes, determine the extent of the transfer. 

Let us now look at the advantages gained by having the new Z80 I/O instructions. 

The value of the Register Indirect I/O instructions is that programs stored in ROM can access any I/O port. If I/O 

port assignments change, then all you need to do is modify that small portion of program which loads the I/O port ad- 
dress into the C register. 

7-38 



z 
c 
o 
m 
u> 
o 

< 

Q 
< 

@ 



The Block Transfer I/O instructions must be approached with an element of caution. In response to the execution 
of a single instruction's object code, up to 256 bytes of data may be transferred between memoryand an I/O port. This 
data transfer occurs at CPU speed — which means external logic must input. or output data at the same speed. If exter- 
nal logic cannot operate fast enough, it can insert Wait states in order to slow the CPU, but that takes additional logic; 
and one might argue that the traditional methods of polling on status to effect block I/O transfers is cheaper than 
adding extra Wait state logic. 

Note that all Z80 enhanced I/O instructions require two bytes of object code. 

PRIMARY MEMORY REFERENCE INSTRUCTIONS 

Instructions that we classify as Primary Memory Reference constitute a subset of the Load instructions, as classifed by 
Zilog. Within the Primary Memory Reference instructions category, as we define it, Zilog offers a single enhan- 
cement: base relative addressing. Instructions that move data between a register and memory may specify the 
memory address as the contents of an Index register; plus an 8-bit displacement provided by the instruction object 
code. Here is a programming example of Zilog base relative addressing and the BOBOA equivalent: 
ZBO BOBOA 

LD IX,BASE LXI H,BASE 

LD C.dX + DISP) LXI D,DISP 

DAD D 

MOV CM 

Observe that the two ZBO instructions do not use any CPU registers — other than the IX Index register. The BOBOA uses 
the DE and HL registers. Here is an example of the true value that results from having Index registers. The ZBO can use 
the DE and HL registers to store temporary data, which the BOBOA cannot do; the BOBOA would have to store such tem- 
porary data in external read/write memory. 

The biggest single advantage that accrues to the ZBO from having indexed addressing is the fact that well written ZBO 
programs will contain far fewer memory reference instructions than equivalent BOBOA programs; therefore ZBO pro- 
grams will execute faster. 

Other primary memory reference instructions provided by the ZBO, and not present in the BOBOA, include instructions 
which load data into the Index registers and store Index registers' contents in memory. Since the BOBOA does not have 
Index registers, it cannot have memory reference instructions for them. The ZBO also has instructions which transfer 
16-bit data between directly addressed memory and any register pair, except AF. Recall that in the BOBOA, HL is the 
only register pair which stores to memory and loads from memory using direct addressing. 

BLOCK TRANSFER AND SEARCH INSTRUCTIONS 

We classify the Zilog Block Transfer and Search instructions in a separate category, since our hypothetical com- 
puter, as described in Volume I, had no equivalent instructions. 

A Block Transfer instruction allows you to move up to 65,536 bytes of data between two memory buffers 
which may be anywhere in memory. The H and L registers address the source buffer, the D and E registers address 
the destination buffer, and the B and C registers hold the byte count. 

After every byte of data is transferred, the B and C registers' contents are decremented; instruction execution ceases 
after the B and C registers decrement to zero. You have the option of incrementing or decrementing the source and 
destination addresses following the transfer of each data byte. Thus you can transfer data from low to high memory, or 
from high to low memory. Here is a programming example of the ZBO Block Move instruction, along with the BOBOA 
equivalent: 





ZBO 


BOBOA 




LD 


BCCOUNT 


LXI 


B,COUNT 


LD 


DE,DEST 


LXI 


D,DEST 


LD 


HLSRCE 


LXI 


H,SRCE 


LDIR 


LOOP: 


MOV 


A,M 






STAX 


D 






INX 


H 






INX 


D 






DCX 


B 






MOV 


A,B 






ORA 


C 






JNZ 


LOOP 



The two instruction sequences illustrated. above move a block of data, COUNT bytes long, from a buffer whose starting 
address is SRCE to another buffer whose starting address is DEBT. SRCE and DEST are 1 6-bit address labels. COUNT is 
a symbol representing a 16-bit data value. 



7-39 



The Z80 - 8080A comparison above is one that makes the 8080A look particularly bad. This is because it emphasizes 
8080A weaknesses; the 8080A requires memory addresses to be incremented as separate steps. Also, after decrement- 
ing the counter in Registers B and C, status is not set, therefore BC contents are tested by loading B into A and ORing 
with C. 

You can use Block Move instructions in Z80 configurations that include dynamic memory. While the Block Move 
is being executed, dynamic memory is refreshed. 

The Block Search instruction will search a block of data in memory, looking for a match with the Accuniulator 
contents. The H and L registers address memory, while the B and C registers again act as a byte counter. When a 
match between Accumulator contents and a memory location is found, the Search instruction ceasds executing. After 
every Compare, the B and C registers' contents are decremented; once again you have the option of either increment- 
ing or decrementing H and L registers' contents. Thus you can search a block of memory from high address down, or 
from low address up. 

The results of every step in a Block Search are reported in the Z and P/0 statuses. If a match is found between Ac- 
cumulator and memory contents, then Z is set to 1 ; otherwise Z will equal 0. When the B and C registers count out to 
zero, the P/0 status will be reset to 0; otherwise the P/0 status will equal 1. 

Here is an example of a program using the Z80 Block Search instruction, along with 8080A program equivalent: 
Z80 8080A 



LD A.REFC 


LXI 


BCCOUNT 


LD BCCOUNT 


LXI 


HLSRCE 


LD HL.SRCE LOOP: 


MVI 


A,REFC 


CPDR 


CMP 


M 


JR Z,FOUND 


JZ 


FOUND 


;N0 MATCH FOUND 


, DCX 


H 


- 


DCX 


B 


- 


MOV 


A,B 


;MATCH FOUND 


ORA 


C 


FOUND: 


JNZ 


LOOP 



;N0 MATCH FOUND 



;MATCH FOUND 
FOUND: - 



Each of the above instructi6n sequences tries to match a character represented by the symbol REFC with the contents 
of bytes in a memory buffer. The nhemory buffer is origined at SRCE and is COUNT bytes long. 

In the example illustrated above, SRCE is the highest memory address for the buffer, which is searched towards the low 
memory address. FOUND is the label for the first instruction in the sequence which is executed if a match is found. If no 
match is found, that is, the BC registers count out to 0, program execution continues with the next sequential instruc- 
tion. ■ 

The Z80 Block Search instruction is particularly useful when searching a large memory buffer for a byte that 
may frequently occur. Suppose you have an ASCII text in which Control codes have been imbedded. For the sake of 
argument, let us assume that all Control codes are two bytes long, where the first byte has the hexadecimal value 02 
and the second byte identifies the Control code. You can use one set of registers in order to search the text buffer for 
Control codes, while using the second set of registers to process the text buffer after each Control code has been lo- 
cated. 

All you need to do in the Block Search instruction sequence illustrated above is follow the CPDR instruction with an 
EXX instruction; after executing the instruction sequence following MATCH FOUND, again execute an EXX instruction 
before returning to search for the next Control code. 

Each of the Block Move and Block Search instructions has a single step equivalent, the single step instruction 
moves one byte of data, or compares the Accumulator contents with the next byte in a data buffer; addresses and 
counters are incremented and decremented as for the Block Move and Search instructions, however execution ceases 
after a single step has been completed. 



7-40 



SECONDARY MEMORY REFERENCE (MEMORY OPERATE) INSTRUCTIONS 

Instructions that we classify as Secondary Memory Reference, or Memory Operate, constitute a portion of the 
arithmetic and logical instructions, as defined by the Z80. Within the Memory Operate group of instructions, the 
single enhancement offered by the Z80 is a duplicate set of instructions that uses base relative addressing. We 

have already discussed this enhancement in connection with Primary Memory Reference instructions. Here is a pro- 
gramming example with the 8080A equivalent: 





ZBO 




8080A 


LD 


IX,BASE 


LXI 


H,BASE 


ADD 


(IX + DISP) 


LXI 


D.DISP 






DAD 


D 






ADD 


M 



m The same comments we made regarding the use of indexed addressing in the Primary Memory Reference example ap- 

< ply to the instruction sequences above. 

§ IMMEDIATE INSTRUCTIONS 

C/) 

< Within the group of instructions that we classify as Immediate, the Z80 offers two enhancements: 

oil 

uj 1) Instructions are provided to load immediate data into the additional Z80 registers. 

z 

Q 2) You can use base relative addressing to load a byte of data immediately into read/write memory. 

I JUMP INSTRUCTIONS 

^ In addition to the standard Jump instruction offered by the 8080A, the Z80 has a two-byte, unconditional 

o Branch instruction, and two instructions which allow you to jump to the memory location specified by an Index 



register. 

The two indexed Jump instructions ^ransfer the contents of the identified Index register to the Program Counter. 

The two-byte Jump instruction interprets the second object code byte as an 8-bit signed binary number, which is ad- 
ded to the Program Counter, after the Program Counter has been incremented to point to the next instruction. This is a 
standard program relative branch, as described in Volume I. 

Note that the Z80 uses many of the spare 8080A object codes to implement the two-byte Branch and Branch-on-Con- 
dition instructions. This makes sense; it would certainly not make much sense to have two bytes of object code 
followed by a single branch byte, since that would create a three-byte Branch instruction — offering no advantage over 
the three-byte Jump instructions which already exist. 

SUBROUTINE CALL AND RETURN INSTRUCTIONS 

The Z80 instructions in this group are identical to 8080A equivalents. 

IMMEDIATE OPERATE INSTRUCTIONS 

Z80 Immediate Operate instructions, as we define them, are identical to those in the 8080A instruction set. 

JUMP-ON-CONDITION INSTRUCTION 

The Z80 offers two significant Jump-on-Condition instruction enhancements over the 8080A: 

1) There are two-byte equivalents for four of the more commonly used Jump-on-Condition instructions. The 

two-byte Jump-on-Condition instructions execute exactly as described for the two-byte Jump instruction. 

2) There is a decrement and Jump-on-Nonzero instruction which is particularly useful in any kind of iterative loop. 
When this instruction is executed, the B register contents are decremented; if the B register contents, after being 
decremented, equal zero, the next sequential instruction is executed. If after being decremented the B register con- 
tents are not zero, then a Jump occurs. This is a two-byte instruction, where the Jump is specified by a single 8-bit 
signed binary value. 



7-41 



Here is an example of how the DJNZ instruction may be used along with the 8080A equivalent 



LOOP: 





Z80 


8080A 




AND 


A 


•■ANA 


A 


LD 


IX,VALA 


LXI 


D.VALA 


LD 


IY,VALB 


LXI 


H.VALB 


LD 


B.CNT 


MVI 


B.CNT 


LD 


A.(IX) LOOP: LDAX 


D 


ADC 


A.(IY) 


ADC 


M 


LD 


(IX),A 


STAX 


D 


INC 


IX 


INX 


D 


INC 


lY 


INX 


H 


DJNZ 


LOOP 


DCR 


B 






JNZ 


LOOP 



The two instruction sequences illustrated above perform simple multibyte binary addition. The contents of two buffers, 
origined at VALA and VALB, are summed: the results are stored in buffer VALA^ 

The first instruction in each sequence is executed in order to clear the Carry status. Like the 8080A, the Z80 does not 
have an instruction which sets the Carry status to 0, while performing no other operation. 

REGISTER-REGISTER MOVE INSTRUCTIONS 

Register-Register Move instructions, as we defined them in this book, constitute a subset of the Z80 Load instructions. 
All Z80 Exchange instructions, except those that exchange with the top of the Stack, are also classified as Register- 
Register Move instructions. 

The Z80 enhancements within this instruction group apply strictly to the additional registers implemented 
within the Z80. That is to say, because the Z80 has registers which the 8080A does not have, the Z80 must also have 
instructions to move data in and out of these additional registers. 

The instructions which exchange data between registers and their alternates need comment. Note that you can swap 
the entire set of duplicated registers, or you can swap selected register pairs. If you use these instructions following an 
interrupt acknowledge, you do not have to save the contents of the registers on the Stack. Of course, this will only work 
for a single interrupt level. There are also occasions when the alternate set of registers can be used effectively in normal 
programming logic, as we illustrated when describing the Block Search instruction. 

REGISTER-REGISTER OPERATE INSTRUCTIONS 

There are a few new Z80 Register-Register Operate instructions which do the following: 

1) Add without Carry the contents of a register pair to an Index register. 

2) Add with Carry to HL the contents of a register pair. 

3) Subtract with Carry from HL the contents of a register pair. 

REGISTER OPERATE INSTRUCTIONS 

Within this category, the Z80 has two enhancements: 

1) You can increment or decrement the contents of an Index register. 

2) A rich variety of Shift and Rotate instructions have been added. These instructions are illustrated in Table 7-2. In 
particular, note the RLD and RRD instructions, which are very useful when performing multidigit BCD left and right 
shifts. 

BIT MANIPULATION INSTRUCTIONS 

The 8080A has no equivalent for this set of Z80 instructions. We give these instructions a separate category in Ta- 
ble 7-2 because of their extreme importance in microprocessor applications. 

Bit manipulation instructions are particularly important for signal processing. A single signal is a binary entity; it is not 
part of an 8-bit unit. One of the great oversights among microprocessor designers has been to ignore bit manipulation 
instructions. The Z80 has instructions that set to 1 (SET), reset to (RES) or test (BIT) individual bits in memory 
or any general purpose register. The result of a bit test is reported in the Zero status. 



7-42 



Here are some Z80 instructions with 8080A equivalents: 

Z80 8080A 

BIT 4.A MOV B.A 

ANI 10H 

MOV A,B 

ui The 8080A tests Accumulator bits destructively — all untested bits are cleared; Accumulator contents must therefore 

< be saved before testing. We can also contrive an example to emphasize the strengths of the Z80 bit instructions: 

o 
a. 
cc 
o 
u 
z 





-Z80 




8080A 


LD 


lY.BASE 


LXI 


KBASE 


SET 


2,(IY + DISP) 


LXI 


D.DISP 






DAD 


D 






MVI 


A,4 






ORA 


M 



5 Once again, note that the 8080A needs to use the D, E, H and L registers. 

(/} 

< Note that all Z80 Bit instructions operate on memory or CPU registers. But in most microcomputer applications in- 

'^ dividual pins at I/O ports will most frequently be set, reset or tested. The Z80 has no I/O Bit instructions. If you wish, 

z you can interface I/O devices so that they are addressed as memory locations; however, in that case, you cannot use 

o Block I/O instructions. 

CO 

g The 8080A can do anything that a Z80 Bit Manipulation instruction can do but an additional Mask instruction is 

5 needed and the Accumulator is involved. On the surface these seem to be small penalties; but it is the frequency with 

< which Bit Manipulation instructions are needed that escalates small penalties into major aggravations. 

^ STACK INSTRUCTIONS 

Additional Stack instructions provided by the Z80 allow the Z80 Index registers to be pushed onto the Stack, 
popped from the Stack, or exchanged with the top of the Stack. 

INTERRUPT INSTRUCTIONS 

In addition to the 8080A Interrupt instructions, the Z80 has two Return-from-lnterrupt instructions. RETI and RETN are 
used to return from maskable and nonmaskable interrupt service routines, respectively. 

RETI and RETN are two-byte instructions. Within the CPU these instructions enable interrupts, but otherwise ex- 
ecute exactly as a Return-from-Subroutine (RET) instruction. However, devices designed by Zilog to support 
the Z80 CPU use the RETI and RETN instructions in a unique way. Any support device that has logic to request an 
interrupt also includes logic which tests the Data Bus contents during the low Ml pulse. Upon detecting the second 
byte of an RETI or RETN instruction's object code, a device which has had an interrupt request acknowledged deter- 
mines that the interrupt has been serviced. 

Why does a support device need to know that an interrupt service routine has completed execution? The reason is that 
Zilog extends interrupt priority arbitration logic beyond the interrupt acknowledge process to the entire interrupt ser- 
vice routine. 

This is the scheme adopted by the 8259 PICU. After reading the next paragraph, if you are still unclear on concepts, 
refer to the 8259 PICU discussion in the 8080A chapter. 

Consider the typical daisy chain scheme used to set interrupt priorities in a multiple interrupt microcomputer system. 
Daisy chaining has been described in good detail in Volume 1. When more than one device is requesting an interrupt, 
an acknowledge ripples down the daisy chain until trapped by the interrupt requesting device electrically closest to the 
CPU. As soon as the interrupt acknowledge process has ceased, an interrupt service routine is executed for the 
acknowledged interrupt; acknowledged external logic will now remove its interrupt request. Unless the CPU disables 
further interrupts, a lower priority device can immediately interrupt the service routine of a higher priority device. With 
the Zilog system, that is not the case. A device which has its interrupt request acknowledged continues to suppress in- 
terrupt requests from all lower priority devices in a daisy chain, until the second object code byte for an RETI or RETN 
instruction is detected on the Data Bus. The acknowledged device responds to an RETI or RETN instruction's object 
code by re-enabling interrupts for devices with lower priority in the daisy chain. 

Providing a Zilog microcomputer system has been designed to make correct use of the RETI and RETN instructions, in- 
terrupt priority arbitration logic will allow an interrupt service routine to be interrupted only by a high priority interrupt 
request. 



7-43 



Here is an illustration of the Zilog interrupt priority arbitration scheme: 



•Active 
. IREQ1 IREQ2 



DEVICE 1 



( 



Lower priority 
interrupts 

suppressed 



•Active 



IREQ3 • IREQ4 



\ \\ — ^ \r^ \\ — ^lr~ * 



DEVICE 2 



DEVICE 3 



DEVICE 4 



Device 2 Interrupt Request 



Main 




Main 
Program 




Program 


y x" 






^r Device 2 interrupt ^^ 








^ service routine ^ 


\ 






Only IREQ1 can be 


^ 


RETI instruction executed 




acknov/ledged v/hile Device 2 




here enables interrupts at 




interrupt service routine is 




Devices 3 and 4. IREQ4 




executing 




can now be acknov^ledged 



The three IM instructions allow you to specify that the CPU will respond to maskable interrupts in Mode 0, 1 or 

2. These three interrupt response modes have already been described. 

STATUS AND MISCELLANEOUS INSTRUCTIONS 

Z80 and 8080A instructions in these categories are identical. 

THE BENCHMARK PROGRAM 

Our benchmark program is coded for the ZOO as follows: 

LD BCLENGTH ;LOAD 10 BUFFER LENGTH INTO BC 

LD DE,(TABLE) :LOAD ADDRESS OF FIRST FREE TABLE BYTE OUT OF FIRST TWO TABLE 

; BYTES 
LD HLIOBUF ;LOAD SOURCE ADDRESS INTO HL 

LDIR ;EXECUTE BLOCK MOVE 

The program above makes absolutely no assumptions. Both source and destination tables may have any length and 
may be located anywhere in memory. 

Notice that there is no instruction execution loop, since the LDIR block move will not stop executing until the entire 
block of data has been moved. 

SUPPORT DEVICES THAT MAY BE USED WITH THE Z80 

The Z80 signal interface is very close to that of the 8080A. When looking at Z80 signals we saw how they may be com- 
bined to generate 8080A equivalents. Thus 8080A support devices may be used with the Z80 CPU. Exceptions 
are the 8259 Priority Interrupt Control Unit and the TMS5501 multifunction device. 

The 8259 Priority Interrupt Control Unit should not be used with the Z80 CPU because the Z80 CPU provides essen- 
tially the same capabilities within the CPU chip itself. So far as signal interface is concerned, you could use an 8259 
with a Z80, but it would make no sense. 



7-44 



The TMS5501 cannot be used with a Z80 because it assumes status on the Data Bus — as output by the 8080A with- 
out an 8228 Systenn Controller. 

The 8085 support devices — the 8155, the 8355 and the 8755 — are difficult to use with the Z80; you have to 
multiplex the low order eight Z80 address lines and the Z80 8-bit Data Bus to sinnulate the 8085 multiplexed bus lines. 
Logic needed to perform this bus multiplexing would likely be more expensive than discrete packages that implement 
individual functions provided by the 8155 and 8355 multifunction devices. 

Using MC6800 support devices with the Z80 is not practical. MC6800 support devices all require a synchronizing 
clock signal whose characteristics cannot be generated simply from the Z80 clock signal. 

With the exception of the Z80 DMA device, Z80 support devices (whic h we are ^out to describe) are not 
general-purpose devices. The Z80 PIO, SIO, and CTC devices decode the Ml , lORQ, and RD control signals to identify 
a number of functions. Table 7-4 defines the manner in which these signals are decoded. Were you to use the Z80 PIO, 
SIO, or CTC with any other microp roces sor, you would have to multiplex the other microprocessor's control signals in 
order to create equivalents of Ml, lORQ, and RD; this may not be straightfonward. 



< 

o3 
lU 

Z 
c 
o 
m 
(n 
O 

< 

< 
@ 



Table 7-4. Z80 PIO Interpretation of Control Signals 



SIGNALS 


FUNCTIONAL INTERPRETATION * 


Ml 


lORQ 


RD 





0- 



1 
1 
1 
1 




1 
1 




1 
1 



1 


1 



1 



1 


No function 

Interrupt acknowledge 

Check for end of interrupt service routine 

Reset 

Read from PIO to CPU 

Write from CPU to PIO 

No function 

No function 



* These interpretations only apply if the device has been selected 

Z80 support devices also rely on exact Z80 CPU characteristics for interrupt processing. Specifically, Z80 support 
devices detect every instruction fetch, as identified by Ml and RD simultaneously low; if a return from interrupt object 
code is fetched, then Z80 support devices respond to this object code by resetting internal interrupt pridrjty logic. Ac- 
counting for this end of interrupt logic in a non-Z80 system could be difficult. 

Because of the unique characteristics of the Z80 support devices, the Z80 PIO and CTC devices are described in 
this chapter. The Z80 DMA device is described in Volume 3, however, because this device is easily used in non-Z80 
configurations; moreover, its unique capabilities make it a highly desirable part to include in any microcomputer 
system that has to move text or data strings. The Z80 SIO device is also described in Volume 3 because it is an ex- 
ceptionally powerful device; in many cases the power of the Z80 SIO device will compensate for the additional logic it 
will demand in a non-Z80 microcomputer system. 

THE Z80 PARALLEL I/O INTERFACE (PIO) 

The Z80 PIO is Zilog's parallel interface device; it may be looked upon as a replacement for the 8255 PPI, biit it 
is equivalent to the PPI at a functional level only. No attempt has been made to make the Z80 PIO an upward 
compatible replacement for the 8255 PPI. 

The Z80 PIO has 16 I/O pins, divided itito two 8-bit I/O ports. Each I/O port has two associated control liries. 
This makes the Z80 PIO more like the Motorola MC6820 than the 8255 PPI. 

The two Z80 PIO I/O ports may be separately specified as input, output or control ports. When specified as a 
control port, pins may be individually assigned to input or output. Port A may be used as a bidirectional I/O port. 

The Z80 PIO also provides, a significant interrupt handling capability. This includes: 

- The ability to define conditions which will initiate an interrupt. 

- Interrupt priority arbitration 

- Vectored response to an interrupt acknowledge 

Figure 7-1 6 illustrates that part of our general microcomputer system logic which has been implemented on the 
Z80 PIO. 



7-45 



The Z80 PIO is packaged as a 40-pin DIP. It uses a single +5V power supply. All inputs and outputs are TTL-level 
compatible. The device is fabricated using N-channel silicon gate depletion load technology. 



Clock Logic 



Logic to Handle 
Interrupt Requests 

, from 
External Devices 



Arithmetic and 
Logic Unit 



Instruction Register 



Control Unit 



Interrupt Priority 
Arbitration 



Bus Interface 
Logic 



Accumulator 
Registerts) 



Data Counteris) 



Stack Pointer 



Program Counter 



System Bus 



I/O Communication 
Serial to Parallel 
Interface Logic 



Programmable 
Timers 



ROM Addressing 

and 
Interface Logic 



I/O Ports 
(r>terface Logic 



Read Only 
Memory 



I 



I/O Ports 



Direct Memory 

Access Control 

Logic 



RAM Addressing 

and 
Interface Logic 



Read/Write 
Memory 



Figure 7-16. Logic Functions of the Z80 PIO 



Z80 PIO PINS AND SIGNALS 

Z80 PIO pins and signals are illustrated in Figure 7-17. Signals are very straightforward; therefore their functions 
will be summarized before we discuss device characteristics and operation. 

Let us first consider the PIO CPU interface. 

All data transfers between the PIO and the CPU occur via the Data Bus, which connects to pins DO - D7. 

For the PIO to be selected, a low input must be present at CE. There are two additional address lines. B/A SEL 
selects Port A if low and Port B if high. For the selected I/O port, C/D SEL selects a data buffer when low and a 
control buffer when high. Device select logic is summarized in Table 7-5. 



7-46 



Table 7-5. Z80 PIO Select Logic 



z 
oc 
o 
m 
v> 
o 

< 

Q 
< 

@ 



SIGNAL 


SELECTED LOCATION 


CE 


B/A SEL 


C/D SEL 






1 




1 
1 
X 



1 
. 
1 
X 


Port A data buffer 
Port A control buffer 
Port B data buffer 
Port B control buffer 
Device not selected 



Z80 PIO device control l ogic is not straightforward. Of the control signals output by the Z80 CPU, three are input to the 
PIO; M l. lORQ. and RD. WR is_not input to the PIO. Table 7-5 illustrates the way in which Z80 PIO interprets Ml, 
lORQ and RD. Observe that RD is being treated as a signal with two active states: low RD specifies a r ead operation, 
whereas high RD specifies a write operation. This does not conform to the CPU, which treats RD and WR as signals 
with a low active state only. 

Let us now look at the PIO external logic interface. 

AO - A7 rep resent the eight bidirectional I/O Port A lines; I/O Port A is supported by two control signals, A RDY 
and A STB. 

Similarly, I/ O Port B is implemented via the eight bidirectional lines BO - B7 and the two associated control lines 
B RDY and B STB. 

The I/O Port A and B control lines provide handshaking logic which we will describe shortly. 

Now consider interrupt control signals. 

lEI and lEO are standard daisy chain interrupt priority signals. When more than one PIO is present in a system, the 
highest priority PIO will have lEI tied to +5V and will connect its lEO to the lEI for the next highest priority PIO in the 
daisy chain: 



+ 5V 



X I ^ I ^ I \ I 



• No connection 



lEI 


PIO 

1 


lEO 





lEI 


PIO 


lEO 




n 





Highest 


Second 


Third 


Lowest 


(first) 


priority 


priority 


priority 


priority 









If you are unsure of daisy chain priority networks, refer to Volume 1 for clarification. 

INT is a standard interrupt request signal which is output by the Z80 PIO and must be con necte d as an input to the 
Z80 CPU interrupt request. Observe that there is no interrupt acknowledge line, since Ml and lORQ simultaneously low 
constitute an interrupt acknowledge and will thus be decoded by the Z80 PIO. 

Clock, power, and ground signals are absolutely standard. The same clock signal is used by the PIO and the Z80 
CPU. 

Observe that there is no Reset signal to the PIO. Ml low with both RD and lORQ high constitutes a reset. We will 
describe the effect of a Z80 PIO reset after discussing operating modes. 



7-47 




280 
PIO 





z^ 




=r 




^ 


-«s 





D3 
D4 
D5 
Ml 

jORQ 
RD 
B7 
B6 
B5 
84 
83 
82 
81 
80 
+ 5V 

JEJ 
INT 
- lEO 
BRDY 



PIN NAME DESCRIPTION 

DO - D7 Data Bus 

CE Device Enable 

8/A SEL Select Port A or Port B 

C/D SEL Select Control or Data 

Ml Instruction fetch machine cycle 

signal from CPU 

lORQ Input/Output request from CPU 

RD Read cycle status from CPU 

AO - A7 Port A Bus 

A RDY Register A Ready 

A STB Port A strobe pulse. 

80 - 87 Port 8 Bus 

8 RDY Register 8 Ready 

8 STB Port B strobe pulse 

lEI Interrupt enable in 

lEO Interrupt enable out 

INT Interrupt request 

<t>, + 5V,GND clock. Power and Ground 



TYPE 

Tristate, Bidirectional 

Input 

Input 

Input 

Input 

Input 

Input 

Tristate, Bidirectional 

Output 

Input 

Tristate, Bidirectional 

Output 

Input 

Input 

Output 

Output, Open-drain 



Figure 7-17. Z80 PIO Signals and Pin Assignments 



7-48 



o 

CD 
CO 
O 

< 

o 
< 

@ 



Z80 PIO OPERATING MODES 

To the programmer, a Z80 PIO will be accessed as four addressable locations: 



Data Bus 
D0-D7 



C 



:> 



C 



I/O Port A logic 



:> 



I/O Port A 
Data 



c 



:> 



I/O Port A 
A0-A7 



T^ 





1 


I/O Port A 
Control 




^ I' 


1 ■* 



I/O Port B logic 



^ 



I/O Port B 
Control 



I 



ASTB 
ARDY 



•BSTB 



-^«-BRDY 



N — ri/ 



I/O Port B 
Data 



<:;=> 



I/O Port B 
B0-B7 



I 
J 



By loading appropriate information into the Control register you determine the mode in which the I/O port is to 
operate. 

The Z80 PIO has operating modes which are equivalent to those of the 8255 PPI, plus an additional mode which 
the 8255 PPIdoes not have. However, 8255 PPI Mode provides 24 I/O lines, as against a maximum of 16 I/O lines 
available with the Z80 PIO. 

Zilog literature uses Mode 0, Mode 1, Mode 2, and Mode 3 to describe the ways in which the ZBO PIO can operate; in 
order to avoid confusion between mode designations as used by the ZBO PIO and the 8255 PPI, mode equivalences are 
given in Table 7-6. 

Table 7-6. Z80 PIO And 8255 Mode Equivalences 



Z80 PIO 


8255 PPI 


INTERPRETATION 


Mode 3* 


Mode 


Simple input or output 


Mode 


Mode 1 


Output with handshaking 


Mode 1 


Mode 1 


Input with handshaking 


Mode 2 


Mode 2 


Bidirectional I/O with handshaking 


Mode 3 


None 


Port pins individually assigned as con- 
trols 



'Special case of Mode 3 

Let us now look at the Z80 PIO modes in more detail. 

Output mode (Mode 0) allows Port A and/or Port B to be used as a conduit for transferring data to external logic. 
Figure 7-18 illustrates timing for Mode 0. An output c ycle is initiated when the CPU executes any Output instruction 
accessing the I/O port. The Z80 P IO do es not receive the WR pulse from the CPU, therefore it derives an equivalent sig- 
nal by ANDing RD • CE • C/D • lORO. 

This pseudo write pulse (WR* in Figure 7-18) is used to strobe data off the Data Bus and into the addressed I/O port's 
Output register. After the pseudo write pulse goes high, on the next high-to-low transition of the clock pulse O, the 
RDY control signal is output high to external logic. RDY remains high until external logic returns a low pul se o n the STB 
acknowledge. On the following high-to-low clock pulse $ transition, RDY returns low. The low-to-high STB transition 
also generates an interrupt request. 



7-49 



WR» \_ 


u\ 


1 


p^ J-L^i^LTi- 


' 1 /V 




\ 


HUKI UUIHUl 


I 




/ 


\ 


RDY 






c 


) 


^ 


\ \^ 


\ 


STB \ (jK 


Int 

WR*= 


RD . CE 


MODE (OUTPUT) TIMING 
. C/D • lORQ 


^ 





Figure 7-18. Mode (Output) Tinning 

The RDY and STB signal transition logic has b een designed to let RDY create STB. If you connect these two signals, the 
RDY low-to-high transition becomes the STB low-to-high transition and RDY is strobed high for one clock pulse only. 
This may be illustrated as follows: 



RDY 



STB 




PL. 



RDY = STB 




Timing for input mode (Mode 1) is illustrated in Figure 7-19. External logic initiates an input cycle by pulsing STB 
low. This lo w pu lse causes the Z80 PIO to load data from the I/O port pins into the port Input register. On the rising 
edge of the STB pulse an interrupt request will be triggered. 

On the falling edge of the O clock pulse which follows STB input high, RDY will be output low informing external logic 
that its data has been received but has not yet been read. RDY will remain low until the CPU has read the data, at which 
time RDY will be returned high. 

It is up to external logic to ensure that data is not input to the Z80 PIO while RDY is low. If external logic does in- 
put data to the ZBO PIO while RDY is low, then the previous data will be overwritten and lost — and no error status will 
be reported. 

In bidirectional mode (Mode 2), the control lines supporting I/O Ports A and B are both applied to bidirectional 
data being transferred via Port A; Port B must be set to bit control (Mode 3). 

Figure 7-20 illustrates timing for bidirectional data transfers. This figure is simply a combination of Figures 7-18 and 
7-19 where the A control lines apply to data output while the B control lines apply to data input. The o nly un ique 
feature of Figure 7-20 is that bidirectional data being output via Port A is stable only for the duration of the A STB low 
pulse. This is necessary in bidirectional mode since the Port A pins must be ready to receive input data as soon as the 
output operation has been completed. 

Once again, it is up to external logic to make sure tha t it con forms with the timing requirements of bidirectional mode 
operation. External logic must read output data while A STB is low. If external logic does not read data at this time, the 
data will not be read and the ZBO PIO will not report an error status to the CPU; there is no signal that external logic 
sends back to the ZBO PIO following a successful read. 



7-50 



Also, it is up to external logic to make sure that it transmits data to Port A only while B RDY is high and A RDY is low. If 
external logic tries to input data while the Z80 PIO is outputting data, input data will not be accepted. If external logic 
tries to input data before previously input data has been read, the previously input data will be lost and no error status 
will be reported. 



o 
m 

o 

< 
< 
© 



PORT INPUT — 
(8 BITS) — 




RD*= RD . Cf . 570" • lORQ 



Figure 7-19. Mode 1 (Input) Timing 




WR*= RD • CE • c7d . lORQ 



Figure 7-20. Port A, Mode 2 (Bidirectional) Timing 

Control mode (Mode 3) does not use control signals. You must define every pin of an I/O port in IVIode 3 as an in- 
put or an output pin. The section on programming the Z80 PIO explains how to do this. Timing associated with the ac- 
tual transfer of data at a single pin is as illustrated in Figures 7-1 8 and 7-1 9, ignoring the RDY and STB signals. If all the 
pins of a single port are defined in the same direction, then that port can be used for simple parallel input or output 
(without handshaking). 

Z80 PIO INTERRUPT SERVICING 

The ZBO PIO has a single interrupt request line via which it transmits interrupt requests to the CPU. 

An interrupt request can originate from I/O Port A logic, or from I/O Port B logic. In the case of simultaneous in- 
terrupt requests, I/O Port A logic has higher priority. 

An interrupt request may be created in one of two ways. We have already seen in our discussion of Modes 0, 1 and 2 
that appropriate control signal transitions will activate the interrupt request line; that is the first way in which an inter- 
rupt request may occur. In Mode 3 you can program either I/O port to generate an interrupt request based on the status 
of signals at individual I/O port pins; you can specify which I/O port pins will contribute to interrupt request logic and 
what the pin states must be for the interrupt request to occur. In a microcomputer system that has more than one ZBO 
PIO, interrupt priorities are arbitrated using daisy chain logic as we have already described. But there is a significant 
difference between priority arbitration within a ZBO system as compared to typical priority arbitration. Figure 7-21 ih 
lustrates interrupt acknowledge timing. 



7-51 



LASTT 
STATE 




lORQ 



lORQ AND Ml INDICATE 
INTERRUPT ACKNOWLEDGE 



lEI 



Figure 7-21. Interrupt Acknowledge Timing 

The Z80 PIO requires the CPU to execute an RETI instruction upon concluding an interrupt service routine. 

Following an interrupt, an acknowledged Z80 PIO continously scans the Data Bus whenever Ml is pulsed low. Until an 
RETI instruction's object code is detected, the acknowledged Z80 PIO will continuously output lEO low, thus disabling 
all lower priority Z80 PIOs. As soon as an RETI instruction's object code is detected on the Data Bus, the Z80 PIO will 
output lEO high, thus enabling lower priority Z80 PIOs. What this meansjs that interrupt priorities extend to the inter- 
rupt service routine as well as the interrupt request arbitration logic. Once an interrupt has been acknowledged, all 
lower priority interrupt requests will be denied until the acknowledged interrupt service routine has completed execu- 
tion and has executed an RETI instruction. However, higher priority interrupts can be acknowledged and in turn inter- 
rupt an executing service routine. This is identical to the priority arbitration logic which we described for the 8259 
PICU. 

You can, if you wish, enable lower priority interrupts by executing an RETI instruction before an interrupt service 
routine has completed execution. But this requires that you execute an RETI instruction in order to return from a 
subroutine within the interrupted service routine. This instruction sequence may be illustrated as follows: 

;START OF INTERRUPT SERVICE ROUTINE 



CALL 



ENABLE 



;ENABLE ALL INTERRUPTS AT PIO DEVICES 



RET 
ENABLE RETI 



;END OF INTERRUPT SERVICE ROUTINE 



If you simply executed an RETI instruction shortly after entering an interrupt service routine, you would make a hasty 
exit from the routine — before completing the tasks that have to be performed in response to the acknowledged inter- 
rupt, 

PROGRAMMING THE Z80 PIO 

You program the Z80 PIO by outputting a series of commands. 

Let us start by identifying command format. 

If the bit of a command is low, then the receiving I/O port logic will interpret the command as an interrupt vec- 
tor, with which it must respond to an interrupt acknowledge, assuming that the CPU is operating in interrupt Mode 2: 



7 6 5 4 3 2 1 



cn 



3-* 




"Bit No. 
Command Byte 

Interrupt vector specified 

Output these eight bits when 

an interrupt request is acknowledged 



7-52 



Do not confuse CPU interrupt modes with I/O port modes; they have nothing in common. 

In order to define an I/O port's mode you must output a Control code to the I/O port's Control buffer. This is the 
Control code format: 



765432 10^ ^ 

I I |x|><h h M hh ^ 



• Bit No. 
Control Code 



Mode Select Code 
Don't Care 

00 Output, Mode 

01 Input, Mode 1 

10 Bidirectional, Mode2 

1 1 Control, Mode 3 



Z 
cc 
o 
m 

(A 

o 

< 
< 



Observe that the same address, the I/O Port A or B Control buffer address, is used when outputting a Control code, an 
interrupt vector, or a mode select. The low-order four bits of the Control code determine the way in which the Control 
code will be interpreted. The following Control code will enable or disable interrupts: 

7 6 5 4 3 2 10 

I |x|x|x|o|o|in 



Interrupt enable control 
Don't Care 

Disable interrupts 

1 Enable interrupts 




LD 


C, (PORT AC) 


LD 


A,OCFH 


OUT 


(C),A 


LD 


A,3AH 


OUT 


(C),A 



If a Mode Select Control code is output specifying that an I/O port will operate in Mode 3, then the next byte 
output is assumed to be a pin direction mask. 1 identifies an input pin, whereas identifies an output pin. Here is a 
sample instruction sequence: 

;LOAD PORT A CONTROL ADDRESS INTO REGISTER C 
;LOAD MODE 3 SELECT INTO ACCUMULATOR 
;OUTPUT TO PORT A CONTROL REGISTER 
iDEFINE PINS 5, 4, 3 AND 1 AS INPUTS, 
:PINS 7, 6, 2 AND AS OUTPUTS 

If you set an I/O port to Mode 3, then you can define the conditions which will cause an interrupt request; you 
do this by outputting the following interrupt Control code: 



fnterrupt control word 

1 if interrupt select mask follows 

otherwise 

1 high input on selected pins Is active 
low input on selected pins is active 

1 AND selected pins for Interrupt 

OR selected pins for interrupt 

1 Enable interrupts 
Disable interrupts 




7-53 



When you output an interrupt Control code, as illustrated above, if bit 4 is 1. Z80 PIO logic will assume that the next 
Control code output is an interrupt mask. An interrupt mask selects the pins that will contribute to interrupt request 
logic. A bit selects a pin, while a 1 bit deselects the pin. 

Combining the various Control codes that have been described we can now illustrate a typical sequence of instructions 
for accessing a Z80 PIO. Assume that PIO I/O port addresses are: 

Port A data 4 

Port A command 5 

Port B data 6 

Port B command 7 

We are going to set I/O Port B to Mode 3, with an interrupt request triggered by either pin 6, 3 or 2 high. Pins 6, 3, 2 
and 1 will be input pins, while pins 7, 5, 4 and are outputs. The Port B interrupt vector will be 04. Port A will be a 
bidirectional I/O port with an interrupt vector of, 02. Here is the initialization instruction sequence: 

;SET PORT A TO MODE 2 

:OUTPUT INTERRUPT VECTOR 

ISET PORT B ADDRESS IN C 
;SET PORT B TO MODE 3 

;OUTPUT PIN DIRECTION MASK 

;OUTPUT INTERRUPT VECTOR 

;OUTPUT INTERRUPT CONTROL WORD 

;OUTPUT INTERRUPT MASK 



THE Z80 CLOCK TIMER CIRCUIT (CTC) 

The Z80 Clock Timer Circuit is a programmable device which contains four sets of timing logic. Each set of tim- 
ing logic can be programmed independently as an interval timer or an external event counter. 

The master Z80 system clock is used by interval timer logic. A time out may be identified by an interrupt request. 

An external signal is used to trigger decrement logic when the timer is functioning as an event counter. An interrupt 
may be requested when the predetermined number of events count out. 

If you compare the Z80 CTC with the 8253 Counter/Timer described in Chapter 4, you will see that the Z80 CTC 
has four sets of counter/timer logic as compared to the three sets of the 8253; however the 8253 has more pro- 
grammable options. In addition to functioning as an event counter or an interval timer, the 8253 can be programmed to 
generate a variety of square vyaves and pulse output signals. 

The Z80 CTC is fabricated using N-channel depletion load technology. It is packaged as a 28-pin DIP. All pins are 
TTL-level compatible. 

Z80 CTC FUNCTIONAL ORGANIZATION 

Before we examine pins, signals, and operating characterics of the Z80 CTC in detail, let us take an overall look 
at device logic. 

There are four counter/timer logic elements in a Z80 CTC; each is referred to as a "channel". 



LD 


A,8FH 


OUT 


(5),A 


LD 


A,2 


OUT 


(5),A 


LD 


C,7 


LD . 


A,OCFH 


OUT 


(C),A 


LD 


A,4EH 


OUT 


(C),A 


LD 


A, 4 


OUT 


(C),A 


LD 


A,0B7H 


OUT 


(C),A 


LD 


A.0B3H 


OUT 


(C),A 



7-54 



Each of the four counter/timer channels may be visualized as consisting of three 8-bit registers and two control 
signals. This may be illustrated as follows: 



< 
ea 

UJ 

z 

DC 

o 

GO 
W 

o 

< 
o 
< 

@ 




8-bit 

Time Constant 

Register 



\7 



Channel only 



CLK/TRG 




Channels 0, 1. and 2 only 



An initial counter or timer constant is loaded into the Time Constant register. The value in the Time Constant 
register is maintained unaltered until you write a new value into this register. 

The initial Timer Constant is loaded into the Down Counter register at the beginning of a counter or timer opera- 
tion; the contents of the Down Counter register are decremented. You can at any time read the contents of the Down 
Counter register in order to determine how far a time interval or event counting sequence has progressed. 

The Channel Control register contains a Control code which defines the channel's programmable options. There 
are four Control registers, one for each of the four channels. Thus one channel's operations in no way influence opera- 
tions for any other channel. 

There is an Interrupt Vector register which is addressed as though it were part of channel logic. This register 
contains the address which is transmitted by the Z80 CTC upon receiving an interrupt acknowledge. The Z80 

CTC assumes that the Z80 CPU is operating in Interrupt mode 2 — in which mode the device requesting an interrupt 
responds to an acknowledge by providing the second byte of a subroutine address which the CPU will Call. For details 
refer to our earlier discussion of the Z80 CPU. 

Z80 CTC PINS AND SIGNALS 

Z80 CTC pins and signals are illustrated in Figure 7-22. 

DO - D7 is the bidirectional Data Bus via which parallel data is transferred between the CPU and any register of the 
ZBO CTC. 

CE is the master chip select signal for the ZBO CTC. This signal must be low for the device to be selected. 



7-55 



While CE is low, CSO and CS1 are used to select one of the four counter/timer logic channels as follows: 
CS1 CSO Channel 















1 


1 


1 
1 




1 


2 
3 




lORQ 

RD 

RESET 

lEI 

lEO 

INT 

CE 

CSO, CS1 

<t>, + 5V, GND 



External Clock or timer trigger 



Zero Count or timeout indicator 

Instruction fetch machine cycle 

signal from CPU 

Input/Output request from CPU 

Read cycle status from CPU 

Device Reset 

Interrupt enable in 

Interrupt enable out 

Interrupt request 

Device enable 

Register select 

Clock, pov/er and ground 



TYPE 

Bidirectional, tristate 



Output 



Input 



Input 

Input 

Input 

Input 

Output 

Output, Open-drain 

input 

Input 



Figure 7-22. Z80-CTC Signals and Pin'Assignnnents 



7-56 



CSO and CS1 select registers associated with counter/timer logic, to be accessed by read and write operations. The ac- 
tual register which will be accessed is determined as follows: 



o 

< 
< 



Write to Channel 



7 6 5 4 3 2 1 

nxi 



H 



■ Bit No. 

■ Data v;ritten I 

• X = 0, channel = 
Select Interrupt 
Vector 

•X = 1, select Channel 
Control register on 
first access. 



Read from channel 



Dovjn Counter 



* If Y = ^ Select Tinne Constant register 

on next write 
If Y = 1 » Select Channel Control register 

again on next write 
(If Channel = 0, select on next 
write according to X.) 

As the illustration above would imply, the Down Counter register is the only location of any channel whose contents 
can be read. All other registers are write only locations. 

When you write to a channel, bits and 2 of the data byte being written determine the data destination as follows: 

1) If bit is and you are selecting channel 0, then the data is written to the Interrupt Vector register. 

2) If bit is and you select channel 1, 2 or 3, the data destination is undefined. 

3) If bit is 1, then on the first access of any channel the data will be written to the Channel Control register. 

4) If within the data byte written to a Channel Control register bit is 1 and bit 2 is 0, then the next data byte written 
to this channel will be loaded into the Time Constant register, irrespective of whether bit is or 1 . The data writ- 
ten will be interpreted as a time constant; select logic will immediately revert to selecting the Channel Control 
register or the Interrupt Vector register on the next write, depending on the condition of bit of the next data byte. 

Ml, lORQ and RD are three control signals input to theZSO CTC. Combinations of these three control signals control 
logic within the Z80 CTC, as described for the Z80 PIO. An exc eptio n is the device Reset. The Z80 CTC has its 

own RESET input. The PIO decodes a Reset when Ml is low while iORQ and RD are high. With_the exception of the 
RESET function, Table 7-4 defines the manner in which the Z80 CTC interprets Ml, IORQ, and RD signals. 

Interrupt logic has three associated signals: lEI, lEO and INT. These signals operate exactly as described for the 
Z80 PIO. 

The Z80 CTC requests an interrupt with a low INT output. 

lEI and lEO are used to implement daisy chain priority interrupt logic as described for the PIO. 

Each of the four counter/timer channels has a CLK/TRG input control. This signal can be used to trigger timer logic; 
it is also used as a decrement control by counter logic. 

Counter/timer logic channels 0, 1 and 2 have a ZC/TO output. This signal is pulsed high on a time out or a count out. 



When a low input is applied to the RESET pin, the Z80 CTC is reset. At this time all counter/timer logic is stopped, 
INT is output high, lEO is output at the IE! level and the Data Bus is floated. Register contents are not cleared during a 
reset. " 

Z80 CTC OPERATING MODES 

The ZBO CTC is accessed by the CPU as four I/O ports or four rnemory locations. Timing for any CTC access con- 
forms to descriptions given earlier in this chapter for the CPU. 

Let us begin by looking at a counter/timer operating as a timer. 



7-57 



Using an appropriate Control code (described later) you select Timer mode for the channel and specify that an initial 
time constant is to follow. 

You load an initial constant into the Time Constant register, after which timer operations begin. 

You have the option of using the CLK/TRG input to start the timer, in which case timer logic is initiated by external 
logic. The alternative is to initiate the timer under program control, in which case the timer starts on the clock pulse 
following the Time Constant register being loaded. 

When timer operations begin, the Time Constant register contents are transmitted to the Down Counter register. The 
Down Counter register contents are decremented on every 16th system clock pulse, or on every 256th system clock 
pulse. You make the selection via the Control code. Assuming a 500 nanosecond clock, therefore, the timer will decre- 
ment the Down Counter register contents every 8 microseconds, or every 128 microseconds. 

When timer logic decrements the Down Counter register contents from 1 to a time out occurs. At this time ZC/TO is 
pulsed high, the Time Constant register contents are reloaded into the Down Counter register and timer logic starts 
again. Thus timer logic is free running; once started, the timer will run continuously until stopped by an appropriate 
Control code. 

Here is a timing example for a timer started under program control and decrementing the Down Counter register on ev- 
ery 16th clock pulse: 



ZC/TO 



INT 




Output 


Output 


Time Constant 


Decrement 


Control 


Initial 


to Down Counter 


Down Counter 


Code 


Time 


Register, Start 


Register 




Constant 


Timer 





Down Counter Register 
Decrements from 1 to 0. 
Retoad Down Counter from 
Time Constant Register and 
restart timer 



Here is a timing example for a timer whose operations are initiated by CLK/TRG, where the Down Counter register con- 
tents are decremented on every 256th clock pulse: 



255 256 1 



255 256 1 



255 256 



CLK/TRG 



ZC/TO 



INT 




Output 


Output 


Tims 


Decrement 


Dov^n Counter 


Restart 


Control 


Initial 


Constant 


Down Counter 


Register decrements 


Timer 


Code 


time 


to Down 


Register 


• from 1 to 0. 






constant 


Counter 

Register, 

Start 

Timer 




Reload Down 

Counter from 

Time Constant 

register 





7-58 



Observe that every time out is marked by a ZC/TO high pulse. INT is also output low providing interrupt logic is enabled 
at the channel. 

In the illustration above CLK/TRG is shown as a high true signal. You can specify CLK/TRG as a low true signal via the 
Channel Control code; the timer will be initiated as follows: 



I — \__J~~Ucd — A_r 



CLK/TRG 




< 

Q 

< 



For exact timing requirements see the data sheets at the end of this chapter. 

■ You can at any time write new data into the Time Constant register. If you do this while the timer is running, nothing 
happens until the next time out; at that time the new Time Constant register contents will be transferred to the Down 
Counter register and subsequent time intervals wjN be computed based on the new Time Constant register contents. 

If you are unfortunate enough to output data to the Time Constant register while a time out is in progress and the Time 
Constant register contents are being transferred to the Down Counter register, then an undefined value will be loaded 
into the Down Counter register; however, following the next time out the new value in the Time Constant register will 
apply; that is to say, there will only be one undefined time interval. 

Let us now look at a counter/timer operating as a counter. 

Using an appropriate Control code (described later) you select Counter mode for the channel and specify that an initial 
time constant is to follow. 

You load an initial constant into the Time Constant register, after which counter operations begin. 

When counter operations begin, the Time Constant register contents are transmitted to the Down Counter register. The 
Down Counter register contents are decremented every time the CLK/TRG input makes an active transition. Counter 
logic begins on the first active transition of CLK/TRG following data being loaded into the Time Constant register. The 
active transition of CLK/TRG may be selected under program control as iow-to-high or high-to-!ow. 

When counter logic decrements the Down Counter register contents from 1 to 0, a count out occurs. At this time the 
ZC/TO signal is pulsed high; an interrupt request occurs, providing the channel's interrupt logic has been enabled. The 
Time Constant register contents are reloaded into the Down Counter register and counter operations begin again. That 
is to say, counter logic is free running and yvjil continue to re-execute until specifically stopped by an appropriate Con- 
trol code. Counter logic timing may be illustrated as follows: 



.AJIAA.-.AAA. 



JUUUL 



CLK/TRG 



ZC/TO 




Output Output Start 
Control Initial Counter 

Code Time 

Constant 



Decrement Dovi^n Counter 

Dov;n Counter register 

Register ' decrements 

from 1 to 



7-59 



Z80 CTC INTERRUPT LOGIC 

Every Z80 CTC channel has its own interrupt logic. A channel's interrupt logic generates an interr upt request 
when the channel counts out or times out. All interrupt requests are transmitted to the CPU via the INT output. 
This is true if one, or more than one channel is requesting an interrupt. If more than one channel is requesting an 
interrupt, then priorities are arbitrated as follows: 

Highest Priority Channel 

Channel 1 

Channel 2 
Lowest Priority Channel 3 

Every channel's interrupt logic can be individually enabled or disabled under program control. 

The Z80 CTC device's overall interrupt logic is identical to that which we have already described for the Z80 
PIO. 

The interrupt request is transnnitted to the CPU via a low INT signal. 



The CPU acknowledges the interrupt by outputting Ml and lORQ low as illustrated in the data sheets at the end of this 
chapter. 

The device requesting an interrupt which is highest in the daisy chain acknowledges the interrupt. Presuming this is a 
Z80 CTC, the CTC places its interrupt vector on the Data Bus; it is assumed that the CPU is operating in Interrupt mode 
2. The Z80 CTC immediately outputs lEO low, disabling all devices below it in the daisy chain. 

When an RETI instruction is executed, Z80 CTC logic sets lEO high again. 

For more information on Z80 interrupt logic refer to discussions of this subject given earlier in the chapter for the Z80 
CPU and the PIO. 

PROGRAMMING THE Z80 CTC 

These are the steps required to program a ZBO CTC: 

1) Output an interrupt vector once, when initializing the ZBO CTC. 

2) For each active counter/timer channel, output one or more Control codes. Control codes are used initially to 
set counter/timer operating conditions and to load the Time Constant register. Subsequently Control codes 
are used to start and stop the counter/timer, or to change the initial time constant. 

The interrupt vector is written to a counter/timer by outputting a byte of data to counter/timer channel with a in the 
low order bit. The interrupt vector may be illustrated as follows: 



7 6 5 4 3 2 1 



1— . 



OHs 



rr*— 





■ Bit No. 

■ Interrupt Vector' 

Must be to identify Interrupt Vector 
Ignored by Z80 CTC v/hich substitutes 
bits as follov/s: 
for Channel interrupt 

1 for Channel 1 interrupt 

1 for Channel 2 interrupt 
1 1 for Channel 3 interrupt 

Address bits stored 



7-60 



The Control code which must be output to each active channel will be interpreted as illustrated in Figure 7-23. 



(A 
< 

a 

Z 
cc 
o 

00 
(0 

o 

< 
o 

< 

@ 



7 6 5 4 3 2 10 

il I I I 1 I I 



ii n il ji n il i> ii 




Must be 1 to identify data as a Control code 



RESET 1 stops channel immediately or 

leaves it running 
LOAD 1 Next data output is a time constant to be loaded into 
the Time Constant register. If counter/timer is not 
running, do not start until time constant has been written. 

No time constant follows. 
TRIGGER 1 If timer is stopped, start on CLK/TRG ) Timer Mode 

If timer is stopped, start on O » Only 

SLOPE 1 CLK/TRG positive edge triggered 

CLK/TRG negative edge triggered 
RANGE 1 Decrement Down counter every 256th ^ pulse.J Timer Mode 

Decrement Down counter every 16th 4> pulse. J Only 
MODE 1 Counter mode 

Timer mode 
IE 1 Enable channel interrupt 

Disable channel interrupt 



Figure 7-23. Z80 CTC Control Code Interpretation 

Bit must be 1 to identify the data as a Control code. If bit is 0, then the data is interpreted as an interrupt vector — 
providing Channel is addressed; the data is undefined otherwise. 

Bit 1 is used to stop the channel when it is running. If bit 1 is 0, then every time the channel times out the Down 
Counter register is immediately reloaded from the Time Constant register contents and channel operations restart ac- 
cording to current options. If bit 1 is 1 , the channel stops immediately; the ZC/TO output is inactive and channel inter- 
rupt logic is disabled. The channel must be restarted by outputting a new Control code. 

Bit 2 is used to output time constants. If bit 2 is 1 , then the next data output to the channel will be interpreted as a time 
constant. If bit 2 is 0, then the next data output to the channel will be interpreted as another Control code, or an inter- 
rupt vector